JP2000183155A - Method of forming grooved element isolation region and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a method of forming a grooved element isolation region which can surely prevent generation of junction leakage even when deviation is generated in the alignment for formation of a contact hole. SOLUTION: A method of forming a grooved element isolating region comprises the processes for forming a mask layer 12 on the surface of a semiconductor substrate 10, forming an opening to the mask layer, subsequently forming a groove 13 to the semiconductor substrate exposed at the bottom part of the opening, embedding the groove with a first insulating material layer 15 by depositing the first insulating material layer 15 on the mask layer including the inside of the groove, depositing a second insulating material layer 16 on the first insulating material layer and mask layer in the groove, executing the flattening process at least to the second insulating material layer, matching the level of the top surface of mask layer with the top surface of the second insulating material layer 16, and thereafter exposing the surface of semiconductor substrate by removing the mask layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a groove-type element isolation region, that is, an element isolation region having a trench structure, and a method of manufacturing a semiconductor device to which such a method of forming a groove-type element isolation region is applied. .

[0002]

2. Description of the Related Art In a silicon semiconductor device, an element isolation region composed of a silicon oxide film layer is formed on a silicon semiconductor substrate in order to electrically isolate a transistor element. The element isolation region is conventionally formed by the LOCOS method. However, in the LOCOS method, a so-called bird's peak phenomenon occurs in which the formation region of the silicon oxide film layer isotropically spreads in the XY directions. As a result, it has become difficult to achieve both miniaturization and element isolation characteristics of semiconductor devices.

On the other hand, studies on a method of forming a groove-type element isolation region, that is, an element isolation region having a so-called shallow trench structure, have been earnestly advanced. An outline of a conventional method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region will be described with reference to FIGS. 15 to 17 which are schematic partial cross-sectional views of a silicon semiconductor substrate and the like.

[Step-10] First, a pad oxide film 111 having a thickness of about 8 nm is formed on the surface of the silicon semiconductor substrate 10 by a thermal oxidation method. Note that the pad oxide film is formed for the purpose of relaxing stress between the SiN layer to be formed next and the silicon semiconductor substrate. After that, the thickness 15
An about 0 nm SiN layer 112 is formed on the entire surface. Then, a resist layer (not shown) is formed on the SiN layer 112 based on the lithography technique, and the SiN layer 112 and the pad oxide film 111 are etched using the resist layer as an etching mask. An opening is formed in the opening. Further, the silicon semiconductor substrate 10 is etched to form a groove 113 in the silicon semiconductor substrate 10. Then, the silicon oxide film 114 is formed on the inner surface of the groove 113 by removing the resist layer and thermally oxidizing the surface of the silicon semiconductor substrate 10 exposed in the groove 113. This state is shown in FIG.

[Step-20] Thereafter, an insulating material layer 115 made of SiO ₂ is deposited on the entire surface including the inside of the groove 113 by a CVD method. Next, the SiN layer 11 is formed by an etch back method or a chemical mechanical polishing method (CMP method).
2 is removed and the surface is planarized (FIG. 15).
(B)). At this time, the SiN layer 112 functions as a stopper layer. Then, by removing the SiN layer 112 by a wet etching method, the groove-type element isolation region 11 having a shallow trench structure in which the groove 113 is filled with an insulating material layer 115 made of SiO _2.
7 (see FIG. 15C).

[Step-30] Thereafter, the pad oxide film 11 is formed.
1 is removed, a gate insulating film 20 is formed by thermally oxidizing the surface of the silicon semiconductor substrate 10, a gate region 23 is formed by a known method, and a low concentration impurity region 24 is formed by ion implantation. Form. The gate region 23 includes, for example, a polysilicon layer 21 containing an impurity and an offset film 22 made of SiN formed thereon. After that, Si
An N layer is deposited by a CVD method, and the SiN layer is etched back to form a Si layer on the side wall of the gate region 23.
The gate sidewall 25 made of N is formed (FIG. 1).
6 (A)).

[Step-40] Next, after a high-concentration impurity region is formed on the surface of the silicon semiconductor substrate 10 by an ion implantation method, an ion-implanted impurity is activated to form a source / drain region 26. (See FIG. 16B).

[Step-50] Thereafter, an interlayer insulating layer 27 made of SiO ₂ is deposited on the entire surface, and the interlayer insulating layer 27 above the source / drain region 26 is etched to form an opening 28 (FIG. 17). (A)). Then, a conductive material is formed by sputtering on the interlayer insulating layer 27 including the inside of the opening 28, and the wiring 29 is formed by patterning the conductive material (FIG. 17).
(B)). The source / drain region 26 and the wiring are electrically connected by a contact hole 29A. As described above, a semiconductor device including a MOS-FET type transistor element can be obtained.

As described above, by forming the groove-type element isolation region 117 in the silicon semiconductor substrate 10, it is possible to prevent the phenomenon that the region where the silicon oxide film layer is formed isotropically expands in the XY directions. In addition, it is possible to achieve both miniaturization of a semiconductor device and element isolation characteristics.

[0010]

SUMMARY OF THE INVENTION However, semiconductors
As device miniaturization and integration progress, contact holes
When forming the opening 28 to form 29A,
The problem of misalignment in the lithography process is greater than before
It is a serious problem. Opening 28 in interlayer insulating layer 27
When misalignment occurs during the formation of_TwoOr
The opening 28 is formed by etching the interlayer insulating layer 27 made of
When formed, the groove-type element isolation region 117 is made of SiO._TwoConsisting of
Therefore, the shoulders of the groove-type element isolation regions 117 are simultaneously etched.
It will be. This region is indicated by an arrow in FIG.
Marked with "X". As a result, as shown in FIG.
When the contact hole 29A is formed,
The hole 29A extends to the inside of the silicon semiconductor substrate 10.
And the junction leaks. Note that the interlayer insulating layer 27 is made of S
In the case of using iN, the relative dielectric constant of SiN is SiO _Two
Higher, the capacitance between the wires would increase.
There is a problem. Further, the groove 113 is made of an insulating material made of SiN.
When embedded by a material layer, the capacity of the element isolation region
Problems such as an increase in the amount of the silicon semiconductor substrate 1
When crystal defects occur due to interface states and film stress at 0
Such a problem arises. Therefore, it is not necessary to embed the groove 113.
As materials for forming the edge material and the interlayer insulating layer 27,
Currently, SiO _TwoIt is most practical to use a system material.

Therefore, an object of the present invention is to provide a semiconductor device in which a misalignment occurs in a lithography process for forming a contact hole, the contact hole protrudes from a source / drain region, and the contact hole extends over a groove-type element isolation region. Another object of the present invention is to provide a method of forming a groove-type element isolation region capable of reliably preventing a junction leak from occurring, and a method of manufacturing a semiconductor device to which the method of forming a groove-type element isolation region is applied.

[0012]

In order to achieve the above object, a method of forming a trench type element isolation region according to the present invention comprises the steps of (a) forming a mask layer on the surface of a semiconductor substrate; Forming an opening in the layer and subsequently forming a groove in the semiconductor substrate exposed at the bottom of the opening; and (c) depositing a first insulating material layer on the mask layer including the inside of the groove, Embedding with a first insulating material layer; (d) depositing a second insulating material layer on the first insulating material layer in the groove and on the mask layer; Is subjected to a planarization process, and the top surface of the mask layer and the second
Matching the level of the top surface of the insulating material layer of
(F) removing the mask layer and exposing the surface of the semiconductor substrate, whereby the groove formed in the semiconductor substrate, the first insulating material layer filling the groove, and the first A groove-type element isolation region including a second insulating material layer formed on the insulating material layer is formed.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises the steps of (a) forming a mask layer on a surface of a semiconductor substrate, and (b) forming an opening in the mask layer. Forming a groove in the semiconductor substrate exposed at the bottom of the opening; and (c) depositing a first insulating material layer on a mask layer including the inside of the groove and filling the groove with the first insulating material layer. (D) depositing a second insulating material layer on the first insulating material layer in the groove and on the mask layer; and (e) performing a planarization process on at least the second insulating material layer. Applying the same to the level of the top surface of the mask layer and the level of the top surface of the second insulating material layer; and (f) removing the mask layer to expose the surface of the semiconductor substrate, thereby forming the semiconductor substrate. Groove, a first insulating material layer filling the groove, and a portion on the first insulating material layer Forming a trench isolation region comprising a second insulating material layer which is formed,
(G) a step of forming a transistor element on a semiconductor substrate surrounded by a groove-type element isolation region; and (h) an interlayer insulating layer made of a material having an etching rate higher than that of the material forming the second insulating material layer. Is formed over the entire surface, an opening reaching the transistor element is formed in the interlayer insulating layer based on an etching method, and then the opening is filled with a conductive material to form a contact hole reaching the transistor element in the interlayer insulating layer. Performing the steps of: Note that when the etching rate of the material forming the second insulating material layer is 1, the etching rate of the material forming the interlayer insulating layer is desirably 5 or more, preferably 10 or more. Here, the etching rate means the etching rate in the normal direction of the semiconductor substrate.

According to the method of forming a groove type element isolation region or the method of manufacturing a semiconductor device of the present invention (hereinafter sometimes collectively referred to as the method of the present invention), a groove formed in a semiconductor substrate and a groove formed in a semiconductor substrate are formed. A groove-type element isolation region including the buried first insulating material layer and a second insulating material layer formed over the first insulating material layer can be formed. In addition, in step (e), at least the second insulating material layer is subjected to a planarization process so that the level of the top surface of the mask layer matches the level of the top surface of the second insulating material layer. When the mask layer is removed and the surface of the semiconductor substrate is exposed, the shoulder of the groove-shaped element isolation region is formed not only of the top surface but also at least the upper part of the side surface from the second insulating material layer. Become.

Therefore, in the method of forming the groove-type element isolation region according to the present invention, if the second insulating material layer is made of a material having an etching rate lower than that of the material forming the interlayer insulating layer, In the method of manufacturing a semiconductor device, since the second insulating material layer is formed from a material having an etching rate lower than that of the material forming the interlayer insulating layer, misalignment occurs in a lithography step when an opening is formed in the interlayer insulating layer. Is generated, and even if the opening is formed over the groove-type element isolation region by etching the interlayer insulating layer, the groove-type element separation region is not etched. Therefore, when the contact hole is formed, it is possible to reliably avoid the problem that the contact hole extends to the inside of the silicon semiconductor substrate and a junction leak occurs.

In the method of the present invention, the method of depositing the first insulating material layer in the step (c) includes the steps of:
Preferably, it is based on Method D. In the case where the first insulating material layer is formed by a normal conformal, that is, a CVD method capable of obtaining an isotropic deposition state, the groove may not be filled with the first insulating material layer having a sufficient thickness. When such a phenomenon occurs, a planarization process is performed on the second insulating material layer so that the level of the top surface of the mask layer matches the level of the top surface of the second insulating material layer, and then the mask layer is removed. As shown in FIG. 13A, there arises a problem that the first insulating material layer in the groove is exposed and the first insulating material layer is exposed at the shoulder of the groove type element isolation region. There is a fear. Alternatively, since the thickness of the first insulating material layer deposited in the narrow groove portion generally tends to be larger than that in the wide groove portion, the top surface of the mask layer and the second insulating material layer Even when trying to match the level of the top surface, the second insulating material layer may not remain above the groove, as schematically shown in FIG.

The plasma generation method in the high-density plasma CVD method includes, for example, an ECR method, an ICP method, and a helicon method. In the high-density plasma CVD method, it is preferable to apply a bias to the semiconductor substrate. Note that by employing the high-density plasma CVD method, the deposition rate of the first insulating material layer in the horizontal direction becomes faster than the sputter etching rate in the horizontal direction. That is, the first
The insulating material layer recedes without being deposited in the horizontal direction. It is desirable that the relationship between the sputter etching rate SE in the vertical direction and the deposition rate DP in the vertical direction satisfies SE ≦ DP ≦ 10SE, preferably 2SE ≦ DP ≦ 5SE.

Further, the method of the present invention preferably includes a step of etching back the first insulating material layer between the step (c) and the step (d). Etching back of the first insulating material layer can be performed based on, for example, a wet etching method using hydrofluoric acid, or can be performed based on a dry etching method using an etching gas. The method of the present invention including the former etch back method based on the wet etching method is referred to as a method according to the first embodiment of the present invention for convenience. On the other hand, the method of the present invention including the latter etch-back method based on the dry etching method is referred to as a method according to the second aspect of the present invention for convenience. In the method according to the first or second aspect of the present invention,
When etching back the first insulating material layer, it is preferable to etch back the first insulating material layer so that at least a part of the side surface of the mask layer is exposed and the side wall of the groove is not exposed.

Further, the method of the present invention preferably includes a step of partially exposing the top surface of the mask layer having a predetermined width between the step (d) and the step (e). . If the second insulating material layer and the first insulating material layer on the wide mask layer are not removed, it may be difficult to uniformly planarize the second insulating material layer in the next step. .
Here, if the minimum exposure width for forming the resist layer based on the lithography technique is L ₀ (μm), and the width of the fogging region in consideration of the margin for misalignment is L ₁ (μm) on the left and right, L ₀ + 2L ₁ ( μm) is preferably a predetermined width.

In the method of the present invention, the flattening treatment in the step (e) may be performed based on an etch-back method, but is preferably performed based on a chemical-mechanical polishing method (CMP method). At this time, it is preferable to perform a planarization process so that the first insulating material layer below the second insulating material layer in the groove is not exposed. Note that “to at least perform the planarization process on the second insulating material layer” means not only to perform the planarization process on the second insulating material layer but also to perform the planarization process on the mask layer. Means that. Further, the level of the top surface of the mask layer and the level of the top surface of the second insulating material layer may be slightly inconsistent due to the planarization process. It is included in the concept that it is in agreement with the level of the top surface of the material layer.

In the method of forming a trench type element isolation region according to the present invention, the mask layer is made of polysilicon, the first insulating material layer is made of silicon oxide (SiO ₂ ), and the second insulating material layer is made of silicon oxide (SiO ₂ ). It is preferable to be composed of silicon nitride (SiN). In the method of manufacturing a semiconductor device according to the present invention, the mask layer is made of polysilicon, the first insulating material layer is made of silicon oxide (SiO ₂ ), and the second insulating material layer is made of silicon nitride (SiN). ), And the interlayer insulating layer is preferably made of a silicon oxide (SiO ₂ ) -based material. Here, as a silicon oxide (SiO ₂ ) -based material, LTO (Low Temperature Oxide, low-temperature CVD-Si) is used.
O ₂ ), HTO (High Temperature Oxide, low temperature CVD)
-SiO ₂ ), plasma CVD-SiO ₂ , HDP / CV
Not only SiO ₂ including D-SiO ₂ but also BPSG, PS
G, BSG, AsSG, PbSG, SbSG, NSG,
Examples thereof include SOG, organic SOG, SiOF, and a stack of these materials.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings based on embodiments of the present invention (hereinafter, abbreviated as embodiments).

(Embodiment 1) Embodiment 1 relates to a method of forming a trench-type element isolation region and a method of manufacturing a semiconductor device according to the first aspect of the present invention. That is, the first insulating material layer is etched back by a wet etching method using hydrofluoric acid. The mask layer is made of polysilicon, the first insulating material layer is made of silicon oxide (SiO ₂ ), the second insulating material layer is made of silicon nitride (SiN), and the interlayer insulating layer is made of silicon oxide. (SiO ₂ )
It is composed of A planarization process is performed on the second insulating material layer, and the planarization process is performed by a chemical mechanical polishing method (CM).
P method). Hereinafter, a method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region according to the first embodiment will be described with reference to FIGS. 1 to 6 which are schematic partial cross-sectional views of a silicon semiconductor substrate and the like.

[Step-100] First, a mask layer 12 is formed on the surface of a semiconductor substrate composed of a silicon semiconductor substrate 10. That is, a pad oxide film 11 having a thickness of about 8 nm is formed on the surface of the silicon semiconductor substrate 10 by a thermal oxidation method.
Incidentally, the pad oxide film 11 is used as a mask layer 1 in a later step.
2 has a function as an etching stopper when removing 2. Examples of the thermal oxidation method include a method in which the silicon semiconductor substrate 10 is heated to about 850 ° C. in a dry oxygen gas atmosphere, but is not limited to such a method. Then, the reduced pressure CV under the conditions exemplified in Table 1 below
By the method D, a mask layer 12 made of polysilicon having a thickness of about 150 nm is formed on the entire surface.

[0025]

[Table 1] Source gas: SiH ₄ = 400 sccm Temperature: 625 ° C Pressure: 20 Pa

[Step-110] Next, an opening is formed in the mask layer 12, and subsequently, a groove 13 is formed in the silicon semiconductor substrate 10 exposed at the bottom of the opening. Specifically, a resist layer (not shown) is formed on the mask layer 12 based on a lithography technique, and the mask layer 12 and the pad oxide film 11 are used as an etching mask using the resist layer.
Is etched to form openings in the mask layer 12 and the pad oxide film 11. And further, the silicon semiconductor substrate 1
0 is etched to form a groove 13 having a depth of about 0.3 μm in the silicon semiconductor substrate 10. After that, the resist layer is removed, and the silicon semiconductor substrate 10 exposed in the groove 13 is removed.
By thermally oxidizing the surface of the mask layer 12 and the top surface and side surface of the mask layer 12 made of polysilicon at about 1000 ° C., the inner surface of the groove 13 and the top surface and side surface of the mask layer 12 have a thickness of about 10 nm. Of silicon oxide film 14 is formed. This state is shown in FIG. If the trench 13 is filled with a first insulating material layer made of SiO ₂ in the next [Step-120] without forming the silicon oxide film 14, an interface state may be generated in the silicon semiconductor substrate 10,
There is a possibility that a problem that the film quality of the first insulating material layer in the groove 13 is deteriorated.

[Step-120] After that, a first insulating material layer 15 made of SiO ₂ is deposited on the mask layer 12 including the inside of the groove 13, and the groove 13 is filled with the first insulating material layer 15 (FIG. 1 (B)). Specifically, based on the high-density plasma CVD method shown in Table 2 below, a thickness of about 0.
A 3 μm first insulating material layer 15 is deposited. The first
The thickness of the insulating material layer 15 is not limited to 0.3 μm, but if the thickness is too large, the variation in the thickness becomes too large. Here, the thickness of the first insulating material layer 15 is a thickness assuming that the first insulating material layer is deposited on a flat surface. Generally, the thickness of the first insulating material layer in the groove 13 is slightly larger than 0.3 μm. When a CVD method other than the high-density plasma CVD method is employed, the problem described above may occur. The shape of the first insulating material layer 15 when the first insulating material layer 15 deposited on the mask layer 12 is cut along a vertical plane depends on the thickness of the first insulating material layer 15 and the like. In some cases, the shape may be substantially triangular.

[0028]

Gas used: SiH ₄ / O ₂ / Ar = 90/180/130 sccm Pressure: 3 × 10 ² Pa (2 torr) Temperature: 500 ° C. Power: 2 kW DP / SE ratio: 4.5 (vertical direction) )

[Step-130] Next, the first insulating material layer 15 is etched back (see FIG. 1C). In the first embodiment, the first insulating material layer 15 made of SiO ₂ is etched back by a wet etching method using hydrofluoric acid. The amount of etch back of the first insulating material layer 15 was set to about 20 nm. By the etching back of the first insulating material layer 15, the silicon oxide film 14 on the upper side of the mask layer 12 is removed at the same time, and the upper side of the mask layer 12 is exposed (FIG. 1C). (See arrow "A"). The first insulating material layer 15 may be etched back so that the silicon oxide film 14 on the side surface of the mask layer 12 is removed and the entire side surface of the mask layer 12 is exposed. However, in this case, it is important that the silicon oxide film 14 formed on the side wall of the groove 13 is not etched. When the silicon oxide film 14 formed on the side wall of the groove 13 is etched, when the second insulating material layer 16 is formed in the next step, the second insulating material layer 16 is in direct contact with the silicon semiconductor substrate 10. This may cause a problem that an interface state is generated on the silicon semiconductor substrate 10.

On the other hand, even when the first insulating material layer 15 is etched back, the upper side of the mask layer 12 is not exposed, and the first insulating material layer 15 above the shoulder of the mask layer 12 is not exposed. Is too thick, when the mask layer 12 is removed to expose the surface of the silicon semiconductor substrate 10 in [Step-170], the side surface of the groove-type element isolation region is formed from SiO ₂ to its upper end. The first insulating material layer 15 made of SiO ₂ is exposed not only in the state where the first insulating material layer 15 is exposed, but also on the top surface of the shoulder of the groove type element isolation region. As a result, the trench-type element isolation region is in a state as shown in FIG. 13A, and a misalignment occurs in a lithography process when an opening is formed in an interlayer insulating layer to form a contact hole. When the opening is formed by etching the interlayer insulating layer made of SiO ₂ , the shoulder of the groove type element isolation region may be etched.

However, by etching back the first insulating material layer 15, the silicon oxide film 14 on the upper side of the mask layer 12 is removed and the upper side of the mask layer 12 is exposed. If the silicon oxide film 14 on the side surface is completely removed and all the side surfaces of the mask layer 12 are exposed, a second insulating material layer made of SiN exists at least at the upper end of the side surface of the trench type element isolation region. Will do. As a result, when the opening is formed by etching the interlayer insulating layer made of SiO ₂ , it is possible to reliably prevent the shoulder of the groove-type element isolation region from being etched.

However, [Step-130] is not essential.
As shown in FIG. 7A, if the first insulating material layer 15 is buried in the groove 13 so that the end of the first insulating material layer 15 in the groove 13 is located on the side surface of the mask layer 12. On the first insulating material layer 15 in the groove 13 and on the mask layer 12
FIG. 7B shows the state when the second insulating material layer 16 is deposited on the substrate, and as shown in FIG. 7C, the groove-type element isolation region finally obtained. There is only a thin silicon oxide film 14 on the side of. Accordingly, when the opening is formed by etching the interlayer insulating layer made of SiO ₂ , the silicon oxide film 14 is etched, but a substantial problem hardly occurs.

[Step-140] After that, on the first insulating material layer 15 in the groove 13 and on the mask layer 12,
A second layer of insulating material 16 of iN is deposited (FIG. 2).
(A)). Here, “depositing the second insulating material layer 16 on the first insulating material layer 15 in the groove 13” means that the second insulating material layer 16 is directly formed on the first insulating material layer 15. Means to deposit. On the other hand, “depositing the second insulating material layer 16 on the mask layer 12”
When depositing the second insulating material layer 16 directly on the mask layer 12, the second insulating material layer 16 is deposited on the top surface 12 of the mask layer and the first insulating material layer 15 deposited on the top surface of the mask layer 12. In the case where the insulating material layer 16 is deposited (see FIG. 2A), all cases in which the second insulating material layer 16 is deposited on the first insulating material layer 15 deposited on the top surface of the mask layer 12 Is included.

Specifically, the CVD conditions shown in Table 3 were used.
A second insulating material layer 16 having a thickness of about 150 nm is formed on the entire surface.
What is necessary is just to film. A second insulating material on the first insulating material layer 15
Second insulating material above the groove 13 after forming the material layer 16
The lowest level of the surface of layer 16 (horizontal in FIG.
The solid line A indicates water on the surface of the silicon semiconductor substrate 10.
2 (indicated by a horizontal dashed line B in FIG. 2A)
Higher is required. The second portion above the groove 13
Of the surface of the insulating material layer 16 of the
If it is too high, the second insulating material
It takes a long time to planarize the layer 16. Therefore, the groove 1
The minimum level of the surface of the second insulating material layer 16 above 3 is appropriate.
You need to make a choice. Table of silicon semiconductor substrate 10
A second insulating material layer above the groove 13 with respect to the surface
The lowest level of the surface of H₁₆Water on the surface of the mask layer 12
H₁₂First insulating material in contact with the side surface of mask layer 12
The level at the top of layer 15 is H₁₅(Smell of (A) in FIG. 2)
(Shown by a horizontal two-dot chain line C). At this time, 0 <H
₁₆Needs to be satisfied. Preferably, 0.8H ₁₂≤
H₁₆≦ 1.2H₁₂, More preferably 0.9H₁₂≤H₁₆≤
1.1H₁₂It is desirable to satisfy the following relationship. Also, 0
≤H₁₅Needs to be satisfied. Furthermore, 0 <H₁₅≤
H₁₂, Preferably 0 <H₁₅≦ 0.8H₁₂Satisfy the relationship
Is desirable. In addition, H₁₅<H₁₆Satisfy the relationship
Preferably. Moreover, the bottom of the groove 13 was used as a reference.
At this time, the minimum of the surface of the first insulating material layer 15 in the groove 13 is
H 'level ₁₅, When the depth of the groove 13 is D, H ′₁₅
<D, H '₁₅= D, H '₁₅> D
There may be.

[0035]

Table 3 Gas used: SiH ₂ Cl ₂ / NH ₃ / N ₂ = 90/600/500 sccm Pressure: 53 Pa (0.4 torr) Film forming temperature: 760 ° C.

[Step-150] Thereafter, although not an essential step, the top surface of the mask layer 12 having a predetermined width is partially exposed. That is, the second insulating material layer 16 and the first insulating material layer 15 on the wide mask layer 12 are removed.
Specifically, a resist layer (not shown) patterned based on a lithography technique
Then, the second insulating material layer 16 and the first insulating material layer 15 are etched using the resist layer as an etching mask. As an example, the minimum exposure width L ₀ for forming a resist layer by lithography 0.5
[mu] m, in the case where the head region width L ₁ in consideration of margin for misalignment and the lateral 0.25μm has a width L ₀ + 2L
₁ = a resist layer having an opening is formed on the mask layer 12 of 1.0 μm or more, and the second insulating material layer 16
After the portion of the first insulating material layer 15 is removed by etching, the resist layer is removed (see FIG. 2B).
In FIG. 2B, an area of the mask layer 12 where the second insulating material layer 16 and the first insulating material layer 15 are removed by etching is indicated by an arrow “C”. As described above, when the second insulating material layer 16 and the first insulating material layer 15 on the wide mask layer 12 are not removed, the second insulating material layer 16 is uniformly planarized in the next step. This may be difficult.

[Step-160] Next, a flattening process is performed on at least the second insulating material layer 16 based on a chemical mechanical polishing method (CMP method), so that the top surface of the mask layer 12 and the second insulating material are removed. The level of the top surface of the material layer 16 is matched (see FIG. 3A). The shoulder of the second insulating material layer 16 (FIG. 3)
FIG. 3B is an enlarged schematic partial cross-sectional view of an area surrounded by a circle “B” in FIG. Here, the second insulating material layer 16 is subjected to a planarization process based on the CMP method, and at the same time, the mask layer 12 is partially polished in the thickness direction by the CMP method, so that the silicon oxide film 14 and a portion of the mask layer 12 are partially polished. May be removed, and the level of the top surface of the mask layer 12 and the level of the top surface of the second insulating material layer 16 may be matched. In this case, it is preferable to perform a planarization process so that the first insulating material layer 15 is not exposed as much as possible. Here, when the first insulating material layer 15 remains on the mask layer 12, the first insulating material layer 15 is subjected to a flattening process by a CMP method, and from the top surface of the mask layer 12. Removed.

FIG. 14 is a conceptual diagram of a polishing apparatus suitable for performing the CMP method. This polishing apparatus includes a polishing plate, a substrate holder, and an abrasive slurry supply system. The polishing plate is supported on a rotating polishing plate rotation shaft, and a polishing pad is provided on the surface thereof. The substrate holder is disposed above the polishing plate, and is supported on a substrate holder rotating shaft. The substrate to be polished is placed on a substrate holder.
The substrate holder rotating shaft is attached to a polishing pressure adjusting mechanism (not shown) that pushes the substrate holder in the direction of the polishing pad. The abrasive slurry containing the abrasive is supplied to the polishing pad from the abrasive slurry supply system. The CMP method uses such a polishing apparatus. Then, the polishing plate is rotated while supplying the slurry containing the abrasive to the polishing pad. At the same time, the polishing pressure of the substrate with respect to the polishing pad is adjusted by the polishing pressure adjusting mechanism while rotating the substrate placed on the substrate holding table. Thus, the surface of the substrate can be polished.

[Step-170] Thereafter, the mask layer 12 made of polysilicon is removed by dry etching to expose the surface of the silicon semiconductor substrate 10 (FIG. 4).
(A)). FIG. 4B is a schematic partial cross-sectional view in which the shoulder portion of the second insulating material layer 16 (the area surrounded by a circle “B” in FIG. 4A) is enlarged. Thus, the groove 13 formed in the silicon semiconductor substrate 10 and the groove 13
A first insulating material layer 15 made of SiO ₂ and a second insulating material layer made of SiN formed on the first insulating material layer 15.
Of the insulating material layer 16 of the groove type element isolation region 17 can be formed.

[Step-180] Next, the pad oxide film 11
Is removed, the surface of the silicon semiconductor substrate 10 is thermally oxidized to form the gate insulating film 20, then the gate region 23 is formed by a known method, and the low concentration impurity region 24 is formed by ion implantation. Form. The gate region 23 includes, for example, a polysilicon layer 21 containing an impurity and an offset film 22 made of SiN formed thereon. Thereafter, a SiN layer is deposited on the entire surface by the CVD method, and the SiN layer is etched back, so that S
A gate sidewall 25 made of iN is formed (see FIG. 5A). Next, after a high-concentration impurity region is formed on the surface of the silicon semiconductor substrate 10 by an ion implantation method, activation treatment of the ion-implanted impurity is performed to form a source / drain region 26 (FIG. 5B). reference). Thus, a MOS-FET type transistor element can be obtained.

[Step-190] Thereafter, an interlayer insulating layer 27 made of SiO ₂ is formed on the entire surface, and the opening 28 reaching the transistor element (specifically, the source / drain region 26) is formed by etching (RIE). The opening 28 is formed in the interlayer insulating layer 27 (see FIG. 6A).
A conductive material is formed on the interlayer insulating layer 27 including the inside by a sputtering method, and the opening 28 is filled with the conductive material to form a contact hole 29A reaching the transistor element (specifically, the source / drain region 26). To the interlayer insulating layer 2
7 is formed. Next, a wiring 29 is formed by patterning a conductive material on the interlayer insulating layer 27 (see FIG. 6B). As described above, a semiconductor device including a MOS-FET transistor element can be obtained. Although depending on the etching conditions, when the etching rate of the second insulating material layer 16 made of SiN is 1, the etching rate of the interlayer insulating layer 27 made of SiO ₂ is 5 or more.

Even if misalignment occurs in the lithography step when forming the opening 28 in the interlayer insulating layer 27, when the opening 28 is formed by etching the interlayer insulating layer 27 made of SiO ₂ , Separation area 17
Since the second insulating material layer 16 made of SiN is formed on the top surface of the trench, the shoulder of the groove-type element isolation region 17 is not etched. Therefore, as shown in FIG. 6B, when the contact hole 29A is formed, the contact hole 29A is
And the problem that junction leakage occurs can be reliably avoided. In the method described in the first embodiment, since the deposited film thickness of the first insulating material layer 15 can be made relatively thin, the film thickness variation of the first insulating material layer 15 after film formation can be reduced. And the film thickness of the first insulating material layer 15 is excellent. In addition, since the amount of etch back of the first insulating material layer 15 may be small,
The thickness variation of the first insulating material layer 15 after the etch back is small.

Embodiment 2 Embodiment 2 relates to a method for forming a trench-type element isolation region and a method for manufacturing a semiconductor device according to a second aspect of the present invention. That is, the first insulating material layer is etched back based on the dry etching method. As in the first embodiment, the mask layer is made of polysilicon, the first insulating material layer is made of silicon oxide (SiO ₂ ), the second insulating material layer is made of silicon nitride (SiN), The interlayer insulating layer is made of silicon oxide (SiO ₂ ). A planarization process is performed on the second insulating material layer, and the planarization process is performed by a chemical mechanical polishing method (CMP).
Law). Hereinafter, a method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region according to the second embodiment will be described with reference to FIGS. 8 to 11 which are schematic partial cross-sectional views of a silicon semiconductor substrate and the like.

[Step-200] First, as in [Step-100] of the first embodiment, the silicon semiconductor substrate 1
After a pad oxide film 11 is formed on the surface of a semiconductor substrate made of zero, a mask layer 12 made of polysilicon having a thickness of about 150 nm is formed on the entire surface by a CVD method.

[Step-210] Next, an opening is formed in the mask layer 12 and the pad oxide film 11 in the same manner as in [Step-110] of the first embodiment, and subsequently, the opening is exposed at the bottom of the opening. The silicon semiconductor substrate 10 has a depth of about 0.3 μ
The groove 13 of m is formed. Thereafter, the resist layer is removed, and a silicon oxide film 14 having a thickness of about 10 nm is formed on the surface of the silicon semiconductor substrate 10 exposed in the trench 13 and on the top and side surfaces of the mask layer 12 made of polysilicon. This state is shown in FIG.

[Step-220] Thereafter, a first insulating material layer 15 made of SiO ₂ is deposited on the mask layer 12 including the inside of the groove 13, and the groove 13 is buried with the first insulating material layer 15 (FIG. 8 (B)). Specifically, based on a high-density plasma CVD method under the same conditions as shown in Table 2,
A first insulating material layer 15 having a thickness of about 0.7 μm is deposited. Here, the thickness of the first insulating material layer 15 is a thickness assuming that the first insulating material layer 15 is deposited on a flat surface. The conditions for forming the first insulating material layer may be the same as those in Table 2.

[Step-230] Next, the first insulating material layer 15 is etched back (see FIG. 9A). In the second embodiment, the first insulating material layer 15 made of SiO ₂ is etched back by a dry etching method (RIE method) using a C ₄ F ₈ / CO-based etching gas.
The etch back amount of the first insulating material layer 15 is set to about 0.4 μm
And By the etching back of the first insulating material layer 15, the silicon oxide film 14 on the side surface of the mask layer 12 is removed at the same time, and the side surface of the mask layer 12 is exposed. However, in this case, it is important that the silicon oxide film 14 formed on the side wall of the groove 13 is not etched. Silicon oxide film 1 formed on the side wall of groove 13
4 is etched, when the second insulating material layer 16 is formed in the next step, the second insulating material layer 16 comes into direct contact with the silicon semiconductor substrate 10, and the interface state May be generated. The first insulating material layer 15 may be etched back so that the silicon oxide film 14 on the upper side of the mask layer 12 is removed and the upper side of the mask layer 12 is exposed. When the deposited film thickness of the second insulating material layer 16 is 0.7 μm and the etch-back amount is 0.4 μm, the first insulating material layer 15 on the mask layer 12 having a width of less than 1.0 μm is almost removed. .

It should be noted that if the deposited film thickness of the first insulating material layer 15 is small, the following inconvenience may occur. Incidentally, the minimum exposure width L ₀ for forming a resist layer by lithography 0.
5 [mu] m, in the case where the head region width L ₁ in consideration of margin for misalignment and the lateral 0.25μm will be described later in [Step-250], second on the mask layer 12 having a width of more than 1.0μm of The insulating material layer 16 and the first insulating material layer 15 can be partially removed by etching. By the way, in the case where the first insulating material layer 15 is deposited by the high-density plasma CVD method, and when the deposited film thickness of the first insulating material layer 15 is small, a schematic diagram of FIG. 1.0 μm
The first insulating material layer 15A having a triangular cross section tends to be deposited on the mask layer 12 having a width smaller than the width. In such a case, since the deposited film thickness of the first insulating material layer 15 is small in the first place, the etch back amount of the first insulating material layer 15 as a whole is also small. Therefore, the first insulating material layer 15A
Is etched back, as shown in FIG.
The first insulating material layer 15B having a triangular cross-sectional shape is left on the mask layer 12. The first remaining
The second insulating material layer 16 is also deposited on the insulating material layer 15B in the next [Step-240]. By the way, in [Step-250] described below, the second insulating material layer and the first insulating material layer on the mask layer 12 having a width of 1.0 μm or more can be removed by etching.
The second insulating material layer and the first insulating material layer on the mask layer 12 having a width of less than 1.0 μm are not removed. Therefore, even if a planarization process is performed based on the CMP method in [Step-260] described later, the second insulating material layer 1 on the mask layer 12
6 and the first insulating material layer 15B are difficult to remove, and finally, the second insulating material layer 16 and the first insulating material layer 15B on the mask layer 12 having a width of less than 1.0 μm remain. There is a risk of being done. Therefore, the second insulating material layer 16
Is preferably determined in consideration of not only the depth of the groove 13 but also the minimum width of the mask layer.

On the other hand, as shown in FIG.
If the thickness of the deposited insulating material layer 15 is sufficiently large (for example, about 0.7 μm), the first insulating material layer 15 can be formed in [Step-
240], the width is 1.0 μm
Even the first insulating material layer deposited on the mask layer 12 of less than m can be removed.

If the top surface of the mask layer 12 is not exposed by the etch back of the first insulating material layer 15, the CMP will be performed in [Step-260] described later.
Even if a planarization process is performed based on the method, the level of the top surface of the mask layer and the level of the top surface of the second insulating material layer cannot be matched, and when the top surface of the mask layer 12 is exposed, Is already removed, and the first insulating material layer 15 is exposed. Accordingly, when the surface of the silicon semiconductor substrate 10 is exposed by removing the mask layer 12, the second insulating material layer does not remain above the groove 13, as shown in FIG. As a result, when misalignment occurs in a lithography process when forming an opening in the interlayer insulating layer, when the opening is formed by etching the interlayer insulating layer made of SiO ₂ , the shoulder of the groove-type element isolation region is formed. Is etched.

However, the etch-back of the first insulating material layer 15 exposes the top surface of the mask layer 12, and furthermore,
The state where the silicon oxide film 14 on the upper side of the mask layer 12 is removed and the upper part of the side surface of the mask layer 12 is exposed, or the case where the silicon oxide film 14 on the side of the mask layer 12 is entirely removed and the side of the mask layer 12 is removed If all are exposed, the second insulating material layer made of SiN exists at least at the upper end of the side surface of the groove-type element isolation region. As a result, when the opening is formed by etching the interlayer insulating layer made of SiO ₂ , it is possible to reliably prevent the shoulder of the groove-type element isolation region from being etched.

[Step-240] Then, the second step in the groove 13 is performed.
1 on the insulating material layer 15 and the mask layer 12.
A second layer of insulating material 16 of iN is deposited (FIG. 9).
(B)). Specifically, the same as illustrated in Table 3
Second insulating material layer 1 having a thickness of about 150 nm under CVD conditions
6 is formed on the entire surface. On the first insulating material layer 15, a second
The second insulating layer above the groove 13 after forming the insulating material layer 16
The lowest level of the surface of the edge material layer 16 is a silicon semiconductor substrate.
10 higher than the surface level. Silicon semiconductor substrate 10
The second insulating material above the groove 13 with respect to the surface of
The minimum level of the surface of the material layer 16 is H₁₆Surface of the mask layer 12
The level of H₁₂First insulation contacting the side surface of the mask layer 12
The level of the top surface of the material layer 15 is H₁₅And This and
0 <H₁₆Needs to be satisfied. Preferably,
0.8H₁₂≤H₁₆≦ 1.2H₁₂, More preferably 0.9
H₁₂≤H₁₆≤1.1H₁₂Want to satisfy the relationship
No. Also, 0 ≦ H₁₅Needs to be satisfied. Furthermore, 0
<H₁₅≤H₁₂, Preferably 0 <H₁₅≦ 0.8H₁₂connection of
It is desirable to satisfy In addition, H₁₅<H₁₆connection of
Is preferably satisfied. Also, based on the bottom of the groove 13,
The table of the first insulating material layer 15 in the groove 13
The minimum level of the surface is H '₁₅When the depth of the groove 13 is D
D ≦ H ′ ₁₅Is preferably satisfied.

[Step-250] Then, as in [Step-150] of the first embodiment, although not an essential step, the top surface of the mask layer 12 having a predetermined width is partially exposed. That is, the second insulating material layer 16 and the first insulating material layer 15 on the wide mask layer 12 are removed (FIG. 1).
0 (A)). Note that, in FIG.
The region of the mask layer 12 where the insulating material layer 16 and the first insulating material layer 15 are removed by etching is indicated by an arrow “C”.

[Step-260] Next, a chemical / mechanical polishing method (CMP method) is applied to at least the second insulating material layer 16.
Is applied to the top surface of the mask layer 12 and the second surface.
The level of the top surface of the insulating material layer 16 of FIG.
(B)). Here, CM is applied to the second insulating material layer 16.
A flattening process is performed based on the P method, and the mask layer 12
Is partially polished in the thickness direction by a CMP method to remove the silicon oxide film 14 and a part of the mask layer 12 so that the top surface of the mask layer 12 and the level of the top surface of the second insulating material layer 16 are matched. You may. In this case, it is important to perform a planarization process so that the first insulating material layer 15 is not exposed. Here, when the first insulating material layer 15 remains on the mask layer 12, the first insulating material layer 15 is subjected to a flattening process by a CMP method, and from the top surface of the mask layer 12. Removed.

[Step-270] Then, the mask layer 12 made of polysilicon is removed by dry etching to expose the surface of the silicon semiconductor substrate 10 (see FIG. 11A). Thus, the silicon semiconductor substrate 1
0 and a SiO ₂ filling the groove 13
A first insulating material layer 15 made of
5, a second insulating material layer 16 made of SiN
Can be formed.

[Step-280] Next, by performing the same steps as [Step-180] and [Step-190] of the first embodiment, the MOS-MOS shown in FIG.
A semiconductor device including a FET-type transistor element can be obtained.

Even if misalignment occurs in the lithography step when forming the opening 28 in the interlayer insulating layer 27, when the opening 28 is formed by etching the interlayer insulating layer 27 made of SiO ₂ , Separation area 17
Since the second insulating material layer 16 made of SiN is formed on the top surface of the trench, the shoulder of the groove-type element isolation region 17 is not etched. Therefore, FIG.
As shown in FIG. 2, when the contact hole 29A is formed, the contact hole 29A is
And the problem that junction leakage occurs can be reliably avoided. In the method described in the second embodiment, the top surface of the first insulating material layer 15 in the groove 13 after the etch back becomes relatively flat.
A second control of the minimum level H ₁₆ of the surface of the insulating material layer 16 of the groove 13 upwardly, excellent controllability of levels H ₁₅ portion of the top surface of the first layer of insulating material 15 which is in contact with the side surface of the mask layer 12 .

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. Various conditions and numerical values in the embodiment of the invention, and the structures of the semiconductor device and the transistor element are merely examples, and the design can be changed as appropriate.

[0059]

According to the present invention, misalignment occurs in a lithography process for forming an opening in an interlayer insulating layer based on an etching method, and the opening is formed so as to hang over the groove-type element isolation region. Even if it is, the trench type element isolation region is not etched. Therefore, when the contact hole is formed, it is possible to reliably avoid the problem that the contact hole extends to the inside of the silicon semiconductor substrate and cause a junction leak, and to manufacture a highly reliable semiconductor device. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a method of manufacturing a semiconductor device including a method of forming a groove-type element isolation region according to a first embodiment of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region according to the first embodiment of the invention, following FIG. 1; .

FIG. 3 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for illustrating a method for manufacturing a semiconductor device including a method for forming a trench-type element isolation region according to the first embodiment of the invention, following FIG. 2; .

FIG. 4 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining a method of manufacturing a semiconductor device including a method of forming a groove-type element isolation region according to the first embodiment of the present invention, following FIG. .

FIG. 5 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region according to the first embodiment of the present invention, following FIG. .

FIG. 6 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for explaining a method of manufacturing a semiconductor device including the method of forming the groove-type element isolation region according to the first embodiment of the present invention, following FIG. .

FIG. 7 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like showing a modified example of a film formation state of a first insulating material layer.

FIG. 8 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a method of manufacturing a semiconductor device including a method of forming a groove-type element isolation region according to a second embodiment of the present invention.

FIG. 9 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of manufacturing a semiconductor device including a method of forming a trench-type element isolation region according to a second embodiment of the present invention, following FIG. .

FIG. 10 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for illustrating a method of manufacturing a semiconductor device including a method of forming a groove-type element isolation region according to a second embodiment of the present invention, following FIG. .

11 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of manufacturing a semiconductor device including a method of forming a groove-type element isolation region according to a second embodiment of the present invention, following FIG. 10; .

FIG. 12 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a problem that may occur when the deposited film thickness of the first insulating material layer is small.

FIG. 13 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for describing a problem that may occur depending on a film formation state of a first insulating material layer.

FIG. 14 is a conceptual diagram of a polishing apparatus suitable for performing a chemical / mechanical polishing method.

FIG. 15 is a schematic partial cross-sectional view of a silicon semiconductor substrate and the like for describing a method of manufacturing a semiconductor device including a conventional method of forming a trench-type element isolation region.

FIG. 16 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for illustrating a method of manufacturing a semiconductor device including a conventional method of forming a trench-type element isolation region, following FIG.

FIG. 17 is a schematic partial cross-sectional view of a silicon semiconductor substrate or the like for explaining a method of manufacturing a semiconductor device including a conventional method of forming a trench-type element isolation region, following FIG. 16;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Silicon semiconductor substrate, 11 ... Pad oxide film, 12 ... Mask layer, 13 ... Groove, 14 ...
Silicon oxide film, 15... First insulating material layer, 16.
..First insulating material layer, 17 ... groove type element isolation region,
20: gate insulating film, 21: polysilicon layer,
22: offset film, 23: gate region, 24
... low concentration impurity region, 25 ... gate side wall, 26 ... source / drain region, 27 ... interlayer insulating layer, 28 ... opening, 29 ... wiring, 29A
... Contact holes

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F032 AA34 AA44 AA45 AA46 AA70 CA17 DA03 DA04 DA23 DA24 DA28 DA33 DA34 DA43 DA53 DA78 5F040 DA00 DB01 DC01 EC07 EF02 FA07 FB02 FB04 FC10 5F058 BD01 BD04 BD10 BE03 BF07 BF23 BJ01 BJ06

Claims (7)

[Claims] (A) forming a mask layer on the surface of a semiconductor substrate; and (b) forming an opening in the mask layer and subsequently forming a groove in the semiconductor substrate exposed at the bottom of the opening. (C) depositing a first insulating material layer on the mask layer including the inside of the groove, and embedding the groove with the first insulating material layer; and (d) on the first insulating material layer in the groove. And depositing a second insulating material layer on the mask layer; and (e) subjecting at least the second insulating material layer to a flattening process, so that the top surface of the mask layer and the top of the second insulating material layer (F) removing the mask layer and exposing the surface of the semiconductor substrate, whereby the groove formed in the semiconductor substrate and the first filling the groove are formed. And a second insulating material layer formed on the first insulating material layer. Groove type element formation method of the isolation region and forming a type isolation region. 2. The method according to claim 1, wherein the method of depositing the first insulating material layer in the step (c) is based on a high-density plasma CVD method. 3. The trench type element isolation region according to claim 1, further comprising a step of etching back the first insulating material layer between the step (c) and the step (d). Forming method. 4. The method according to claim 1, further comprising the step of partially exposing the top surface of the mask layer having a predetermined width between the step (d) and the step (e). A method for forming a groove type element isolation region. 5. The method according to claim 1, wherein the planarization in the step (e) is based on a chemical / mechanical polishing method. 6. The trench-type device according to claim 1, wherein the mask layer is made of polysilicon, the first insulating material layer is made of silicon oxide, and the second insulating material layer is made of silicon nitride. A method for forming an isolation region. 7. A step of forming a mask layer on the surface of the semiconductor substrate, and a step of forming an opening in the mask layer and subsequently forming a groove in the semiconductor substrate exposed at the bottom of the opening. (C) depositing a first insulating material layer on the mask layer including the inside of the groove, and embedding the groove with the first insulating material layer; and (d) on the first insulating material layer in the groove. And depositing a second insulating material layer on the mask layer; and (e) subjecting at least the second insulating material layer to a flattening process, so that the top surface of the mask layer and the top of the second insulating material layer (F) removing the mask layer to expose the surface of the semiconductor substrate, and thereby forming a groove formed in the semiconductor substrate and a first insulating material layer filling the groove. And a groove-type element isolation region comprising a second insulating material layer formed on the first insulating material layer Forming a transistor element on a semiconductor substrate surrounded by a groove-type element isolation region; and (h) forming a transistor element having a higher etching rate than a material forming the second insulating material layer. After the formed interlayer insulating layer is formed on the entire surface, an opening reaching the transistor element is formed in the interlayer insulating layer based on an etching method, and then the opening is filled with a conductive material to form a contact hole reaching the transistor element. Forming a semiconductor device on an interlayer insulating layer.