KR20050067474A - Method for isolation in semiconductor device - Google Patents

Abstract

The present invention can uniformly form TCRs between lots, wafers, or locations within a wafer, and is suitable for device isolation of semiconductor devices suitable for preventing the depth of the moat during the pre-cleaning process for removing the pad oxide film. In order to provide a device separation method of the present invention, the step of forming a pad oxide film (LP-TEOS) having a fast wet etch rate on a silicon substrate, forming a pad nitride film on the pad oxide film, the pad nitride film and the Etching the pad oxide layer using a device isolation mask, etching the silicon substrate using a stacked pattern in the order of the pad oxide film, the pad nitride film, and the device isolation mask to form a trench, and forming the device isolation mask. Stripping, and by performing a wet cleaning to etch the side surface of the pad oxide film faster The step of exposing the top corner, and a step of rounding the top corner of the trench sidewall oxidation proceeds to the surface of the trench including the exposed top corner.

Description

Device Separation Method for Semiconductor Devices {METHOD FOR ISOLATION IN SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a device separation method for a semiconductor device.

The device-to-device isolation of semiconductor devices can be broadly divided into LOCal Oxidation of Silicon (hereinafter referred to as LOCOS) and trench isolation.

Among them, the LOCOS method has the advantage that the process is simple and separates large and narrow portions at the same time, but the bird's beak is formed by lateral oxidation, so that the width of the device isolation region is widened. The effective area of the drain region is reduced. In addition, when the field oxide film is formed, stress is concentrated on the edges of the oxide film due to the difference in thermal expansion coefficient, so that a crystal defect occurs in the silicon substrate and thus a leakage current is increased.

Therefore, by forming a trench in a silicon substrate and filling the inside with an insulating material such as an oxide, a trench element isolation (Trench) can realize a separation region smaller than the LOCOS by increasing the effective separation length even at the same isolation width. Isolation technology is required.

Among the various processes of device isolation technology using trenches, how to form a trench profile is very important for realizing a device having stable characteristics. That is, the depth of the trench, the trench angle, the shape of the trench edge, and the like should be appropriately used. In particular, when using the shallow trench isolation (STI) method in a highly integrated semiconductor device, the electrical characteristics of the device are determined by the profile of the edge portion of the trench. It is not an exaggeration to say.

1 is a cross-sectional view illustrating a problem in a conventional STI device isolation method, in which reference numeral 11 denotes a semiconductor substrate, 12 denotes a device isolation layer embedded in an STI region, 13 denotes a gate oxide layer, and 14 denotes a gate electrode. Represent each.

As shown in FIG. 1, the following problem occurs when the edge portion of the trench is formed at a sharp angle close to about 90 °.

First, in the gate electrode forming process, the gate electrode wraps around the top corner of the trench, whereby a strong electric field is concentrated in the trench corner so that the transistor is turned on twice. The performance of the transistor is degraded by inducing a hump phenomenon and an inverse narrow width effect. The reverse narrow effect refers to a phenomenon in which the threshold voltage decreases as the channel width of the transistor decreases.

The second problem that occurs when the edge portion of the trench is formed at a sharp angle close to 90 ° is that the gate oxide layer 13 is thinly formed at the trench edge portion (see 'x'), or the electric field is formed on the gate oxide layer in this region. Is concentrated and the reliability of the gate oxide film is lowered.

Due to the above two problems, the refresh characteristics of the cell transistors of the DRAM are deteriorated.

In order to solve the above problems, a technique for rounding the top corner of the trench (hereinafter, abbreviated as 'TCR') has been proposed.

2A to 2H are cross-sectional views illustrating an STI device isolation method using a TCR technique according to the prior art.

As shown in FIG. 2A, after the pad oxide layer 22 and the pad nitride layer 23 are sequentially formed on the silicon substrate 21, a device isolation mask is formed using a photoresist on the pad nitride layer 23. , 24). In this case, the pad oxide film 22 is a thermal oxide film.

Next, after etching the pad nitride layer 23 and the pad oxide layer 22 sequentially using the device isolation mask 24 as an etching mask, the exposed surface of the silicon substrate 21 after etching the pad oxide layer 22 is etched, Etching is performed under the primary etching conditions for generating the polymer 25. In this case, the polymer 25 is attached to sidewalls of the pad oxide layer 22, the pad nitride layer 23, and the device isolation mask 24.

The top corner of the trench is rounded by etching the surface of the silicon substrate 21 under the condition of generating the polymer 25 as described above.

As shown in FIG. 2B, the trench 26 is formed by etching the second etching condition in which the silicon substrate 21 is etched to a predetermined depth.

As shown in FIG. 2C, a strip process for removing the device isolation mask 24 is performed, and a cleaning process for removing residual etching byproducts and the polymer 25 is performed.

After the above cleaning process, the top corner 26a of the trench 26 from which the polymer 25 has been removed is exposed.

As shown in FIG. 2D, the post-etch process is performed to remove the etch loss layer generated during the etching of the trench 26, which is referred to as a light etching treatment (LET) process. Through this additional LET process, the etch loss layer generated during the etching of the trench 26 may be removed and the bottom corner 26b of the trench 26 may be rounded. In particular, the polymer 25 is removed to form a top corner 26a of the exposed trench 26.

As shown in FIG. 2E, a sidewall oxidation process is performed to form a sidewall oxide layer 27 on the surface of the trench 26. The top corner 26a of the trench 26 is rounded by forming the sidewall oxide layer 27.

As shown in FIG. 2F, after the liner nitride layer 28 is formed on the silicon substrate 21 on which the sidewall oxide layer 27 is formed, the trench 26 is sufficiently buried on the silicon substrate 21. A high density plasma oxide film 28 is formed.

As shown in FIG. 2G, the high-density plasma oxide film 28 is subjected to chemical mechanical polishing (CMP) until the surface of the pad nitride film 23 is exposed.

In the subsequent process, after further etching to remove the step between the high density plasma oxide film 28 and the silicon substrate 21, the wet etching using a phosphate solution (H ₃ PO ₄ ) to remove the pad nitride film 23 Proceed with the process. At this time, since the pad oxide film 22 is a thermal oxide film having a slow wet etch rate when the pad nitride film 23 is removed, the pad oxide film 22 remains thick after the pad nitride film 23 is removed.

As shown in FIG. 2H, a pre-cleaning process for removing the pad oxide layer 22 is performed prior to depositing the screen oxide layer. At this time, since the pad oxide film 22 is thermal oxidation having a slow wet etching rate, and the pad oxide film 22 remains thick after the pad nitride film 23 is removed, the wet etching time during the pre-cleaning process is required for a long time.

In this manner, if the time of the pre-cleaning process for removing the pad oxide film 22 is required for a long time, the depth of the moat (Mat) M in which the device isolation film is lowered in comparison with the surface of the silicon substrate is deepened near the trench top corner. .

Prior to the etching of the trench 26, the conventional etching process is performed by applying a primary etching condition for generating the polymer 25 to round the top corner 'z' of the trench.

However, in the TCR technology using a polymer, it is difficult to uniformly attach the polymer to the sidewalls of the pad oxide film 22, the pad nitride film 23, and the device isolation mask 24, and foreign matters stick to the etching chamber as the polymer is generated. In addition, it is difficult to ensure the reproducibility of the polymer according to the characteristics of the etching apparatus, there is a problem that the TCR is not formed uniformly between the lot (Lot), each wafer or position in the wafer.

In addition, the prior art has a problem that the depth of the moat deepens because the time of the pre-cleaning process to proceed before the deposition of the screen oxide film requires a long time.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a device separation method of a semiconductor device capable of uniformly forming a TCR for each lot, for each wafer, or for each position in the wafer. .

In addition, another object of the present invention is to provide a device isolation method of a semiconductor device suitable for preventing the depth of the moat deep in the pre-cleaning step for removing the pad oxide film.

The device isolation method of the present invention for achieving the above object is to form a pad oxide film having a fast wet etch rate on a silicon substrate, forming a pad nitride film on the pad oxide film, device separation between the pad nitride film and the pad oxide film Etching using the mask, etching the silicon substrate using a pattern stacked in the order of the pad oxide film, the pad nitride film, and the device isolation mask to form a trench; stripping the device isolation mask; Exposing the top corners of the trenches by performing a wet cleaning to quickly etch the side surfaces of the pad oxide films, and oxidizing the sidewalls of the trenches including the exposed top corners to perform sidewall oxidation. It characterized in that it comprises a rounding process, the pad oxide film is LP-TEOS Characterized in that, the LP-TEOS is characterized in that formed to 50 ~ 200Å thickness.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3H are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 3A, the pad oxide film 32 and the pad nitride film 33 are sequentially formed on the silicon substrate 31. Here, the pad oxide film 32 is used to relieve stress that the silicon substrate 31 receives when the pad nitride film 33 is deposited, and has a low pressure furnace tetra ethyl ortho having a thickness of 50 kPa to 200 kPa. Silicate. Here, LP-TEOS has better wet etching characteristics than thermal oxide, and LP-TEOS has excellent role of alleviating stress during deposition of the pad nitride layer 33 even though the thickness is thinner than that of thermal oxide. Therefore, the present invention uses LP-TEOS as the pad oxide film 32, the thickness is optimized to a thickness of 50 ~ 200 ~. On the other hand, the thermal oxide film is 100 Å thickness is required to relieve stress, in the present invention, since the wet etching rate is four times faster than the thermal oxide film LP-TEOS may be variable in thickness.

In addition, the pad nitride layer 33 serves as a subsequent etch stop layer and also serves as a polishing stop layer in a subsequent chemical mechanical polishing (CMP) process. Preferably, the pad nitride film 33 is formed of a silicon nitride film (Si ₃ N ₄ ) having a thickness of about 300 GPa to 2000 GPa.

Next, a photoresist is applied on the pad nitride film 33 and patterned by exposure and development to form an isolation mask 34.

Next, using the device isolation mask 34 as an etch mask, the pad nitride film 33 and the pad oxide film 32 are sequentially etched to expose the surface of the silicon substrate 31 on which the trench is to be formed. At this time, when the pad nitride layer 33 and the pad oxide layer 32 are etched, the etching gas is etched using, for example, a mixed gas of CHF ₃ / CF ₄ / Ar / O ₂ . Point) to set the end point of etching. Preferably, CHF _3, CF _4, or to use a mixture of O ₂ and flow rate of 0sccm~10sccm, in the absolute amount of the mixed gas flow rate of 5sccm~15sccm 5sccm~30sccm flow is often CHF _3.

As illustrated in FIG. 3B, the trench 35 is formed by etching the silicon substrate 31 using the stacked pattern of the pad oxide layer 32, the pad nitride layer 33, and the device isolation mask 24 as an etch mask. Proceed with the etching process. The etching process of the silicon substrate 31 forming the trench 35 uses hydrogen bromide (HBr).

Since the top corner of the trench 35 is rounded in a subsequent process, the trench 35 may be formed almost vertically without performing the step of rounding the top corner of the trench 35.

As shown in FIG. 3C, a strip process for removing the device isolation mask 34 and a cleaning process for removing residual etching byproducts are performed.

The cleaning process uses an HF solution, which is an oxide film etching solution. Since the pad oxide film 32 is LP-TEOS having a faster wet etching rate than the thermal oxide film, the side surface of the pad oxide film 32 near the top corner of the trench 35. This faster etching results in an undercut 36 under the pad nitride layer 33.

As a result, the top corner 35a of the trench 35 is exposed to the undercut 35 under the pad nitride layer 33 as the side surface of the pad oxide layer 32 is rapidly etched through the cleaning process.

As shown in FIG. 3D, the post-etch process is performed to remove the etch loss layer generated during the etching of the trench 35, which is called a LET (Light Etch Treatment) process. At this time, the LET process is performed by isotropic etching (isotropic etching), for example, isotropic etching is performed using a mixed gas of CF ₄ / O ₂ .

Through the additional LET process, the etch loss layer generated during the etching of the trench 35 may be removed and the bottom corner 35b of the trench 35 may be rounded. For example, the isotropic etching has a characteristic of etching the bottom corner 35b of the trench 35 more than the sidewall of the trench 35 close to the vertical, so that the angled bottom corner 35b of the trench 35 is formed. It can be formed round.

In the above LET process, since the top corner 35a of the trench 35 is exposed in FIG. 3C, the top corner 35a of the trench 35 may be partially rounded.

As shown in FIG. 3E, a sidewall oxidation process is performed to form a sidewall oxide film 37 on the surface of the trench. The top corner 35a of the trench 35 is rounded by forming the sidewall oxide film 37.

The sidewall oxidation process for forming the sidewall oxide film 37 can be either dry oxidation or wet oxidation.

As described above, in the case of forming the sidewall oxide film 37 using dry oxidation, the sidewall oxide film 37 is formed thicker than the sidewall at the top corner 35a portion of the trench 35. This is because the dry oxidation, dry oxidation has a characteristic of oxidizing the top corner 35a of the trench 35 more than the side wall of the trench 35 compared to the wet oxidation.

In addition, since the top corner 35a of the trench is exposed in advance through the cleaning process after the trench 35 is formed, the top corner 35a of the trench becomes more oxidized during the sidewall oxidation process, so that the top corner of the sidewall oxide film 37 is increased. The thickness d1 is very thick compared to the thickness d3 of the bottom and the thickness d2 of the side wall. Here, since the sidewall oxidation process proceeds based on the bottom of the trench 35, the thickness d2 of the sidewall is thicker than the thickness d1 of the bottom, which is caused by the difference in the surface orientation of the trench 35. This is because the degree of oxidation on the sidewalls varies. In particular, the amount of oxidation of the sidewalls of the trench is relatively large.

Therefore, the present invention rounds the top corner 35a of the trench 35 by oxidizing it to the top corner 35a of the trench 35 during the sidewall oxidation process, thereby stably securing the profile of the top corner 35a. Can be. In addition, the process is simple because the top corner of the trench is rounded by a cleaning and sidewall oxidation process without producing a polymer.

In addition, if the side etching amount of the pad oxide film 32 is adjusted in the cleaning process performed before the sidewall oxidation, the rounding size of the top corner 35a of the trench 35 may be variably managed during sidewall oxidation.

As shown in FIG. 3F, a liner nitride layer 38 is formed on the silicon substrate 31 on which the sidewall oxide layer 37 is formed using chemical vapor deposition (CVD). As such, by forming the liner nitride layer 38, the threshold voltage and the refresh characteristics of the cell may be improved.

Here, the liner nitride film 38 serves to buffer stress caused by the difference in coefficient of thermal expansion between the silicon substrate 31 and the high density plasma oxide film to be embedded in the trench 35. Defects generated in the region are prevented from diffusing into the trench 35. A silicon nitride film (Si ₃ N ₄ ) may be used as the liner nitride film 38, and may be formed to a thickness of 20 μm to 100 μm.

Next, an insulating film, for example, a high density plasma oxide film 39, is formed to a thickness of 6000 kPa to 10000 kPa so that the trench 35 is sufficiently buried in the upper portion of the silicon substrate 31. At this time, the high-density plasma oxide film 39 uses a plasma deposition method using a silicon source and oxygen gas, preferably a chemical vapor deposition method (CVD) using a plasma.

As shown in FIG. 3G, the high-density plasma oxide film 39 is subjected to chemical mechanical polishing (CMP) until the surface of the pad nitride film 33 is exposed.

In the subsequent process, after further etching to remove the step between the high density plasma oxide film 39 and the silicon substrate 31, the wet etching using a phosphate solution (H ₃ PO ₄ ) to remove the pad nitride film 33 Proceed with the process.

At this time, since the pad oxide film 32 is a wetted etch rate LP-TEOS to remove the pad nitride film 33, only a small amount of the pad oxide film 32a remains as a part is lost. In the case of using a conventional thermal oxide film, there is almost no loss of the pad oxide film during wet etching of the pad nitride film.

As shown in FIG. 3H, a pre-cleaning process for removing the pad oxide layer 32a is performed prior to depositing the screen oxide layer. In this case, since the pad oxide film 32a is LP-TEOS having a fast wet etching rate, and the pad oxide film 32a remains after the pad nitride film 33 is removed, the wet etching time during the pre-cleaning process can be shortened. In particular, the thickness of the pad oxide film 32 was optimized to 50 kPa to 60 kPa when the pad oxide film 32 was first deposited, and a part of the pad nitride film 33 was consumed when the pad nitride film 33 was removed. .

As such, when the wet etching time is shortened during the pre-cleaning process, the depth of the moat M may be minimized.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above has the effect of simplifying the process by using the LP-TEOS fast wet etch rate as the pad oxide film can form the TCR only by cleaning and sidewall oxidation without adding a separate process for the TCR treatment.

In addition, instead of a method using a polymer, since the TCR is formed through sidewall oxidation after wet etching using cleaning, it is possible to secure a stable profile of the TCR and to control particles.

In addition, since the time of the pre-cleaning process for removing the pad oxide film can be reduced, there is an effect that can minimize the depth of the moat.

1 is a cross-sectional view illustrating a problem in a conventional STI device isolation method;

2A to 2H are cross-sectional views illustrating an STI device isolation method using a TCR technique according to the prior art;

3A to 3H are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 silicon substrate 32 pad oxide film

33: pad nitride film 35: trench

35a: Top corner of trench 35b: Top corner of trench

37 side wall oxide film 38 liner nitride film

39: high density plasma oxide film

Claims (7)

Forming a pad oxide film having a high wet etching rate on the silicon substrate; Forming a pad nitride film on the pad oxide film; Etching the pad nitride layer and the pad oxide layer using a device isolation mask; Forming a trench by etching the silicon substrate using a pattern stacked in the order of the pad oxide layer, the pad nitride layer, and the device isolation mask as a mask; Stripping the device isolation mask; Exposing the top corner of the trench by performing a wet cleaning process to etch the side surface of the pad oxide layer more quickly; And Rounding the top corner of the trench by performing sidewall oxidation on the surface of the trench including the exposed top corner; Device isolation method of a semiconductor device comprising a. The method of claim 1, The pad oxide film, Device separation method of a semiconductor device, characterized in that formed by LP-TEOS. The method of claim 2, The LP-TEOS is, A device isolation method for a semiconductor device, characterized in that formed to a thickness of 50 kHz to 200 kHz. The method of claim 1, Exposing the top corner of the trench, Device separation method of a semiconductor device, characterized in that the progress through the wet cleaning using HF solution. The method of claim 1, The sidewall oxidation is Device isolation method of a semiconductor device, characterized in that using wet oxidation or dry oxidation. The method of claim 1, Exposing the top corner of the trench, And further performing an isotropic etching process of rounding the bottom corner of the trench. The method of claim 1, After the sidewall oxidation, Forming a liner nitride film on the entire surface of the silicon substrate including the trench; Forming an insulating film on the liner nitride film to sufficiently fill the trench; Planarizing the insulating film until the surface of the pad nitride film is exposed; Selectively removing the pad nitride film and the liner nitride film; And Performing a wet pre-cleaning process to remove the pad oxide layer Device isolation method of a semiconductor device characterized in that it further comprises.