JP2000181699A - Program process control method and digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the miswriting of a program and to shorten the time for a shipment test by returning to the process of a shipment test program during a regular program process. SOLUTION: A CPU 15 receives a signal (a) and starts an interruption routine. The shipment test program issued by a host 12 is written to a RAM 16 through a path (d) passing through a host interface 13. A shipment test program load end command is outputted from the host 12 and outputted as a signal (b) to the CPU 15 through the host interface 13. The CPU 15 switches the process address to the head address of the shipment test program written in a ROM 16 and further starts the process of the shipment test program. Then a shipment test process forcible end command is outputted from the host 12 and inputted as a signal (c) to the CPU 15. The CPU 15 starts a system resetting process and perform the process of the regular program in a ROM 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program processing control method for a CPU in a digital signal processing system.

[0002]

2. Description of the Related Art A digital signal processing apparatus using a program processing control method according to the prior art is disclosed in Japanese Patent Application Laid-Open No. 1-246652 as related to the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional digital signal processing device. In FIG.
21 is a digital signal processor, 22 is a host, 23 is a host interface for interpreting a command from the host 22 and controlling each part of the digital signal processor 21 based on the contents of the command, and 24 is a host interface via the host interface 23 from the host 22. A buffer for storing the program input by the CPU 25, a selector 25 for connecting the EEPROM bus to one of the CPU bus and the buffer 24, a writing module 26 for writing the program input via the buffer 24 and the selector 25, An EEPROM 27 for erasing data, a CPU for processing program data in the EEPROM 26, and a CPU for exchanging data and commands with the host 22 via the host interface 23, and a CPU 28 for temporarily processing data by the CPU 27. Necessary storage equipment RAM used as a.
The host interface 23, the EEPROM 26,
The CPU 27 and the RAM 28 are connected by a bus.

FIG. 4 is a flowchart of a process performed by the digital signal processing device 21 according to the prior art. Less than,
The operation of the digital signal processing device 21 according to the prior art will be described with reference to FIG. When the power of the digital signal processing device 21 is turned on, a system reset is performed.
An instruction is given to connect the bus of the EEPROM 26 to the bus of the CPU 27. When the bus of the EEPROM 26 is connected to the bus of the CPU 27 in accordance with the above instruction, the processing of the regular program in the EEPROM 26 by the CPU 27 is started.

When a command for requesting a shipping test (hereinafter referred to as a shipping test mode request command) is output from the host 22 during the above-mentioned regular program processing by the CPU 27, the shipping test mode request command is signaled via the host interface 23. (f) is input to the CPU 27 and the selector 25. By the signal (f), the CPU 27
Enters a temporary processing stop state, and the selector 25
The PROM 26 bus is disconnected from the CPU 27 bus and connected to the buffer 24.

Next, the shipping test program is executed by the host 2
2 through the host interface 23 → buffer 24 → selector 25 (path of (e)).
Written to OM26. When all the shipping test programs are written into the EEPROM 26, the host 22
A command (hereinafter referred to as a shipment test program load end command) for notifying the fact is output from the host interface 23, and a signal (g) is output via the host interface 23 as a signal (g).
It is transmitted to the PU 27 and the selector 25. In response to the signal (g), the bus of the EEPROM 26 is disconnected from the buffer 24 and reconnected to the bus of the CPU 27, and the CPU 27 starts the processing of the shipping test program.

When the processing of the shipping test program ends, a command (hereinafter referred to as a shipping test processing forced termination command) notifying that the processing of the shipping test program has ended is output from the host 22, and the host interface The signal is input to the selector 25 as a signal (h) through the selector 23. By the above signal (h), EEPROM2
When the six buses are connected to the buffer 24, the regular program of the product is output from the host 22, and is written to the EEPROM 26 via the host interface 23 → buffer 24 → selector 25 (path of (e)). afterwards,
After the system reset, the host interface 2
3, the bus of the EEPROM 26 is connected to the bus of the CPU 27, and at the same time, the CPU 27
The processing of the regular program written in the OM 26 is executed. By repeating the above flow, debugging of the shipping test program and shipping test were performed.

[0008]

However, in the conventional digital signal processing apparatus as described above,
EEP for both regular program and shipping test program
There is a drawback that the size of the EEPROM becomes large in the case where it is resident in the ROM, and further, a buffer and a selector of a number of bytes (for example, 512 bytes) corresponding to one writing unit of the EEPROM are required to write a program in the EEPROM. Therefore, there are problems that the circuit scale is large, the configuration is complicated, and the cost is high.

In addition, since the regular program and the shipping test program are often rewritten to the EEPROM, after the test, the regular program as a final product is replaced with the EEPROM.
At the stage of writing to the PROM, an incorrect version of the regular program may be written, which has led to a delay in the shipping test process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and stores a shipping test program in a recording medium separate from a recording medium for a regular program to process the shipping test program. It is an object to provide a program processing control method and a digital signal processing device using the program control method.

[0011]

According to a first aspect of the present invention, there is provided a program processing control method for controlling a program processing in a digital signal processing apparatus including a ROM holding a regular program and a RAM. Loading a program from the outside into the RAM during the processing of the regular program, and loading the program from the processing of the regular program into the RAM after the loading of the program into the RAM is completed. Switching to the processing of
After the processing of the load program ends, a step of switching to the processing of the regular program.

In order to achieve the above object, a digital signal processing device according to a second aspect of the present invention comprises: a ROM for holding a regular program; and a RAM. , Load an external program into the RAM,
After the loading of the program into the RAM is completed, the processing is switched from the processing of the regular program to the processing of the program loaded into the RAM, and after the processing of the loading program is completed, control is performed so as to switch to the processing of the regular program. It is characterized by comprising control means.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a block diagram showing a configuration of a digital signal processing device according to Embodiment 1 of the present invention. In FIG. 1, reference numeral 11 denotes a digital signal processing device, reference numeral 12 denotes a host, reference numeral 13 denotes a host interface for interpreting a command from the host 12 and controlling each part of the digital signal processing device 11 based on the content of the command, and reference numeral 14 holds a regular program. ROM, 15 is R
A CPU 16 that performs various data processing according to a program stored in the OM 14, a RAM 16 used as a storage device temporarily required for data processing by the CPU 15,
It is. The host interface 13 and the ROM 1
4, the CPU 15 and the RAM 16 are connected by a bus.

FIG. 2 is a flowchart of a process performed by the digital signal processing device 11 according to the first embodiment of the present invention.

Hereinafter, the operation of the digital signal processing device 11 according to the first embodiment will be described with reference to FIG.
When the power of the digital signal processing device 11 is turned on, a system reset is performed, and the CPU 15 starts processing from the head address of the regular program in the ROM 14.

When a shipping test mode request command is issued from the host 12 during normal program processing, the host interface 13 interprets the command and outputs a C signal as a signal (a).
Transmit to PU15. The CPU 15 receives the signal (a),
Start the interrupt handling routine. By the interrupt processing routine, the shipping test program issued from the host 12 is written to the RAM 16 via the host interface 13 through the path (d).

All of the shipping test programs are RAM.
When written to the CPU 16, a shipment test program load end command is output from the host 12 and output to the CPU 15 via the host interface 13 as a signal (b). The CPU 15 receives the signal (b) and activates the interrupt processing routine. In this interrupt processing routine, the processing address is obtained from the regular program in the ROM 14 by R
It switches to the start address of the shipping test program written in AM16, and starts the processing of the shipping test program.

When the shipment test program processing is completed, a shipment test processing forced termination command is output from the host 12 and input to the CPU 15 as a signal (c) via the host interface 13. Upon receiving the signal (c), the CPU 15 starts an interrupt processing routine. The interrupt processing routine starts a system reset process and performs processing of a regular program in the ROM 14.

As described above, according to the digital signal processing device of the first embodiment of the present invention, the regular program
OM, the shipment test program is externally loaded into the RAM and temporarily stored, and the load program in the RAM is activated to execute the interruption test of the shipment test. Since the processing is returned to the processing of the regular program, the mistake of writing the program which occurs at the stage of writing the regular program into the EEPROM unlike the related art does not occur, and the time required for the shipping test process can be reduced. Further, as described above, in the conventional case where both the regular program and the shipping test program are resident in the EEPROM, the EEPROM is used.
There is a disadvantage that the OM size increases, but in the case of the present invention, the size can be reduced by the capacity of the shipping test program. Further, since the program is stored in the ROM instead of the conventional expensive EEPROM, a circuit group necessary for writing the program into the EEPROM is not required.
The cost of the device can be reduced. Further, in the present invention, the function of rewriting the program to the EEPROM is not required, and there is an effect that processing of various series of shipping test programs and debugging of the shipping test program itself can be easily performed with a simple configuration.

[0020]

According to the program processing control method according to the first aspect, the ROM holding the regular program and the RAM
A program processing control method for controlling program processing in a digital signal processing device comprising the steps of: loading a program from the outside into the RAM during the normal program processing; and after loading the program into the RAM, The method includes a step of switching from the processing of the regular program to the processing of the program loaded in the RAM, and a step of switching to the processing of the regular program after the processing of the load program is completed. When doing it,
Interruption processing of the shipping test program is performed during the normal program processing, and the processing returns to the normal program after the end of the test. Therefore, a program writing error which has occurred conventionally does not occur, and the time of the shipping test process can be reduced. effective.

Further, since a regular program is stored in a ROM instead of the EEPROM, and a circuit group necessary for writing the program in the EEPROM is not required, the size and cost of the device can be reduced by the capacity of the shipping test program. Can be planned.

In addition, there is no need for a function of rewriting a program to the EEPROM, so that it is possible to easily process various series of shipping test programs and debug the shipping test programs themselves with a simple configuration.

According to a second aspect of the present invention, there is provided a digital signal processing apparatus which includes a ROM for holding a regular program and a RAM, and performs program processing. After the program is loaded into the RAM and the program loading into the RAM is completed, the processing is switched from the processing of the regular program to the processing of the program loaded into the RAM. After the processing of the load program is completed, the processing of the regular program is completed. For example, when performing a shipment test of a product, an interruption process of a shipment test program is performed during the regular program process, and the process returns to the regular program after the test is completed. As a result, a program write error No, there is an effect that it is possible to achieve a time reduction of shipping test process.

Further, since a regular program is held in a ROM instead of an EEPROM, and a circuit group necessary for writing the program in the EEPROM is not required, the size and cost of the apparatus can be reduced by the capacity of the shipping test program. Can be planned. Further, the function of rewriting the program to the EEPROM is not required, and there is an effect that processing of various series of shipping test programs and debugging of the shipping test program itself can be easily performed with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a process performed by the digital signal processing device according to the first embodiment;

FIG. 3 is a block diagram showing a configuration of a digital signal processing device according to a conventional technique.

FIG. 4 is a flowchart of a process performed by a conventional digital signal processing device.

[Explanation of symbols]

 11, 21 Digital signal processing device 12, 22 Host 13, 23 Host interface 14 ROM 15, 27 CPU 16, 28 RAM 24 Buffer 25 Selector 26 EEPROM

Claims (2)

[Claims] A ROM for holding a regular program;
A program processing control method for controlling program processing in a digital signal processing device having an AM, wherein a step of loading an external program into the RAM during the normal program processing, and after the program loading into the RAM is completed. Switching from the processing of the regular program to the processing of the program loaded in the RAM; and switching to the processing of the regular program after the processing of the load program is completed. Method. A ROM for holding a legitimate program;
A digital signal processing device comprising an AM and performing a program processing, wherein an external program is loaded into the RAM during the regular program processing, and after the program loading into the RAM is completed, the processing from the regular program processing is performed. R
A digital signal processing apparatus comprising: a control unit that switches to processing of a program loaded in an AM, and switches to processing of the regular program after the processing of the load program ends.