JP2000180517A - Test circuit of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately increase a test control signal without enlarging the size of a circuit by arranging a plurality of buffer cells with a different input threshold voltage where output is changed from a high level to a low one corresponding to an input voltage from a test input terminal and by generating a plurality of test control signals according to the input voltage. SOLUTION: A signal being inputted from an input terminal for test of a semiconductor integrated circuit is inputted into buffer cells 21, 22, 23, and 24 via a pad 20 inside the integrated circuit. In this case, in the buffer cells 21, 22, 23, and 24, an input threshold voltage (input VTH) where high and low levels are changed according to voltage being inputted into the input terminal is set to a different voltage value, thus making different the state of the high and low levels being outputted from the four kinds of the buffer cells according to the input voltage of the input terminal. The output becomes control signals a-e for test via decode circuits 27, 28, 29, 30, and 31 of the next stage, and only one of them is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit for a semiconductor integrated circuit, and more particularly to a test circuit for a semiconductor integrated circuit for accurately increasing a test control signal without increasing a circuit scale.

[0002]

2. Description of the Related Art Conventionally, as a test circuit for a circuit integrated inside an integrated circuit device, for example, when four types of tests are performed, two test terminals are provided from outside the integrated circuit device to form a binary circuit. There is a test circuit which receives a signal of the same type, decodes the signal inside the integrated circuit device, provides four types of test control signals, and performs different tests.

FIG. 3 shows that two types of tests are performed.
Test input terminals 40 and 41 are provided, and inverter circuits 42 and 43 and decode circuits 44, 45, 46 and 47 are provided.
Is a general test circuit for generating four types of test control signals a to d via the test circuit.

However, according to this test circuit, only three squares of the number of test input terminals are required to set test types, such as three test input terminals for up to eight types of tests and four test inputs for up to sixteen types of tests. However, there is a problem that the number of input terminals is greatly increased by increasing the number of tests.

As a method for solving such a problem, for example, as disclosed in Japanese Patent Application Laid-Open No. 9-89995, a resistor and a comparator are provided inside an integrated circuit device and voltage is divided by the resistor. There is a method of comparing the input voltage with the input voltage value. According to this method, an increase in the number of test terminals can be suppressed even when three or more types of tests are performed.

[0006]

However, the method described in Japanese Patent Application Laid-Open No. 9-89995 has the following problems. (1) In order to increase the number of control signals, it is necessary to add analog circuits such as resistors and comparators inside the integrated circuit device, thereby increasing the chip area and consequently the circuit scale. There was a problem that it would increase. (2) Also, due to fluctuations in characteristics such as temperature, power supply voltage, and process, the voltage value divided by the resistor may not be as expected, and as a result, a desired control test signal may not be obtained. That is, there is a problem with the accuracy of the control circuit.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a test circuit for a semiconductor integrated circuit which can increase the number of test control signals accurately without increasing the circuit scale.

[0008]

According to the present invention, in order to achieve the above object, a test terminal is provided outside a semiconductor integrated circuit, a signal is input from a test input terminal, and a signal is input into the semiconductor integrated circuit. In the test circuit of a semiconductor integrated circuit, which generates a test control signal by decoding with a test control signal and performs different types of tests based on the test control signal, an input whose output switches between high and low in accordance with an input voltage from a test input terminal It is an object of the present invention to provide a test circuit for a semiconductor integrated circuit, in which a plurality of buffer cells having different threshold voltages are arranged and a plurality of test control signals are generated according to an input voltage.

In the above configuration, it is desirable to increase the number of buffer cells by n (n is a natural number), and it is desirable to increase the number of test input terminals by n (n is a natural number).

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
An embodiment of the present invention will be described in detail.

FIG. 1 is a diagram showing a test circuit of a semiconductor integrated circuit according to an embodiment of the present invention. This test circuit inputs a signal input from a pad 20 and a test input terminal of the semiconductor integrated circuit via the pad 20.
Types of buffer cells 21, 22, 23, 24, a P-channel transistor 25, and an N-channel transistor 26
And decode circuits 27, 28, 29, and 3 for decoding the five outputs of buffers 21, 22, 23, and 24, respectively.
0, 31.

A test operation in the test circuit of the semiconductor integrated circuit having the above configuration will be described with reference to FIGS. In FIG. 1, four signals are input from one input terminal.
The example which produces | generates the test control signal of a kind is shown. First, a signal input from a test input terminal of a semiconductor integrated circuit is input to four types of buffer cells 21, 22, 23, and 24 via a pad 20 inside the integrated circuit. Here, in the buffer cells 21, 22, 23, and 24, input threshold voltages (hereinafter, referred to as input VTH) at which high and low are switched according to the voltage input to the input terminal are set to different voltage values. . Therefore, the high / low states output from the four types of buffer cells differ according to the input voltage of the input terminal.

This will be described with a specific example. For example,
The power supply voltage of the semiconductor integrated circuit is set to 5 V, and the buffer cell 2
Input VTHs of 1, 22, 23, and 24 are set to 3.0, respectively.
It is assumed that V, 2.5 V, 2.0 V, and 1.5 V are set.
Then, the voltage input to the input terminal is 3.3 V, 2.8.
When V, 2.3 V, 1.8 V, and 0 V are set, five output states of the buffer cells 21, 22, 23, and 24 occur as shown in FIG. This output becomes the test control signals a to e via the decoding circuits 27, 28, 29, 30, 31 of the next stage, and only one of them is selected.

At this time, for example, if the control signal e selected when 0 V is input is assigned to the signal in the actual use mode, the remaining four types of control signals can be used as the signals for the test mode. .

Here, the buffer cells having different inputs VTH are formed by connecting two stages of inverter circuits. The input VTH can be operated by adjusting the ratio of the channel width (W) between the P channel and the N channel of the first-stage inverter circuit. Generally, when the power supply voltage is 5 V, the input VTH of the buffer cell connected to the input terminal is TTL (Transistor Transistor Transistor).
tor Logic) 1.4V for interface, CM
The voltage is set to 2.5 V in the case of an OS (Complementary MOS) interface.

The input VTH is less affected by fluctuations in characteristics such as power supply voltage, temperature, and process than analog circuits such as resistors and comparators. Therefore, the test control circuit can be realized with high accuracy, and as a result, it is possible to easily increase the types of control signals as the number of buffer cells increases.

In FIG. 1, a P-channel transistor 25 and an N-channel transistor 26 are protection transistors of an input cell circuit, and both constitute a diode. Normally, it is essential that the protection transistor be arranged in the input / output section in order to guarantee the surge withstand voltage of the semiconductor integrated circuit. However, in the case of the input cell circuit, this protection transistor occupies the largest size. Become.

Therefore, even if the four types of buffer cells 21, 22, 23, and 24 shown in FIG. 1 are arranged inside the input cell circuit, it is almost the same as an ordinary input cell in which only one type of buffer cell is arranged. Input cells of no size can be realized. That is, even if the number of test control signals is increased, it can be realized without increasing the chip size of the semiconductor integrated circuit.

Further, according to the present invention, it is possible to increase the number of test control signals in an exponential series as the number of test input terminals is increased. For example, four types of buffer cells 21 as shown in FIG.
When the input cells to which the cells 22, 23, and 24 are connected are used, five types of tests can be realized with one cell as described above. Therefore, when two cells are used, five types of test control signals are output. Decoding circuit (not shown) next to
Can be added to generate 5 × 5 = 25 test control signals.

In the same manner, when three are used, 25 ×
5 = 125 tests can be realized. Again, this is 25 test patterns with 2 test input terminals, 3
This means that 125 different tests are possible with a book. Moreover, as described above, since the input cell circuit can be realized with almost the same size as a normal circuit, increasing the number of test input terminals has a very small effect on the chip size of the semiconductor integrated circuit.

[0021]

As described above, according to the semiconductor integrated circuit test circuit of the present invention, the buffer cells having different input threshold voltages whose output switches between high and low in accordance with the input voltage from the test input terminal. Are arranged, and a plurality of test control signals are generated according to the input voltage. Therefore, without increasing the circuit scale,
The test control signal can be increased with high accuracy.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a test circuit of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an output state of a buffer cell.

FIG. 3 is a diagram showing a configuration of a test circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 Reference Signs 20 pad 21 buffer cell 22 buffer cell 23 buffer cell 24 buffer cell 25 p-channel transistor 26 n-channel transistor 27 decoding circuit 28 decoding circuit 29 decoding circuit 30 decoding circuit 31 decoding circuit

Claims (3)

[Claims] A test terminal is provided outside a semiconductor integrated circuit, a signal is input from the test input terminal, and the signal is decoded inside the semiconductor integrated circuit to generate a test control signal. In a test circuit of a semiconductor integrated circuit for performing different types of tests according to a control signal, a plurality of buffer cells having different input threshold voltages whose output switches between high and low in accordance with an input voltage from the test input terminal are arranged. A test circuit for a semiconductor integrated circuit, wherein a plurality of test control signals are generated according to the input voltage. 2. The test circuit for a semiconductor integrated circuit according to claim 1, wherein in the test circuit for the semiconductor integrated circuit, the number of the buffer cells is increased by n (n is a natural number). 3. The test circuit according to claim 1, wherein the number of the test input terminals is increased by n (n is a natural number) in the test circuit of the semiconductor integrated circuit. .