JP2000174393A - Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device - Google Patents

Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device

Info

Publication number
JP2000174393A
JP2000174393A JP34524498A JP34524498A JP2000174393A JP 2000174393 A JP2000174393 A JP 2000174393A JP 34524498 A JP34524498 A JP 34524498A JP 34524498 A JP34524498 A JP 34524498A JP 2000174393 A JP2000174393 A JP 2000174393A
Authority
JP
Japan
Prior art keywords
iii nitride
nitride semiconductor
group iii
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP34524498A
Other languages
Japanese (ja)
Inventor
Toshiyuki Matsui
俊之 松井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP34524498A priority Critical patent/JP2000174393A/en
Publication of JP2000174393A publication Critical patent/JP2000174393A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a III nitride semiconductor device having an epitaxial layer which has less through dislocation and does not have cracks and whose thickness is not less than 1 μm on a Si substrate, and to provide a, and the manufacturing method thereof. SOLUTION: In a III nitride semiconductor, masks 3m are locally formed on a semiconductor substrate 1 or a first III nitride semiconductor layer 2b formed of Alx Gay In1-x-yN (0<=x and y and 0<=x+y<=1), and a second III nitride semiconductor layer 4 formed of AlxGayIn1-x-yN (0<=x and y and 0<=x+y<=1) is stacked. The masks are formed by using a material whose surface energy is lower than nitride oxide or silicon nitride.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】基板上に III族窒化物がエピ
タキシャル成長されてなる III族窒化物半導体とその選
択成長またはELO(epitaxy of lateral over growt
h)を含む製造方法、およびレーザダイオードを含む II
I族窒化物半導体装置に関する。
BACKGROUND OF THE INVENTION A group III nitride semiconductor obtained by epitaxially growing a group III nitride on a substrate, and its selective growth or ELO (epitaxy of lateral over growt).
h) including manufacturing method and including laser diode II
The present invention relates to a group I nitride semiconductor device.

【0002】[0002]

【従来の技術】直接遷移で、しかも光学エネルギーギャ
ップが1.6 〜6.2 eVの範囲で制御可能なAlx Gay
1-x-y N系材料を使った半導体レーザーや発光ダイオ
ードが試作されている。Alx Gay In1-x-y N系材
料を使った上記の発光素子には、格子や熱膨張係数の整
合性の良さから、主としてサファイア基板やスピネル
(MgAl2 4 )基板等が広く使われている。そし
て、シリコン(Si)やマグネシウム(Mg)を添加す
ることによるn型やp型の価電子制御や、Alx Ga y
In1-x-y Nにおけるxやyの値を変えることによる光
学エネルギーギャップの制御が実現され、ダブルへテロ
(DH)構造のレーザダイオードが試作されている。し
かし、絶縁性基板を使用するので基板裏面に電極を取り
付けることができない、また、炭化ケイ素(SiC)基
板を使ってダブルへテロ(DH)構造のレーザが試作さ
れているが、SiC基板は高価である、などの問題があ
る。
2. Description of the Related Art A direct transition and optical energy gap
Al controllable in the range of 1.6 to 6.2 eVxGayI
n1-xySemiconductor lasers and light emitting diodes using N-based materials
Mode is being prototyped. AlxGayIn1-xyN-based material
The above-mentioned light-emitting device using a material has a lattice and a coefficient of thermal expansion.
Mainly sapphire substrate and spinel
(MgAlTwoOFour) Substrates are widely used. Soshi
And add silicon (Si) and magnesium (Mg)
Control of n-type and p-type by controllingxGa y
In1-xyLight by changing the value of x and y in N
Control of chemical energy gap and double heterogeneity
A laser diode having a (DH) structure has been prototyped. I
However, since an insulating substrate is used, take electrodes on the back of the substrate.
Not attachable, and silicon carbide (SiC) groups
Prototype laser with double heterostructure (DH) using plate
However, there are problems such as the SiC substrate being expensive.
You.

【0003】その対策として、最も一般的で安価なSi
基板上へGaNなどの III族窒化物からなるDH構造な
どを形成することが望まれるが、厚さが1μm 以上のエ
ピタキシャル膜を成長すると割れが生じてしまう。Si
基板上に III族窒化物からなるDH構造を形成するとき
に III族窒化物からなるエピ層が割れてしまう原因とし
て、次の2点が考えられる。
As a countermeasure, the most common and inexpensive Si
Although it is desired to form a DH structure made of a group III nitride such as GaN on a substrate, cracks occur when an epitaxial film having a thickness of 1 μm or more is grown. Si
The following two points can be considered as causes of the breakage of the epitaxial layer made of the group III nitride when the DH structure made of the group III nitride is formed on the substrate.

【0004】1) Siの格子定数は0.5431nmであるの
で、Si(1,1,1) 面上での原子間隔は0.3840nm(=5.43
1/√2 )となる。これに対して、GaNの格子定数は0.
3189nmなので、格子間隔はGaNの方が狭く、約17 %の
格子不整合が存在し、Si(1,1,1) 面上にヘテロエピ成
長したGaN膜には引っ張り応力が発生する。
1) Since the lattice constant of Si is 0.5431 nm, the atomic spacing on the Si (1,1,1) plane is 0.3840 nm (= 5.43 nm).
1 / √2). In contrast, the lattice constant of GaN is 0.
Since it is 3189 nm, the lattice spacing of GaN is smaller than that of GaN, there is about 17% lattice mismatch, and tensile stress is generated in the GaN film heteroepitaxially grown on the Si (1,1,1) plane.

【0005】2) 線膨張係数はSiでは2.6 ×10-6-1
であるのに対して、GaNでは5.6×10-6-1と大き
く、温度を下げるときのGaNの収縮の方が大きく、成
長温度から室温に降温する際にGaNに引っ張り応力が
発生する。
2) The linear expansion coefficient of Si is 2.6 × 10 -6 K -1
On the other hand, GaN is as large as 5.6 × 10 −6 K −1, and the shrinkage of GaN when the temperature is lowered is larger. When the temperature is lowered from the growth temperature to room temperature, tensile stress is generated in GaN.

【0006】この問題は、サファイア基板上にGaNの
厚膜成長を行った場合でも同様である。サファイア基板
はGaNとの格子整合性、および線膨張係数の整合性に
おいてはSiより良いが、その上に数十μm 以上のGa
N厚膜を形成するとSi基板への成長と同様、クラック
が発生する。
This problem is the same even when a GaN thick film is grown on a sapphire substrate. The sapphire substrate is better than Si in lattice matching with GaN and matching in linear expansion coefficient, but has a tens of μm or more Ga
When an N thick film is formed, cracks occur as in the case of growth on a Si substrate.

【0007】しかし、最近、サファイア基板上で、Si
2 をマスクに使ったELO(epitaxy of lateral ove
r growth)成長により膜厚100μm 程度でもクラック
のないGaN厚膜が報告されている。これはELO成長
により、結晶欠陥が減少するために、クラックが入りに
くくなると解釈されている。
However, recently, on a sapphire substrate, Si
ELO (epitaxy of lateral ove) using O 2 as a mask
A growth-free GaN thick film having a thickness of about 100 μm due to growth has been reported. This is interpreted that the crystal defects are reduced by the ELO growth, so that cracks are hardly formed.

【0008】また、Si基板上に直接エピタキシャル成
長したGaNエピタキシャル膜にはSi基板とGaN層
との格子不整合によって生じた貫通転位が生じ、デバイ
ス特性を劣化させるという問題もある。
Further, threading dislocations are generated in a GaN epitaxial film directly epitaxially grown on a Si substrate due to a lattice mismatch between the Si substrate and the GaN layer, thereby deteriorating device characteristics.

【0009】[0009]

【発明が解決しようとする課題】ところが、ELO成長
のメカニズムとして、SiO2 やSiN等の表面に未結
合手が少ない材料上では化学的な分解が行われないた
め、この成長方法はMOCVDやMOMBE等の化学的
な成長方法にのみ有効であり、金属蒸気を直接供給する
MBE(電子ビームエピタキシー)や蒸着等では困難で
あると推定されている。
However, as a mechanism of ELO growth, chemical decomposition is not performed on a material such as SiO 2 or SiN which has few dangling bonds on the surface. Therefore, this growth method uses MOCVD or MOMBE. It is estimated that the method is effective only for chemical growth methods such as MBE (Electron Beam Epitaxy) or vapor deposition which directly supplies a metal vapor.

【0010】本発明の目的は、厚さ1μm 以上の厚いエ
ピタキシャル層を成長しても割れが生じないようにし、
さらにSi基板上に貫通転位の少ない III窒化物半導体
を提供し、そのような III窒化物半導体の製造方法を提
供することにある。
An object of the present invention is to prevent cracking even when a thick epitaxial layer having a thickness of 1 μm or more is grown,
Another object of the present invention is to provide a III nitride semiconductor having few threading dislocations on a Si substrate, and to provide a method for manufacturing such a III nitride semiconductor.

【0011】[0011]

【課題を解決するための手段】上記の目的を達成するた
め、半導体基板上に、または半導体基板上のAlx Ga
y In1-x-y N(但し、0≦x,y、かつ0≦x+y≦
1)からなる第1の III族窒化物半導体層上に、マスク
が局所的に形成されており、さらにAlx Ga y In
1-x-y N(但し、0≦x,y、かつ0≦x+y≦1)か
らなる第2の III族窒化物半導層が積層されてなる III
族窒化物半導体において、前記マスクは酸化ケイ素また
は窒化ケイ素より表面エネルギーの低い材料からなるこ
ととする。
Means for Solving the Problems To achieve the above object,
Al on the semiconductor substrate or on the semiconductor substratexGa
yIn1-xyN (where 0 ≦ x, y and 0 ≦ x + y ≦
1) forming a mask on the first group III nitride semiconductor layer
Are locally formed, and AlxGa yIn
1-xyN (however, 0 ≦ x, y and 0 ≦ x + y ≦ 1)
Formed by stacking a second group III nitride semiconductor layer
In the group nitride semiconductor, the mask is silicon oxide or
Is made of a material with lower surface energy than silicon nitride.
And

【0012】前記表面エネルギーの低い材料は、少なく
ともフッ化カルシウム(CaF2 )、フッ化バリウム
(BaF2 )またはフッ化ストロンチウム(SrF2
のいずれかのII族フッ化物であると良い。前記半導体基
板は表面の面方位が(1,1,1) であるシリコン基板であ
り、前記マスクはシリコン基板の<1,1,0> 方向に平行な
辺を有する短冊形状であると良い。
The material having a low surface energy is at least calcium fluoride (CaF 2 ), barium fluoride (BaF 2 ) or strontium fluoride (SrF 2 ).
Any of the group II fluorides is preferred. Preferably, the semiconductor substrate is a silicon substrate having a surface orientation of (1,1,1), and the mask is a strip having sides parallel to the <1,1,0> direction of the silicon substrate.

【0013】半導体基板上に、または半導体基板上のA
x Gay In1-x-y N(但し、0≦x,y、かつ0≦
x+y≦1)からなる第1の III族窒化物半導体層上
に、マスクが局所的に形成されており、さらにAlx
y In1-x-y N(但し、0≦x,y、かつ0≦x+y
≦1)からなる第2の III族窒化物半導層が積層されて
なる上記の III族窒化物半導体の製造方法において、前
記第2の III族窒化物半導層はMOCVD、MOMB
E、MBEまたは蒸着によってELO成長されると良
い。
On a semiconductor substrate or on a semiconductor substrate
l x Ga y In 1-xy N ( where, 0 ≦ x, y, and 0 ≦
x + y ≦ 1), a mask is locally formed on the first group III nitride semiconductor layer, and Al x G
a y In 1-xy N (where 0 ≦ x, y and 0 ≦ x + y
.Ltoreq.1), wherein the second group III nitride semiconductor layer is laminated, and the second group III nitride semiconductor layer is MOCVD, MOMB
It is preferable to perform ELO growth by E, MBE or vapor deposition.

【0014】前記II族フッ化物層の成膜はII族フッ化物
をターゲットに用いてスパッタにより形成されると良
い。前記II族フッ化物層のマスクはフッ酸によるエッチ
ングによって形成されると良い。
Preferably, the group II fluoride layer is formed by sputtering using a group II fluoride as a target. The group II fluoride layer mask is preferably formed by etching with hydrofluoric acid.

【0015】上記のシリコン基板を用いた III族窒化物
半導体を用いた III族窒化物半導体装置において、前記
III族窒化物半導体装置はレーザーダイオードであると
良い。本発明に係る III族窒化物半導体に用いたII族フ
ッ化物の表面エネルギーは酸化ケイ素や窒化ケイ素のそ
れより低いので、次のようにIII 族窒化物半導体の選択
成長が優れて行うことができる。
In the above-described group III nitride semiconductor device using a group III nitride semiconductor using a silicon substrate,
The group III nitride semiconductor device is preferably a laser diode. Since the surface energy of the group II fluoride used for the group III nitride semiconductor according to the present invention is lower than that of silicon oxide or silicon nitride, selective growth of the group III nitride semiconductor can be performed excellently as follows. .

【0016】一般に表面エネルギーの低い材料の上に、
それより表面エネルギーが高い物質を堆積した場合、堆
積過程において表面エネルギーの差により、凝集が生じ
る。これは、油の上に水を滴下した場合にみられる現象
と同じである。本発明に係るIII族窒化物半導体の成長
をの場合、Si基板上にIII 族窒化物半導体を薄く形成
し、その上に表面エネルギーの小さい物質(II 族フッ化
物) マスクを局所的に形成する。局所的に形成すること
により、その表面にはIII 族窒化物半導体の露出部を形
成する。その後再びIII 族窒化物半導体を形成すると、
表面エネルギーの低い材料上では、ちょうど水がはじか
れたようになるため、選択的に露出部上にのみ成長され
る。
Generally, on a material having a low surface energy,
When a substance having a higher surface energy is deposited, aggregation occurs due to a difference in surface energy during the deposition process. This is the same phenomenon that occurs when water is dropped on oil. In the case of growing a group III nitride semiconductor according to the present invention, a group III nitride semiconductor is formed thinly on a Si substrate, and a material (group II fluoride) mask having a small surface energy is locally formed thereon. . By locally forming, an exposed portion of the group III nitride semiconductor is formed on the surface. Thereafter, when a group III nitride semiconductor is formed again,
On materials with low surface energy, the water is just repelled, so it is selectively grown only on the exposed parts.

【0017】II族フッ化物の表面エネルギーは酸化ケイ
素や窒化ケイ素のそれより低いので、MOCVDやMO
MBE(有機金属分子線エピタキシー)は勿論、酸化ケ
イ素や窒化ケイ素をマスクとした場合には選択成長が不
可能であったMBE(分子線エピタキシー)あるいは蒸
着によってもELOまたは選択成長が可能になる。
Since the surface energy of Group II fluoride is lower than that of silicon oxide or silicon nitride, MOCVD or MO
ELO or selective growth can be performed by MBE (molecular metal epitaxy) or MBE (molecular beam epitaxy) or vapor deposition, which cannot be performed selectively using silicon oxide or silicon nitride as a mask, as well as MBE (organic metal molecular beam epitaxy).

【0018】[0018]

【発明の実施の形態】実施例1 図1は本発明に係る製造工程を示す III窒化物半導体の
基板面に垂直な断面図であり、(a)下地層形成後、
(b)マスク形成後であり、(c) III窒化物層形成後
である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a cross-sectional view perpendicular to the substrate surface of a III nitride semiconductor showing a manufacturing process according to the present invention.
(B) After forming the mask and (c) after forming the III nitride layer.

【0019】Si基板1の基板面は{1,1,1 }であり、
断面はSi基板の{1,0,0 }面である。先ず、Si基板
10の全面にMBEによりAlNのバッファ層2a次い
で下地GaN2bを成膜した(図1(a))。成膜条件
は次の通りである。基板温度を600 ℃に保持し、基板へ
窒素ラジカルの照射とAl蒸気の供給を同時に行い、厚
さ20nmのAlNのバッファ層2aを形成した。このと
き、Si基板表面の窒化を防止するため、窒素ラジカル
の照射開始はAlの供給開始に遅れてはならない。次に
基板温度を800 ℃に昇温し、窒素ラジカルとGa蒸気
(蒸気圧を1×10 -4Paとした)を供給して、厚さ300
nmの下地GaN2bを形成した。
The substrate surface of the Si substrate 1 is {1,1,1},
The cross section is the {1,0,0} plane of the Si substrate. First, the Si substrate
AlN buffer layer 2a next to MBN 10
Then, a base GaN 2b was formed (FIG. 1A). Deposition conditions
Is as follows. Maintain substrate temperature at 600 ℃
Simultaneous irradiation of nitrogen radicals and supply of Al vapor
An AlN buffer layer 2a having a thickness of 20 nm was formed. This and
Nitrogen radicals to prevent nitridation of the Si substrate surface.
Should not be delayed from the start of Al supply. next
Raise the substrate temperature to 800 ℃, nitrogen radicals and Ga vapor
(The vapor pressure is 1 × 10 -FourPa) and supply a thickness of 300
A base GaN 2b of nm was formed.

【0020】その後、500 ℃まで基板温度を下げ、Ca
2 をターゲットに用いてスパッタにより膜厚100 nmの
CaF2 層3を形成した。そして基板を一度取り出し、
フォトリソグラフィによりパターンを形成し、フッ酸溶
液で短冊状のCaF2 のマスク3mを形成した。(図1
(b))最後に、MBEによりGaNからなる III窒化
物層4を形成した。このときのGaNの成長条件は下地
層のGaNと同じとした。厚さ4μm 程度の成長を行う
とマスクの端部に段差のない平滑な表面を有するエピタ
キシャル層( III窒化物4)が得られた。
Thereafter, the substrate temperature is lowered to 500 ° C.
A CaF 2 layer 3 having a thickness of 100 nm was formed by sputtering using F 2 as a target. And take out the board once,
A pattern was formed by photolithography, and a strip-shaped CaF 2 mask 3m was formed with a hydrofluoric acid solution. (Figure 1
(B)) Finally, a GaN III nitride layer 4 was formed by MBE. The GaN growth conditions at this time were the same as those of the underlying layer GaN. When the growth was performed to a thickness of about 4 μm, an epitaxial layer (III nitride 4) having a smooth surface without a step at the end of the mask was obtained.

【0021】従来のようにSi基板にMBE直接成長し
た場合には、1μm の厚さがクラックの生じない限界
で、また貫通転移の密度は約1010個/cm2 であった
が、この実施例では4 μm の厚膜の成長を行ってもクラ
ックは発生せず、貫通転移の密度は約107 個/cm2 と従
来に比べ約1/1000に減らすことができた。 実施例2 実施例1におけるマスク材料をCaF2 からSrF2
たはBaF2 に変え、他は同じ条件でELO成長を行っ
たところ、いずれの場合も、実施例1と同様に、厚さ4
μm 程度まで表面は平滑であり、貫通転移の密度の小さ
いエピタキシャル層が得られた。 実施例3 実施例1における III窒化物のエピタキシャル成長法を
MBEからMOCVDに変えた。MBEと同様にクラッ
クのないエピタキシャル層がSi(1,1,1) 面基板上に形
成できた。 実施例4 実施例1のエピタキシャル成長をレーザダイオードの試
作に適用した。
When MBE was directly grown on a Si substrate as in the prior art, the thickness of 1 μm was at the limit where cracks did not occur, and the density of threading dislocation was about 10 10 / cm 2. In the example, no crack was generated even when a 4 μm thick film was grown, and the density of threading dislocations was reduced to about 10 7 / cm 2, which was about 1/1000 of the conventional value. Example 2 ELO growth was performed under the same conditions as in Example 1, except that the mask material in Example 1 was changed from CaF 2 to SrF 2 or BaF 2.
An epitaxial layer having a smooth surface and a small density of threading dislocation was obtained up to about μm. Example 3 The method of epitaxial growth of III nitride in Example 1 was changed from MBE to MOCVD. Like the MBE, a crack-free epitaxial layer could be formed on the Si (1,1,1) plane substrate. Example 4 The epitaxial growth of Example 1 was applied to a prototype laser diode.

【0022】図2はSi基板とCaF2 の短冊状マスク
の関係を示す斜視図である。CaF 2 の短冊状のマスク
3mの長手方向NはSi基板1の<1/2,1/2,1> 方向に平
行でり、GaNの劈開方向<2,1,1,0> と一致するSiの
劈開方向<1,1,0> に対して垂直である。マスク幅は2 μ
m 、マスク間隔は10μm とした。
FIG. 2 shows a Si substrate and CaFTwoStrip mask
It is a perspective view which shows the relationship of. CaF TwoThe strip-shaped mask
The longitudinal direction N of 3 m is flat in the <1 / 2,1 / 2,1> direction of the Si substrate 1.
Of Si that matches the GaN cleavage direction <2,1,1,0>
It is perpendicular to the cleavage direction <1,1,0>. Mask width is 2 μ
m and the mask interval were 10 μm.

【0023】このようにしてELO成長した層上にさら
にエピタキシャル成長を行いダブルヘテロ構造を作製
し、外部狭窄構造のレーザを作製した。図3は本発明に
係る III窒化物の製造方法によるレーザダイオードの断
面図である。AlNのバッファ層2aおよびGaN層2
bからなる厚さ300 nmの下地層、厚さ5 μm のELO成
長したGaN層をコンタク層4aとし、以降、厚さ0.5
μm のAlGaN層のnクラッド層4b、厚さ50nmのG
aInN層の活性層4c、厚さ0.5 μm のAlGaN層
のpクラッド層4d、厚さ0.5 μm のGaN層をpキャ
ップ層4eとして順次積層した。そして、pキャップ層
4e上にSiO2 の電流阻止層5を間隔5μm で形成し
た後(電流阻止層の間隔部はマスク間隔の中央に位置さ
せる)、Au/Niからなる上部電極6aを形成して、
外部電流狭窄構造を構成した。基板の裏側にはAl/T
iからなる下部電極6bを形成した。
A double heterostructure was fabricated by epitaxial growth on the layer grown by ELO in this manner, and a laser having an external constriction structure was fabricated. FIG. 3 is a sectional view of a laser diode manufactured by the method for producing a III nitride according to the present invention. AlN buffer layer 2a and GaN layer 2
The contact layer 4a is made of a 300 nm thick underlayer made of Eb and a 5 μm thick ELO-grown GaN layer.
μm AlGaN n-cladding layer 4b, 50 nm thick G
An active layer 4c of an aInN layer, a p-cladding layer 4d of an AlGaN layer having a thickness of 0.5 μm, and a GaN layer having a thickness of 0.5 μm were sequentially laminated as a p-cap layer 4e. Then, after forming a current blocking layer 5 of SiO 2 at a spacing of 5 μm on the p cap layer 4e (the spacing of the current blocking layer is located at the center of the mask spacing), an upper electrode 6a made of Au / Ni is formed. hand,
An external current confinement structure was constructed. Al / T on back side of substrate
A lower electrode 6b made of i was formed.

【0024】このような構造では、 III窒化物層の劈開
面に垂直なレーザストライプ方向と短冊状のマスク3m
の長手方向はともに平行になるので、CaF2 からなる
マスク3mのない部分にストライプが位置するように設
定でき、劈開面を光共振器面としたレーザーダイオード
を作製可能となり、また、レーザーダイオードにはマス
ク3mによって遮られることなく上部電極6aから基板
側の下部電極6bに電流を流すことができた。
In such a structure, the laser stripe direction perpendicular to the cleavage plane of the III nitride layer and the strip-shaped mask 3 m
Since the longitudinal directions are parallel to each other, it is possible to set the stripe so as to be located at a portion without the mask 3m made of CaF 2 , and it is possible to manufacture a laser diode having a cleavage plane as an optical resonator surface. The current was able to flow from the upper electrode 6a to the lower electrode 6b on the substrate side without being interrupted by the mask 3m.

【0025】[0025]

【発明の効果】本発明によれば、半導体基板上に、また
は半導体基板上のAlx Gay In1- x-y N(但し、0
≦x,y、かつ0≦x+y≦1)からなる第1の III族
窒化物半導体層上に、マスクを局所的に形成し、さらに
Alx Gay In1-x-y N(但し、0≦x,y、かつ0
≦x+y≦1)からなる第2の III族窒化物半導層を積
層してなるIII 族窒化物半導体において、前記マスクを
酸化ケイ素または窒化ケイ素より表面エネルギーの低
い、例えばCaF2 、BaF2 またはSrF2 などの、
材料からなるようにしたため、酸化ケイ素または窒化ケ
イ素のマスクでは不可能だった、MBEや蒸着により第
2の III族窒化物半導層を積層することができるように
なり、この III族窒化物半導層中の貫通転移密度は低
く、数μm 以上の厚膜を得ることができるようになる。
According to the present invention, on a semiconductor substrate, or on a semiconductor substrate Al x Ga y In 1- xy N ( where 0
≦ x, y, and the 0 ≦ x + y ≦ 1) a first group III nitride semiconductor layer made of, locally forming a mask, further Al x Ga y In 1-xy N ( where, 0 ≦ x , Y, and 0
In ≦ x + y ≦ 1) second formed by laminating a Group III nitride Hanshirubeso III group nitride semiconductor formed of a low surface energy than silicon oxide or silicon nitride the mask, CaF 2, BaF 2 or such as SrF 2,
The second group III nitride semiconductor layer can be laminated by MBE or vapor deposition, which was not possible with a silicon oxide or silicon nitride mask because the material was made of a material. The threading dislocation density in the conductive layer is low, and a thick film of several μm or more can be obtained.

【0026】また、Siを基板上に作製した III族窒化
物半導層を用いて、劈開面を光共振器面としたレーザー
ダイオードを作製可能となる。
Further, a laser diode having a cleavage plane as an optical resonator plane can be manufactured by using a group III nitride semiconductor layer in which Si is formed on a substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る製造工程を示す III窒化物半導体
の基板面に垂直な断面図であり、(a)下地層形成後、
(b)マスク形成後であり、(c) III窒化物層形成後
である。
FIG. 1 is a cross-sectional view perpendicular to the substrate surface of a III-nitride semiconductor showing a manufacturing process according to the present invention.
(B) After forming the mask and (c) after forming the III nitride layer.

【図2】Si基板とCaF2 の短冊状マスクの関係を示
す斜視図である。
FIG. 2 is a perspective view showing a relationship between a Si substrate and a strip mask of CaF 2 .

【図3】本発明に係る III窒化物の製造方法によるレー
ザダイオードの断面図である。
FIG. 3 is a cross-sectional view of a laser diode manufactured by a method for manufacturing a III nitride according to the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 下地層 2a バッファ層 2b 下地GaN層 3m マスク 4 III 窒化物層 4a コンタクト層 4b nクラッド層 4c 活性層 4d pクラッド層 4e pキャップ層 5 外部狭窄層 6a 上部電極 6b 下部電極 Reference Signs List 1 silicon substrate 2 base layer 2a buffer layer 2b base GaN layer 3m mask 4III nitride layer 4a contact layer 4b n clad layer 4c active layer 4d p clad layer 4e p cap layer 5 external constriction layer 6a upper electrode 6b lower electrode

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に、または半導体基板上のA
x Gay In1-x- y N(但し、0≦x,y、かつ0≦
x+y≦1)からなる第1の III族窒化物半導体層上
に、マスクが局所的に形成されており、さらにAlx
y In1-x-yN(但し、0≦x,y、かつ0≦x+y
≦1)からなる第2の III族窒化物半導層が積層されて
なる III族窒化物半導体において、前記マスクは酸化ケ
イ素または窒化ケイ素より表面エネルギーの低い材料か
らなることを特徴とする III族窒化物半導体。
1. A semiconductor device comprising: a semiconductor substrate;
l x Ga y In 1-x- y N ( where, 0 ≦ x, y, and 0 ≦
x + y ≦ 1), a mask is locally formed on the first group III nitride semiconductor layer, and Al x G
a y In 1-xy N (where 0 ≦ x, y and 0 ≦ x + y
.Ltoreq.1), wherein the mask is made of a material having a lower surface energy than silicon oxide or silicon nitride. Nitride semiconductor.
【請求項2】前記表面エネルギーの低い材料は、少なく
ともフッ化カルシウム(CaF2 )、フッ化バリウム
(BaF2 )またはフッ化ストロンチウム(SrF2
のいずれかのII族フッ化物であることを特徴とする請求
項1に記載の III族窒化物半導体。
2. The material having a low surface energy is at least calcium fluoride (CaF 2 ), barium fluoride (BaF 2 ) or strontium fluoride (SrF 2 ).
The group III nitride semiconductor according to claim 1, wherein the group III nitride is any one of the group II fluorides.
【請求項3】前記半導体基板は表面の面方位が(1,1,1)
であるシリコン基板であり、前記マスクはシリコン基板
の<1,1,0> 方向に平行な辺を有する短冊形状であること
を特徴とする請求項2に記載の III族窒化物半導体。
3. The semiconductor substrate has a surface orientation of (1,1,1).
3. The group III nitride semiconductor according to claim 2, wherein the mask has a strip shape having sides parallel to the <1,1,0> direction of the silicon substrate. 4.
【請求項4】半導体基板上に、または半導体基板上のA
x Gay In1-x- y N(但し、0≦x,y、かつ0≦
x+y≦1)からなる第1の III族窒化物半導体層上
に、マスクが局所的に形成されており、さらにAlx
y In1-x-yN(但し、0≦x,y、かつ0≦x+y
≦1)からなる第2の III族窒化物半導層が積層されて
なる請求項1ないし3に記載の III族窒化物半導体の製
造方法において、前記第2の III族窒化物半導層はMO
CVD、MOMBE、MBEまたは蒸着によってELO
成長されることを特徴とする III族窒化物半導体の製造
方法。
4. A semiconductor device comprising: a semiconductor substrate;
l x Ga y In 1-x- y N ( where, 0 ≦ x, y, and 0 ≦
x + y ≦ 1), a mask is locally formed on the first group III nitride semiconductor layer, and Al x G
a y In 1-xy N (where 0 ≦ x, y and 0 ≦ x + y
4. The method of manufacturing a group III nitride semiconductor according to claim 1, wherein a second group III nitride semiconductor layer satisfying ≦ 1) is laminated. 5. MO
ELO by CVD, MOMBE, MBE or evaporation
A method for producing a group III nitride semiconductor, which is grown.
【請求項5】前記II族フッ化物層の成膜はII族フッ化物
をターゲットに用いてスパッタにより形成されることを
特徴とする請求項4に記載の III族窒化物半導体装置。
5. The group III nitride semiconductor device according to claim 4, wherein said group II fluoride layer is formed by sputtering using a group II fluoride as a target.
【請求項6】前記II族フッ化物層のマスクはフッ酸によ
るエッチングによって形成されることを特徴とする請求
項5に記載の III族窒化物半導体の製造方法。
6. The method according to claim 5, wherein the mask of the group II fluoride layer is formed by etching with hydrofluoric acid.
【請求項7】請求項3に記載の III族窒化物半導体を用
いた III族窒化物半導体装置において、前記 III族窒化
物半導体装置はレーザーダイオードであることを特徴と
する III族窒化物半導体装置。
7. A group III nitride semiconductor device using a group III nitride semiconductor according to claim 3, wherein said group III nitride semiconductor device is a laser diode. .
JP34524498A 1998-12-04 1998-12-04 Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device Withdrawn JP2000174393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34524498A JP2000174393A (en) 1998-12-04 1998-12-04 Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34524498A JP2000174393A (en) 1998-12-04 1998-12-04 Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device

Publications (1)

Publication Number Publication Date
JP2000174393A true JP2000174393A (en) 2000-06-23

Family

ID=18375287

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34524498A Withdrawn JP2000174393A (en) 1998-12-04 1998-12-04 Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device

Country Status (1)

Country Link
JP (1) JP2000174393A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002187800A (en) * 2000-10-13 2002-07-05 Ngk Insulators Ltd Group iii nitride epitaxial substrate and utilizing method thereof
US6790279B2 (en) 1999-05-10 2004-09-14 Toyoda Gosei Co., Ltd. Method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor
US6818926B2 (en) 1999-07-27 2004-11-16 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6830948B2 (en) 1999-12-24 2004-12-14 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor and group III nitride compound semiconductor device
US6844246B2 (en) 2001-03-22 2005-01-18 Toyoda Gosei Co., Ltd. Production method of III nitride compound semiconductor, and III nitride compound semiconductor element based on it
US6855620B2 (en) 2000-04-28 2005-02-15 Toyoda Gosei Co., Ltd. Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices
US6861305B2 (en) 2000-03-31 2005-03-01 Toyoda Gosei Co., Ltd. Methods for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US6860943B2 (en) 2001-10-12 2005-03-01 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor
US6881651B2 (en) 1999-05-21 2005-04-19 Toyoda Gosei Co., Ltd. Methods and devices using group III nitride compound semiconductor
US6967122B2 (en) 2000-03-14 2005-11-22 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor and method for manufacturing the same
US6979584B2 (en) 1999-12-24 2005-12-27 Toyoda Gosei Co, Ltd. Method for producing group III nitride compound semiconductor and group III nitride compound semiconductor device
US7052979B2 (en) 2001-02-14 2006-05-30 Toyoda Gosei Co., Ltd. Production method for semiconductor crystal and semiconductor luminous element
US7141444B2 (en) 2000-03-14 2006-11-28 Toyoda Gosei Co., Ltd. Production method of III nitride compound semiconductor and III nitride compound semiconductor element
JP2008543032A (en) * 2005-05-27 2008-11-27 ラティス パワー (チアンシ) コーポレイション InGaAlN light emitting device and manufacturing method thereof
US7619261B2 (en) 2000-08-07 2009-11-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
WO2012066804A1 (en) * 2010-11-19 2012-05-24 京セラ株式会社 Method for manufacturing semiconductor substrate, and light emitting element

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790279B2 (en) 1999-05-10 2004-09-14 Toyoda Gosei Co., Ltd. Method for manufacturing group III nitride compound semiconductor and a light-emitting device using group III nitride compound semiconductor
US6881651B2 (en) 1999-05-21 2005-04-19 Toyoda Gosei Co., Ltd. Methods and devices using group III nitride compound semiconductor
US6893945B2 (en) 1999-07-27 2005-05-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride group compound semiconductor
US6818926B2 (en) 1999-07-27 2004-11-16 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6835966B2 (en) 1999-07-27 2004-12-28 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US7176497B2 (en) 1999-07-27 2007-02-13 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor
US6930329B2 (en) 1999-07-27 2005-08-16 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
US6830948B2 (en) 1999-12-24 2004-12-14 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor and group III nitride compound semiconductor device
US7560725B2 (en) 1999-12-24 2009-07-14 Toyoda Gosei Co., Ltd. Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US6979584B2 (en) 1999-12-24 2005-12-27 Toyoda Gosei Co, Ltd. Method for producing group III nitride compound semiconductor and group III nitride compound semiconductor device
US7462867B2 (en) 2000-03-14 2008-12-09 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor devices and method for fabricating the same
US6967122B2 (en) 2000-03-14 2005-11-22 Toyoda Gosei Co., Ltd. Group III nitride compound semiconductor and method for manufacturing the same
US7141444B2 (en) 2000-03-14 2006-11-28 Toyoda Gosei Co., Ltd. Production method of III nitride compound semiconductor and III nitride compound semiconductor element
US7491984B2 (en) 2000-03-31 2009-02-17 Toyoda Gosei Co., Ltd. Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US6861305B2 (en) 2000-03-31 2005-03-01 Toyoda Gosei Co., Ltd. Methods for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US6855620B2 (en) 2000-04-28 2005-02-15 Toyoda Gosei Co., Ltd. Method for fabricating Group III nitride compound semiconductor substrates and semiconductor devices
US7619261B2 (en) 2000-08-07 2009-11-17 Toyoda Gosei Co., Ltd. Method for manufacturing gallium nitride compound semiconductor
JP2002187800A (en) * 2000-10-13 2002-07-05 Ngk Insulators Ltd Group iii nitride epitaxial substrate and utilizing method thereof
US7052979B2 (en) 2001-02-14 2006-05-30 Toyoda Gosei Co., Ltd. Production method for semiconductor crystal and semiconductor luminous element
US6844246B2 (en) 2001-03-22 2005-01-18 Toyoda Gosei Co., Ltd. Production method of III nitride compound semiconductor, and III nitride compound semiconductor element based on it
US6860943B2 (en) 2001-10-12 2005-03-01 Toyoda Gosei Co., Ltd. Method for producing group III nitride compound semiconductor
JP2008543032A (en) * 2005-05-27 2008-11-27 ラティス パワー (チアンシ) コーポレイション InGaAlN light emitting device and manufacturing method thereof
JP2012212929A (en) * 2005-05-27 2012-11-01 Lattice Power (Jiangxi) Corp InGaAlN LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME
WO2012066804A1 (en) * 2010-11-19 2012-05-24 京セラ株式会社 Method for manufacturing semiconductor substrate, and light emitting element
JP5591349B2 (en) * 2010-11-19 2014-09-17 京セラ株式会社 Manufacturing method of semiconductor substrate

Similar Documents

Publication Publication Date Title
KR100917260B1 (en) Crystal film, crystal substrate and semiconductor device
US6576533B2 (en) Method of forming semiconductor thin film of group III nitride compound semiconductor.
US6606335B1 (en) Semiconductor laser, semiconductor device, and their manufacture methods
US6566231B2 (en) Method of manufacturing high performance semiconductor device with reduced lattice defects in the active region
US6593159B1 (en) Semiconductor substrate, semiconductor device and method of manufacturing the same
JP4371202B2 (en) Nitride semiconductor manufacturing method, semiconductor wafer, and semiconductor device
JP4903189B2 (en) Method of growing semipolar nitride single crystal thin film and method of manufacturing nitride semiconductor light emitting device using the same
JP4451846B2 (en) Method of manufacturing nitride semiconductor device
WO2003072856A1 (en) Process for producing group iii nitride compound semiconductor
JP3712770B2 (en) Method for manufacturing group 3 nitride semiconductor and semiconductor device
JP2003229645A (en) Quantum well structure, semiconductor element employing it and its fabricating method
JP2000174393A (en) Group iii nitride semiconductor, its manufacture and group iii nitride semiconductor device
JPH11135770A (en) Iii-v compd. semiconductor, manufacture thereof and semiconductor element
KR100878512B1 (en) Method of manufacturing semiconductor substrate having GaN layer
JP4883931B2 (en) Manufacturing method of semiconductor laminated substrate
JPH11274082A (en) Group iii nitride semiconductor and fabrication thereof, and group iii nitride semiconductor device
JP2002353134A (en) Nitride based semiconductor element and method for forming nitride based semiconductor
JP3753747B2 (en) Gallium nitride compound semiconductor laser diode
JPH11130597A (en) Control of dislocation line in transmission direction and its use
JP4530234B2 (en) Semiconductor light emitting device
JPH11145515A (en) Gan semiconductor light-emitting element and manufacture thereof
JP4255168B2 (en) Nitride semiconductor manufacturing method and light emitting device
JP3792041B2 (en) Semiconductor device and manufacturing method thereof
JP3562478B2 (en) Method for growing nitride semiconductor and device using the same
JP4104234B2 (en) Semiconductor light emitting device and manufacturing method thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060209

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060214

A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20060417