JP2000174197A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2000174197A
JP2000174197A JP34189598A JP34189598A JP2000174197A JP 2000174197 A JP2000174197 A JP 2000174197A JP 34189598 A JP34189598 A JP 34189598A JP 34189598 A JP34189598 A JP 34189598A JP 2000174197 A JP2000174197 A JP 2000174197A
Authority
JP
Japan
Prior art keywords
heat sink
substrate
conductive circuit
plate
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34189598A
Other languages
Japanese (ja)
Inventor
Hitoshi Sasaki
仁志 佐々木
Yoshinari Tsukada
能成 塚田
Katsuhiko Iwazawa
克彦 岩澤
Takahiko Hamada
貴彦 濱田
Takeshi Ueda
武司 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honda Motor Co Ltd
Original Assignee
Honda Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honda Motor Co Ltd filed Critical Honda Motor Co Ltd
Priority to JP34189598A priority Critical patent/JP2000174197A/en
Publication of JP2000174197A publication Critical patent/JP2000174197A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To absorb a mechanical stress according to a difference of thermal expansion coefficients or a vibration and to effectively maintain an electric connection of an electrode plate to a conductive circuit, by sandwiching a board relatively sliding in a range limited to the plate and a heat sink between the plate and the sink. SOLUTION: A frame 12 made of an insulating material such as a synthetic resin or the like having an opening 13 is clamped on a heat sink 7. The opening 13 is formed in a rectangular shape by disposing four control pins 11 arranged in one row at both ends in the longitudinal direction. A length of the opening of a direction perpendicular to an arraying direction of the pins 11 is formed slightly longer than a length in the longitudinal direction of boards 5. The boards 5 are disposed in the frame 12 slidably to the sink 7 in a range limited by the pins 11 and the opening 13. Thus, an electric connection of the plate to a conductive circuit can be effectively maintained, and a mechanical stress caused by a difference of thermal expansion coefficients of the plate, the board and the sink or a vibration can be absorbed.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップが搭
載される基板がヒートシンク上に載せられる半導体装置
に関する。
The present invention relates to a semiconductor device in which a substrate on which a semiconductor chip is mounted is mounted on a heat sink.

【0002】[0002]

【従来の技術】半導体チップを備える基板がヒートシン
ク上に搭載される構造は、たとえば特開平5−9048
7号公報等により既に知られているが、従来のかかる半
導体装置では、基板がヒートシンクに固定されるととも
に、基板上の導電回路に接続される電極板もヒートシン
クに固定されている。
2. Description of the Related Art A structure in which a substrate having a semiconductor chip is mounted on a heat sink is disclosed in, for example, Japanese Patent Application Laid-Open No. 5-9048.
As is already known from Japanese Patent Application Publication No. 7-107, etc., in such a conventional semiconductor device, a substrate is fixed to a heat sink, and an electrode plate connected to a conductive circuit on the substrate is also fixed to the heat sink.

【0003】[0003]

【発明が解決しようとする課題】ところが、上記従来の
ように、ヒートシンクに対する基板および電極板の位置
が一定に定まると、電極板、基板およびヒートシンクの
熱膨張率の差に伴なう機械的ストレスや、振動による機
械的ストレスが生じることになり、電極板および導電回
路間の良好な導通状態が得られなくなる可能性がある。
However, when the positions of the substrate and the electrode plate with respect to the heat sink are fixed, as in the conventional case, mechanical stress caused by the difference in the coefficient of thermal expansion between the electrode plate, the substrate and the heat sink. Also, mechanical stress due to vibration may occur, and a good conduction state between the electrode plate and the conductive circuit may not be obtained.

【0004】本発明は、かかる事情に鑑みてなされたも
のであり、導電回路および電極板間の良好な導通状態を
維持しつつ良好な熱伝導を得るようにした半導体装置を
提供することを目的とする。
The present invention has been made in view of such circumstances, and has as its object to provide a semiconductor device capable of obtaining good heat conduction while maintaining good conduction between a conductive circuit and an electrode plate. And

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、導電回路が表面に形成される基板と、前
記導電回路に電気的に接続されて前記基板上に固定され
る半導体チップと、前記基板が搭載されるヒートシンク
とを備える半導体装置において、前記導電回路に接触す
る電極板が前記ヒートシンクに固定され、電極板および
ヒートシンクに対して制限された範囲で基板が相対摺動
することを可能として、前記基板が電極板およびヒート
シンク間に挟持されることを特徴とする。
In order to achieve the above object, the present invention provides a substrate having a conductive circuit formed on a surface thereof, and a semiconductor electrically connected to the conductive circuit and fixed on the substrate. In a semiconductor device including a chip and a heat sink on which the substrate is mounted, an electrode plate in contact with the conductive circuit is fixed to the heat sink, and the substrate relatively slides in a limited range with respect to the electrode plate and the heat sink. Preferably, the substrate is sandwiched between an electrode plate and a heat sink.

【0006】このような構成によれば、基板の導電回路
に電極板を接触させた状態で、電極板およびヒートシン
ク間に挟まれた基板が制限された範囲で移動し得るの
で、電極板、基板およびヒートシンクの熱膨張率の差に
伴なう機械的ストレスや、振動による機械的ストレスを
吸収しつつ、導電回路への電極板の電気的な接続を確実
に維持することができる。しかも電極板および導電回路
の相互接触部は、電極板および基板の相対摺動に伴うセ
ルフクリーニング作用により清浄化されることになり、
電極板の導電回路への導通状態を良好に維持するととも
に良好な熱伝導を得ることができる。
According to such a structure, the substrate sandwiched between the electrode plate and the heat sink can move within a limited range in a state where the electrode plate is in contact with the conductive circuit of the substrate. In addition, it is possible to reliably maintain the electrical connection of the electrode plate to the conductive circuit while absorbing the mechanical stress due to the difference in the coefficient of thermal expansion of the heat sink and the mechanical stress due to vibration. Moreover, the mutual contact portion between the electrode plate and the conductive circuit is cleaned by a self-cleaning action accompanying the relative sliding of the electrode plate and the substrate.
Good conduction of the electrode plate to the conductive circuit can be maintained, and good heat conduction can be obtained.

【0007】[0007]

【発明の実施の形態】以下、本発明の実施の形態を、添
付図面に示した本発明の実施例に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described based on embodiments of the present invention shown in the accompanying drawings.

【0008】図1〜図3は本発明の一実施例を示すもの
であり、図1は半導体装置の縦断面図であって図3の1
−1線断面図、図2は半導体装置の分解斜視図、図3は
図1の3矢視平面図である。
FIGS. 1 to 3 show one embodiment of the present invention. FIG. 1 is a longitudinal sectional view of a semiconductor device, and FIG.
2 is an exploded perspective view of the semiconductor device, and FIG. 3 is a plan view of FIG.

【0009】先ず図1において、この半導体装置は、三
相のモータ用のパワーモジュールとして構成されるもの
であり、前記モータにおけるU,V,Wの各相に個別に
対応した窒化アルミニウム製の3つの基板5…と、各基
板5…上にたとえば6個ずつ固定される半導体チップ6
…と、各基板5…が共通に搭載されるアルミニウム合金
製のヒートシンク7とを備える。
First, in FIG. 1, this semiconductor device is configured as a power module for a three-phase motor, and is made of aluminum nitride that corresponds to each of U, V, and W phases in the motor. And five semiconductor chips 6 fixed on each of the substrates 5.
, And a heat sink 7 made of an aluminum alloy on which the substrates 5 are mounted in common.

【0010】図2および図3を併せて参照して、窒化ア
ルミニウムによって2〜5mmの厚みを有して長方形状
に形成される基板5の表面には、銅板のメタライズ接合
によりパターン化された導電回路8が形成されており、
該導電回路8の所定位置に各半導体チップ6…が高融点
の半田により接合される。しかも各半導体チップ6…お
よび導電回路8の電気的接続を果すべく、アルミワイヤ
等の導電線9…の両端が各半導体チップ6…および導電
回路8にボンディング接合される。
Referring to FIG. 2 and FIG. 3 together, a surface of a substrate 5 formed in a rectangular shape having a thickness of 2 to 5 mm by aluminum nitride is provided with a conductive pattern patterned by metallization bonding of a copper plate. A circuit 8 is formed,
Each semiconductor chip 6 is joined to a predetermined position of the conductive circuit 8 by solder having a high melting point. In addition, both ends of conductive wires 9 such as aluminum wires are bonded to the respective semiconductor chips 6 and the conductive circuits 8 in order to achieve electrical connection between the semiconductor chips 6 and the conductive circuits 8.

【0011】各基板5…の裏面は、伝熱グリース10…
を介してヒートシンク7の上面に当接される。ヒートシ
ンク7の上面には、各基板5…の幅よりもわずかに大き
な間隔をあけた4つの規制ピン11…が1列に並んで植
設されており、各基板5…は、各規制ピン11…相互間
で、伝熱グリース10…を介してヒートシンク7の上面
に当接するように配置される。
The back surface of each substrate 5 is provided with a heat transfer grease 10.
Through the upper surface of the heat sink 7. On the upper surface of the heat sink 7, four regulating pins 11 spaced slightly larger than the width of each board 5 are planted in a line, and each board 5 is attached to each regulating pin 11. .. Are arranged so as to abut each other on the upper surface of the heat sink 7 via the heat transfer grease 10.

【0012】ヒートシンク7上には、開口部13を有し
て合成樹脂等の絶縁材料から成る枠体12が締結される
ものであり、前記開口部13は、一列に配列された4つ
の前記規制ピン11…を長手方向両端に配置するように
して長方形状に形成されており、各規制ピン11…の配
列方向と直交する方向の開口部13の長さは、各基板5
…の長手方向長さよりもわずかに長く形成される。すな
わち各基板5…は、各規制ピン11…と、開口部13と
で制限される範囲でヒートシンク7に対して摺動するこ
とを可能として枠体12内に配置される。
A frame 12 made of an insulating material such as a synthetic resin is fastened to the heat sink 7 with an opening 13, and the opening 13 is provided with four regulating members arranged in a line. The pins 11 are formed in a rectangular shape so as to be arranged at both ends in the longitudinal direction, and the length of the opening 13 in the direction orthogonal to the arrangement direction of the restriction pins 11 is
Are formed slightly longer than the length in the longitudinal direction. That is, each of the substrates 5 is arranged in the frame 12 so as to be able to slide with respect to the heat sink 7 within a range limited by each of the restriction pins 11 and the opening 13.

【0013】3つの基板5…のうち両側の基板5…の導
電回路8…において電源のプラス側に接続される部分
と、真ん中の基板5の導電回路8において電源のプラス
側に接続される部分とには、隣接する基板5,5間にわ
たる長方形状の電極板14,14が当接され、両側の基
板5…の導電回路8…において電源のプラス側に接続さ
れる部分に一端が当接される長方形状の電極板15,1
5の他端は両側の基板5,5から側方に突設される。ま
た3つの基板5…のうち両側の基板5…の導電回路8…
において電源のマイナス側に接続される部分と、真ん中
の基板5の導電回路8において電源のマイナス側に接続
される部分とには、隣接する基板5,5間にわたって前
記電極板14,14と平行に配置される長方形状の電極
板16,16が当接され、両側の基板5…の導電回路8
…において電源のマイナス側に接続される部分に一端が
当接されて前記電極板15,15と平行に配置される長
方形状の電極板17,17の他端は両側の基板5,5か
ら側方に突設される。さらに各基板5…の導電回路8…
の出力部分に一端を個別に当接せしめる3つの電極板1
8…の他端が、各基板5…の長手方向一端から外方に突
出される。しかも各基板5…からの電極板15…,17
…,18…の突出端部には、ピン状の端子を嵌合、接続
するための円筒状の接続部15a…,17a…,18a
…が設けられる。
A portion connected to the positive side of the power supply in the conductive circuits 8 of the substrates 5 on both sides of the three substrates 5, and a portion connected to the positive side of the power supply in the conductive circuit 8 of the middle substrate 5 , The rectangular electrode plates 14, 14 extending between the adjacent substrates 5, 5 are in contact with each other, and one end thereof is in contact with a portion of the conductive circuits 8 of both substrates 5, connected to the positive side of the power supply. Rectangular electrode plates 15, 1
The other end of 5 protrudes laterally from both substrates 5, 5. The conductive circuits 8 of the substrates 5 on both sides of the three substrates 5.
The portion connected to the negative side of the power supply and the portion connected to the negative side of the power supply in the conductive circuit 8 of the middle substrate 5 are parallel to the electrode plates 14 and 14 between the adjacent substrates 5 and 5. Are in contact with each other, and the conductive circuits 8 of the substrates 5 on both sides are contacted.
, One end of which is in contact with a portion connected to the negative side of the power source, and the other ends of the rectangular electrode plates 17, 17 arranged in parallel with the electrode plates 15, 15 are on the opposite sides from the substrates 5, 5 on both sides. It is protruded toward. Further, the conductive circuits 8 of each substrate 5.
Electrode plates 1 whose one end is individually brought into contact with the output part of
8 protrude outward from one longitudinal end of each substrate 5. Moreover, the electrode plates 15 ..., 17 from each substrate 5 ...
, 18 ... cylindrical connecting portions 15a, 17a ..., 18a for fitting and connecting pin-shaped terminals.
... are provided.

【0014】上記各電極板14…,15…,16…,1
7…,18…は、絶縁紙等の絶縁材料で長方形状に形成
される絶縁シート19の裏面に接着されており、電極板
15…,17…,18…の他端は、該絶縁シート19か
ら外方に突出される。
Each of the above-mentioned electrode plates 14, 15, 16, 1.
, 18 ... are adhered to the back surface of an insulating sheet 19 formed in a rectangular shape with an insulating material such as insulating paper, and the other ends of the electrode plates 15 ..., 17 ..., 18 ... Projected outward from the

【0015】一方、枠体12には、各規制ピン11…の
配列方向に沿う方向での開口部13の両端に連なる段部
20,20が、電極板15…,17…の一部を載せると
ともにそれらの電極板15…,17…の絶縁シート19
からの突出部を嵌合せしめる形状で形成されるととも
に、各規制ピン11…の配列方向に直交する方向での開
口部13の一側に連なる3つの段部21…が、電極板1
8…の絶縁シート19からの突出部を嵌合、載置せしめ
る形状で形成される。
On the other hand, on the frame 12, steps 20, 20, which are continuous with both ends of the opening 13 in the direction along the arrangement direction of the respective restriction pins 11, put a part of the electrode plates 15,. And the insulating sheet 19 of the electrode plates 15.
Are formed in such a shape that the projecting portions from them are fitted together, and three step portions 21 connected to one side of the opening 13 in a direction orthogonal to the arrangement direction of the respective restriction pins 11 are formed on the electrode plate 1.
8 are formed in such a shape that the protruding portions from the insulating sheet 19 are fitted and placed.

【0016】絶縁シート19には、各基板5…の大部分
を臨ませる3つの窓22…が設けられており、各窓22
…を相互間に挟むようにして4つの金属製押さえ板23
…が絶縁シート19の表面に接着される。これらの押さ
え板23…には、各規制ピン11…を相互間に挟む位置
に一対ずつの挿通孔24,25…が設けられており、一
方の挿通孔24…に挿通されて絶縁シート19を貫通す
るボルト26…が、電極板15,17間および電極板1
4,16間でヒートシンク7に螺合され、また他方の挿
通孔25…に挿通されて絶縁シート19を貫通するボル
ト27…が、前記規制ピン11…を前記ボルト26…と
の間に挟む位置でヒートシンク7に螺合される。
The insulating sheet 19 is provided with three windows 22 through which most of the substrates 5 are exposed.
Are sandwiched between four metal holding plates 23
Are adhered to the surface of the insulating sheet 19. These holding plates 23 are provided with a pair of insertion holes 24, 25 at positions sandwiching each of the restriction pins 11 and are inserted through one of the insertion holes 24 so that the insulating sheet 19 is inserted. The bolts 26 penetrating between the electrode plates 15 and 17 and the electrode plate 1
The bolts 27 which are screwed to the heat sink 7 between the holes 4 and 16 and which penetrate through the insulating sheet 19 by being inserted into the other insertion holes 25 and sandwiching the regulating pins 11 with the bolts 26. To the heat sink 7.

【0017】また絶縁シート19の裏面には、図3にお
いて各ボルト27…の左側に配置される金属製のスペー
サ28…が接着されており、各スペーサ28…の厚み
は、各電極板14…,15…,16…,17…,18…
と同一に設定される。而して図3において最も右側のボ
ルト28を除く3つのボルト28…は、電極板18…お
よびスペーサ28…間に配置されることになり、図3に
おいて最も左側のスペーサ28は枠体12の段部20に
当接するが、他のスペーサ28…は、各基板5…の表面
の導電回路8…に、電気的な接続機能を果すことのない
ようにして当接される。
On the back surface of the insulating sheet 19, metal spacers 28 arranged on the left side of the bolts 27 in FIG. 3 are adhered. , 15 ..., 16 ..., 17 ..., 18 ...
Is set the same as The three bolts 28 except for the rightmost bolt 28 in FIG. 3 are arranged between the electrode plate 18 and the spacers 28, and the leftmost spacer 28 in FIG. The other spacers 28 abut on the step portions 20, but are in contact with the conductive circuits 8 on the surface of each substrate 5 so as not to perform an electrical connection function.

【0018】このようにして各基板5…の表面の導電回
路8…に接触する電極板14…,15…,16…,17
…,18…がヒートシンク7に固定されることになり、
各電極板14…,15…,16…,17…,18…およ
びヒートシンク7間に各基板5…が挟持され、各基板5
…は、各規制ピン11…および枠体12の開口部13に
よって制限される範囲で各電極板14…,15…,16
…,17…,18…およびヒートシンク7に対して相対
摺動することが可能となる。
In this way, the electrode plates 14, 15, 16, 17 contacting the conductive circuits 8 on the surface of each substrate 5.
..., 18 ... are fixed to the heat sink 7.
Each substrate 5 is sandwiched between each of the electrode plates 14, 15, 16, 16, 17, 18, and the heat sink 7.
, Are electrode plates 14,..., 15,..., 16 in a range limited by each regulating pin 11 and the opening 13 of the frame 12.
, 17 ..., 18 ... and the heat sink 7 can be slid relative to each other.

【0019】次にこの実施例の作用について説明する
と、銅板による導電回路8…が表面に形成される窒化ア
ルミニウム製の基板5…の裏面が、伝熱グリース10…
を介してヒートシンク7に当接されるので、基板および
ヒートシンク間に銅板、半田層および銅ベースが介在し
ていた従来のものと比べると、基板5…およびヒートシ
ンク7間の熱抵抗が小さくなる。したがって基板5…上
に搭載される半導体チップ6…が、本実施例のように電
力制御用のものであったとしても、基板5…からヒート
シンク7への充分な放熱性を得ることができる。しかも
基板5…の裏面の銅板と、銅ベースとを比較的大きな面
積にわたる半田接合により接合するものに比べると、広
い面積にわたる半田接合が不要であるので、熟練した技
術は不要であり、組付作業工数も低減されることにな
る。
Next, the operation of this embodiment will be described. The back surface of the aluminum nitride substrate 5 on which the conductive circuit 8 formed of a copper plate is formed is connected to the heat transfer grease 10.
, And the heat resistance between the substrate 5 and the heat sink 7 is smaller than that of the conventional one in which a copper plate, a solder layer and a copper base are interposed between the substrate and the heat sink. Therefore, even if the semiconductor chips 6 mounted on the substrates 5 are for power control as in this embodiment, sufficient heat radiation from the substrates 5 to the heat sink 7 can be obtained. Moreover, compared to a method in which the copper plate on the back surface of the substrate 5 and the copper base are joined by soldering over a relatively large area, soldering over a large area is unnecessary, so that a skilled technique is unnecessary, and assembly is not required. The number of work steps is also reduced.

【0020】ところで、ヒートシンク上に設けられる銅
ベース上に窒化アルミニウム製の基板が半田接合されて
いた従来のものでは、基板の厚みが0.2〜0.3mm
程度であったのに対し、基板5…の厚みは2〜5mmに
設定されるものであり、このように基板5…を厚板化す
ることにより基板5…の熱容量を高めることができる。
これにより、ヒートマスの機能を果たしていた銅ベース
を廃止して、伝熱グリース10…を介して基板5…をヒ
ートシンク7上に取付けても、半導体チップ6…で発生
した熱を、銅ベースを用いた従来のものと同等に放散す
ることができるのである。
Meanwhile, in a conventional device in which an aluminum nitride substrate is soldered on a copper base provided on a heat sink, the thickness of the substrate is 0.2 to 0.3 mm.
However, the thickness of the substrates 5 is set to 2 to 5 mm, and the heat capacity of the substrates 5 can be increased by increasing the thickness of the substrates 5 in this manner.
As a result, even if the copper base serving as a heat mass is abolished and the substrate 5 is mounted on the heat sink 7 via the heat transfer grease 10, the heat generated in the semiconductor chips 6 can be used by the copper base. It can be dissipated as well as the conventional one.

【0021】また基板5…の表面の導電回路8…に接触
する電極板14…,15…,16…,17…,18…が
ヒートシンク7に固定され、電極板14…,15…,1
6…,17…,18…およびヒートシンク7に対して制
限された範囲で基板5…が相対摺動することを可能とし
て、基板5…が電極板14…,15…,16…,17
…,18…およびヒートシンク7間に挟持されるので、
電極板14…,15…,16…,17…,18…、基板
5…およびヒートシンク7の熱膨張率の差に伴なう機械
的ストレスや、振動による機械的ストレスを吸収しつ
つ、導電回路8…への電極板14…,15…,16…,
17…,18…の電気的な接続を確実に維持することが
できる。
The electrode plates 14, 15, 16, 17, 18, 18 which are in contact with the conductive circuits 8 on the surface of the substrate 5 are fixed to the heat sink 7, and the electrode plates 14, 15, 1,
, 17 ..., 18 and the heat sink 7 can be slid relative to each other within a limited range, so that the substrates 5 ...
..., 18 ... and the heat sink 7,
The conductive circuit absorbs the mechanical stress caused by the difference in the coefficient of thermal expansion between the electrode plates 14, 15, 16, 17, 18, the substrate 5, and the heat sink 7 and the mechanical stress due to vibration. , Electrode plates 14 ..., 15 ..., 16 ...,
.., 18... Can be reliably maintained.

【0022】しかも電極板14…,15…,16…,1
7…,18…および導電回路8…の相互接触部は、電極
板14…,15…,16…,17…,18…および基板
5…の相対摺動に伴うセルフクリーニング作用により清
浄化されるので、電極板14…,15…,16…,17
…,18…の導電回路8…への導通状態を良好に維持し
つつ良好な熱伝導を得ることができる。
Moreover, the electrode plates 14, 15, 16, 1
, 18 and the conductive circuit 8 are cleaned by a self-cleaning action accompanying the relative sliding of the electrode plates 14, 15, 16, 17, 17, 18 and the substrate 5. Therefore, the electrode plates 14, 15, 16, 17
, 18 ... good heat conduction can be obtained while maintaining good conduction to the conductive circuits 8 ...

【0023】図4は電極板14〜18の第1変形例を示
すものであり、各電極板14〜18の導電回路8への接
触部がプレス成形による略U字状の突部30として形成
されるものであってもよく、図5で示す第2変形例のよ
うに、各電極板14〜18に一体に形成される一対の突
部31,31が導電回路8に接触するようにしてもよ
く、図6で示す第3変形例のように、前記両突部31,
31の先端部に複数の山部32…が形成されるものであ
ってもよく、図7で示す第4変形例のように、導電回路
8側に屈曲するようにして各電極板14〜18の一端に
設けられる接触部33の導電回路8側の面にローレット
加工による多数の凹凸34が形成されていてもよく、さ
らに図8で示す第5変形例のように、各電極板14〜1
8に設けられている突部30の導電回路8側の面にロー
レット加工による多数の凹凸34が形成されていてもよ
い。
FIG. 4 shows a first modification of the electrode plates 14 to 18. The contact portions of the electrode plates 14 to 18 with the conductive circuit 8 are formed as substantially U-shaped projections 30 by press molding. As in the second modification shown in FIG. 5, a pair of protrusions 31 formed integrally with each of the electrode plates 14 to 18 may be in contact with the conductive circuit 8. As in a third modification shown in FIG.
A plurality of peaks 32 may be formed at the distal end of the electrode plate 31. Each of the electrode plates 14 to 18 may be bent toward the conductive circuit 8 as in a fourth modification shown in FIG. A large number of irregularities 34 may be formed by knurling on the surface on the conductive circuit 8 side of the contact portion 33 provided at one end of the contact plate 33. Further, as in a fifth modification shown in FIG.
A large number of irregularities 34 may be formed by knurling on the surface of the protrusion 30 provided on the conductive circuit 8 side of the protrusion 30.

【0024】以上、本発明の実施例を詳述したが、本発
明は上記実施例に限定されるものではなく、特許請求の
範囲に記載された本発明を逸脱することなく種々の設計
変更を行なうことが可能である。
Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various design changes can be made without departing from the present invention described in the appended claims. It is possible to do.

【0025】たとえば、上記実施例では、基板5として
窒化アルミニウム製のものが用いられたが、他の非導電
性材料によって基板が形成されるものであってもよい。
For example, in the above embodiment, the substrate 5 is made of aluminum nitride, but the substrate 5 may be formed of another non-conductive material.

【0026】[0026]

【発明の効果】以上のように本発明によれば、電極板、
基板およびヒートシンクの熱膨張率の差に伴なう機械的
ストレスや、振動による機械的ストレスを吸収して、導
電回路への電極板の電気的な接続を確実に維持すること
ができ、電極板の導電回路への導通状態を良好に維持し
つつ良好な熱伝導を得ることができる。
As described above, according to the present invention, the electrode plate,
By absorbing the mechanical stress due to the difference in the coefficient of thermal expansion between the substrate and the heat sink and the mechanical stress due to vibration, the electrical connection of the electrode plate to the conductive circuit can be reliably maintained, And good heat conduction can be obtained while maintaining good conduction to the conductive circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図1】半導体装置の縦断面図であって図3の1−1線
断面図である。
1 is a longitudinal sectional view of the semiconductor device, and is a sectional view taken along line 1-1 of FIG. 3;

【図2】半導体装置の分解斜視図である。FIG. 2 is an exploded perspective view of the semiconductor device.

【図3】図1の3矢視平面図である。FIG. 3 is a plan view as viewed in the direction of arrow 3 in FIG. 1;

【図4】電極板の第1変形例の要部側面図である。FIG. 4 is a side view of a main part of a first modification of the electrode plate.

【図5】電極板の第2変形例の要部斜視図である。FIG. 5 is a perspective view of a main part of a second modification of the electrode plate.

【図6】電極板の第3変形例の要部斜視図である。FIG. 6 is a perspective view of a main part of a third modification of the electrode plate.

【図7】電極板の第4変形例の要部側面図である。FIG. 7 is a side view of a main part of a fourth modification of the electrode plate.

【図8】電極板の第5変形例の要部側面図である。FIG. 8 is a side view of a main part of a fifth modification of the electrode plate.

【符号の説明】[Explanation of symbols]

5・・・基板 6・・・半導体チップ 7・・・ヒートシンク 8・・・導電回路 14,15,16,17,18・・・電極板 5 ... substrate 6 ... semiconductor chip 7 ... heat sink 8 ... conductive circuit 14, 15, 16, 17, 18 ... electrode plate

フロントページの続き (72)発明者 岩澤 克彦 埼玉県狭山市新狭山1丁目10番地1 ホン ダエンジニアリング株式会社内 (72)発明者 濱田 貴彦 埼玉県狭山市新狭山1丁目10番地1 ホン ダエンジニアリング株式会社内 (72)発明者 上田 武司 埼玉県狭山市新狭山1丁目10番地1 ホン ダエンジニアリング株式会社内Continued on the front page (72) Inventor Katsuhiko Iwasawa 1-10-1 Shinsayama, Sayama City, Saitama Prefecture Honda Engineering Co., Ltd. (72) Inventor Takahiko Hamada 1-10-1 Shinsayama, Sayama City, Saitama Honda Engineering Co., Ltd. Inside the company (72) Inventor Takeshi Ueda 1-10-1 Shinsayama 1 Sayama-shi, Saitama Honda Engineering Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 導電回路(8)が表面に形成される基板
(5)と、前記導電回路(8)に電気的に接続されて前
記基板(5)上に固定される半導体チップ(6)と、前
記基板(5)が搭載されるヒートシンク(7)とを備え
る半導体装置において、前記導電回路(8)に接触する
電極板(14,15,16,17,18)が前記ヒート
シンク(7)に固定され、電極板(14〜18)および
ヒートシンク(7)に対して制限された範囲で基板
(5)が相対摺動することを可能として、前記基板
(5)が電極板(14〜18)およびヒートシンク
(7)間に挟持されることを特徴とする半導体装置。
1. A substrate (5) having a conductive circuit (8) formed on a surface thereof, and a semiconductor chip (6) electrically connected to the conductive circuit (8) and fixed on the substrate (5). And a heat sink (7) on which the substrate (5) is mounted, wherein the electrode plates (14, 15, 16, 17, 18) contacting the conductive circuit (8) are provided by the heat sink (7). To allow the substrate (5) to slide relative to the electrode plates (14-18) and the heat sink (7) within a limited range. ) And a heat sink (7).
JP34189598A 1998-12-01 1998-12-01 Semiconductor device Pending JP2000174197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34189598A JP2000174197A (en) 1998-12-01 1998-12-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34189598A JP2000174197A (en) 1998-12-01 1998-12-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2000174197A true JP2000174197A (en) 2000-06-23

Family

ID=18349581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34189598A Pending JP2000174197A (en) 1998-12-01 1998-12-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2000174197A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009081273A (en) * 2007-09-26 2009-04-16 Rohm Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009081273A (en) * 2007-09-26 2009-04-16 Rohm Co Ltd Semiconductor device

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