JP2000171834A - Liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the breakage in an upper layer wiring and the shorting to a lower layer wiring and to improve reliability by improving the contact characteristic with insulating films, etc., at the etching ends of the lower layer wiring, making step coverage sufficient and satisfying the adhesiveness to substrates. SOLUTION: This liquid crystal display device has the wiring 2 of a laminated structure constituted by forming a first layer 2A consisting a first metallic layer on an insulative substrate 1 and forming a second layer 2B consisting of a second metallic layer different from the first metallic layer on the first layer. The side end face of the first layer 2A has a forward taper shape of <=60 deg. in taper angle and the side end face of the second layer 2B is either of a shape perpendicular to the substrate surface or a reversed taper shape. the film thickness of the second layer 2B is set at half the film thickness of the first layer or below.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having an improved yield by eliminating disconnection of a wiring laminated portion in an active matrix type liquid crystal display device such as a thin film transistor (TFT) system. It relates to the manufacturing method.

[0002]

2. Description of the Related Art Liquid crystal displays are widely used as devices for displaying various images including still images and moving images.

In a liquid crystal display device, a liquid crystal layer is sandwiched between two substrates, at least one of which is made of transparent glass or the like, and a voltage is selectively applied to various electrodes for pixel formation formed on the substrate. Is applied to turn on and off a predetermined pixel (so-called simple matrix type), and the above-mentioned various electrodes and a switching element for selecting a pixel are formed, and the switching element is selected to turn on and off the predetermined pixel. (So-called active matrix type using a thin film transistor (TFT) as a switching element).

In particular, the latter active matrix type liquid crystal display device has become the mainstream of the liquid crystal display device because of its contrast performance, high-speed display performance and the like.

This active matrix type liquid crystal display device generally employs a vertical electric field method in which an electric field for changing the orientation of a liquid crystal layer is applied between an electrode formed on one substrate and an electrode formed on the other substrate. However, recently, a lateral electric field method (In-Plane Switching Mo) in which the direction of the electric field applied to the liquid crystal is made substantially parallel to the substrate surface.
de: IPS mode) liquid crystal display devices have been put to practical use.

FIG. 16 is an exploded perspective view for explaining the whole structure of an example of an active matrix type liquid crystal display device to which the present invention is applied. FIG. 1 shows a liquid crystal display device according to the present invention (hereinafter, a module in which a liquid crystal display panel, a circuit board, a backlight, and other components are integrated: MDL).
This is to explain the specific structure of the above.

SHD is a shield case (also called a metal frame) made of a metal plate, WD is a display window, INS1
To 3 are insulating sheets, PCB1 to 3 are circuit boards (PCB1
Is a drain side circuit board: a video signal line driving circuit board, P
CB2 is a gate side circuit board: a scanning signal line drive circuit board,
PCB3 is an interface circuit board), JN1-3 are joiners for electrically connecting the circuit boards PCB1-3, TCP1 and TCP2 are tape carrier packages,
PNL is a liquid crystal display panel, GC is a rubber cushion, IL
S is a light shielding spacer, PRS is a prism sheet, SPS is a diffusion sheet, GLB is a light guide plate, RFS is a reflection sheet, M
CA is a lower case (mold frame) formed by integral molding, MO is an MCA opening, LP is a fluorescent tube, L
PC is a lamp cable, GB is a rubber bush supporting the fluorescent tube LP, BAT is a double-sided adhesive tape, BL is a backlight made of a fluorescent tube, a light guide plate, etc., and a liquid crystal display is formed by stacking diffusion plate members in the arrangement shown in the figure. The module MDL is assembled.

The liquid crystal display module MDL has two kinds of storage / holding members of a lower case MCA and a shield case SHD, and includes insulating sheets INS1 to INS3 and circuit boards PCB1 to PCB1.
3. A metal shield case SHD in which the liquid crystal display panel PNL is stored and fixed, and a lower case MCA in which a backlight BL including a fluorescent tube LP, a light guide plate GLB, a prism sheet PRS, and the like are stored are combined. .

An integrated circuit chip for driving each pixel of the liquid crystal display panel PNL is mounted on the drain side circuit board PCB1 and the gate side circuit board PCB2, and a video signal from an external host is received on the interface circuit board PCB3. , An integrated circuit chip for receiving a control signal such as a timing signal, and a timing converter (TCON) for processing a timing to generate a clock signal
And so on.

[0010] The clock signal generated by the timing converter is connected to the interface circuit board PCB3, the drain-side circuit board PCB1, and the gate-side drive board PCB.
2 is supplied to the integrated circuit chip via a clock signal line laid in the same.

The interface circuit board PCB3, the drain-side circuit board PCB1, and the gate-side circuit board P
CB2 is a multilayer wiring board, and the clock signal lines are interface circuit board PCB3, interface circuit board PCB3 and drain side circuit board PC
B1 and the inner wiring of the gate-side circuit board PCB2.

The liquid crystal display panel PNL is formed by laminating two substrates, a TFT substrate on which TFTs and various wirings / electrodes are formed, and a filter substrate on which a color filter is formed, and sealing a liquid crystal in a gap therebetween. , A TFT-side circuit board PCB1, a gate-side circuit board PCB2, and an interface circuit board PCB3 for driving TFTs are connected by tape carrier packages TCP1 and TCP2, and the circuit boards are connected by joiners JN1, JN2, JN3. .

FIG. 17 is a schematic diagram illustrating a wiring structure near one pixel of a TFT substrate constituting the liquid crystal display device shown in FIG. 16, wherein 1 is a substrate, 2 is a scanning signal line (a gate line,
2 ′ is an adjacent scanning signal line (adjacent gate line), 3 is a video signal line (drain wiring or drain electrode), 4 is a source wiring (source wiring or source electrode), 5 is a pixel electrode , TFT indicates a thin film transistor, and Cadd indicates an additional capacitance element.

In FIG. 1, a central portion of the substrate 1 excluding the periphery is a display region. In this display region, liquid crystal is sealed in a gap between the substrate 1 and a filter substrate.

In this display area, a scanning signal line 2 (gate line) extending in the X direction in the figure and a video signal line 3 (drain line) provided in the Y direction are formed. Also,
The scanning signal line 2 is insulated and extends in the Y direction.
A source electrode 4 is formed alongside the direction.

The area surrounded by the scanning signal line 2 and the video signal line 3 constitutes one pixel area.
That is, the display area is formed of an aggregate of a large number of pixel areas arranged in a matrix.

Each pixel region includes a thin film transistor TFT that is turned on by the supply of scanning signals from the scanning signal line 2 and the video signal line 3, and a video signal from the video signal line 3 via the turned on thin film transistor TFT. Is supplied to the pixel electrode 5. In addition to the thin film transistor TFT and the pixel electrode 5, an additional capacitance element Cadd is formed between the pixel electrode 5 and another adjacent scanning signal line 2 'different from the scanning signal line 2 for driving the thin film transistor TFT. ing.

The additional capacitance element Cadd is provided for storing the video signal in the pixel electrode 5 for a long time even when the thin film transistor TFT is turned off.

In this type of liquid crystal display device, the above-described various wirings for selecting pixels are formed on the substrate 1 using various film forming means and patterning means.

For the wiring of an active matrix type liquid crystal display device such as a thin film transistor type, a high melting point metal which causes less hillocks is used. As the wiring material, pure metal such as chrome (Cr) or molybdenum (Mo)
Can be mentioned. Further, as the alloy material, the above-mentioned alloy of Cr and Mo, or Mo and tungsten (W) is used.

In particular, among pure metals, Cr has good adhesion to the substrate and the resist, and has characteristics that when the wiring is etched, the etched end is processed perpendicular to the substrate surface.

When a wiring (lower wiring) is formed in the lowermost layer on the substrate using a material having such characteristics, an insulating film or the like formed on the lower wiring due to the vertical etching end. As a result, the so-called step coverage on the vertical wall at the etched end is deteriorated, and there is a problem in that the withstand voltage is deteriorated and another wiring (upper wiring) formed above is broken at a portion over the lower wiring. .

FIG. 18 is a partial cross-sectional view illustrating a structure around a TFT for explaining a configuration example of a liquid crystal display device according to the prior art. As in FIG. 16, reference numeral 1 denotes a TFT substrate, 1 ′ denotes a filter substrate, Denotes a scanning signal line (gate signal line), 3 denotes a video signal line (drain signal line), 4 denotes a source electrode, 5 denotes a pixel electrode, 6 denotes an insulating film, 7 denotes a semiconductor layer, 7A denotes a contact layer, and 8 denotes a protective film. , 8A are contact holes, 9 is a color filter, 10 is a black matrix, 11 is a smooth layer,
12 is a common electrode, TFT is a thin film transistor, Cadd
Denotes an additional capacitance element, and LC denotes a liquid crystal.

In FIG. 17, one substrate, a TFT,
In the TFT portion on the substrate 1, a gate signal line 2, an insulating film 6, a semiconductor layer 7, a contact layer 7A, a drain signal line 3, a source signal line 4, a protective film 8, a pixel electrode 5, and the like are formed and etched. Are stacked in a multilayer structure by patterning with the additional gate signal line 2 ′,
The insulating film 6, the protective film 8, and the pixel electrode 5 are similarly laminated.

As described above, the gate signal line 2 formed in the lowermost layer of the substrate 1 is made of pure Cr or an alloy material of Cr and Mo, and its end (side end surface) is brought into contact with the surface of the substrate 1 by the etching process. It is machined vertically. For this reason, the insulating film 6 formed thereon has a portion where the step coverage is insufficient as shown in FIG.

As described above, in the conventional technique, the drain signal line 3 and the source signal line 4 are formed on the insulating film 6, and the drain signal line 3 and the source signal line 4 form the gate signal line 2. As shown in the figure, there is a problem that the insulation interval is reduced or the film thickness is insufficient at the portion where the vehicle goes over, which causes a decrease in withstand voltage, a short circuit, or a disconnection.

In the case of wiring using a pure Cr material, there is a problem that fluoride whose upper surface is exposed to an atmosphere of dry etching is generated and the contact characteristics with a film formed on the upper part are deteriorated. When Mo or an alloy material of Mo and W is used as the wiring material, there is also a problem that the adhesive strength to the base or the substrate is weak, and the film is easily peeled off due to the heat history after the film is formed.

As a solution to the problem of step coverage in the formation of this type of wiring, Japanese Patent Laid-Open No. 7-3 is disclosed.
There is a technique described in Japanese Patent No. 01822. The technology disclosed in this publication is based on a technique in which Cr and M
Two alloy layers having different component ratios of o are formed, and the etching-side end face is provided with a positive taper simply by utilizing the difference in etching rate between the lower layer and the upper layer.

In order to solve the above-mentioned problem of step coverage, the present applicant has replaced the use of an end film of pure Cr or a Cr alloy for the wiring of the gate signal line and the drain / source signal line. And pure Cr in the lower layer
And a stacked wiring using a CrMo alloy as an upper layer.

In this laminated wiring, the upper Cr-Mo alloy layer has a low contact resistance with ITO (indium tin oxide) as a pixel electrode, and the lower pure Cr has an insulating substrate and a semiconductor (a-Si) substrate. To achieve good adhesion to Further, the Cr-Mo alloy has a lower stress than pure Cr, and has a higher Cr-M
The laminated wiring of the o-alloy layer and the pure Cr has a low stress and can reduce the disconnection caused by the film stress.

With respect to workability, the etching-side end face can be formed into a forward tapered shape by utilizing the corrosion potential difference between pure Cr and Cr-Mo alloy, that is, the battery reaction.

In the battery reaction, when ceric ammonium nitrate was used as an etching chemical (etchant), Cr-50Mo (Cr-M containing 50 wt% Mo) was used.
o alloy, and Cr- containing 30 wt% of Mo.
Mo alloys are expressed as Cr-30Mo) and pure Cr have a corrosion potential of +1080 mV and +110 mV, respectively.
0 mV, and pure Cr is higher by 20 mV,
-When the Mo alloy is formed into a laminated film in which pure Cr is arranged in the lower layer, the etching rate of the upper Cr-Mo alloy layer becomes faster than that of the pure Cr layer. The end face is processed into a tapered shape.

[0033]

In the prior art described above, when a laminated film in which the upper layer is made of a Cr--Mo alloy layer and the lower layer is made of pure Cr is etched, the etching-side end face of the upper layer has a vertical or reverse tapered shape. If the thickness ratio between the upper layer and the lower layer (upper layer thickness / lower layer thickness) is large, the step coverage of the insulating film formed on the upper layer to the etching-side end surface of the upper layer film is deteriorated, so that the thickness ratio is reduced. (0.5 or less, preferably 0.3 or less). However, when the thickness ratio is reduced, the taper angle of the etching-side end face of the stacked film increases, and there is a problem that the step coverage of an insulating film or the like formed on the stacked film deteriorates.

With respect to the above problem, the corrosion potential of the Cr—Mo alloy layer is reduced by setting the Mo content of the upper Cr—Mo alloy layer to be large, and the battery reaction with pure Cr proceeds. By reducing the thickness ratio between the upper layer and the lower layer, a favorable tapered shape on the etching-side end face can be improved. However, when the Mo content of the Cr—Mo alloy layer is increased, the adhesion to the resist serving as an etching mask is deteriorated, and this causes defects such as disconnection due to resist peeling.

An object of the present invention is to solve the above-mentioned problems of the prior art, to provide good contact characteristics between a lower wiring and an upper conductor film, and to provide sufficient step coverage of an upper film such as an insulating film.
Another object of the present invention is to provide a liquid crystal display device which satisfies the adhesiveness to a substrate, prevents disconnection of an upper layer wiring, and prevents occurrence of a short circuit with a lower layer wiring to improve reliability, and a method of manufacturing the same.

[0036]

In order to achieve the above object, the present invention utilizes a difference in corrosion rate due to a corrosion potential difference between dissimilar metals, and employs the following means.

(1) A first layer made of a first metal layer and a second layer made of a second metal layer different from the first metal layer are formed on the first layer on an insulating substrate. Wherein the side end surface of the first layer has a forward taper shape with a taper angle of 60 ° or less, and the side end surface of the second layer has a shape perpendicular to the substrate surface or an inverse taper shape. And the thickness of the second layer is not more than half the thickness of the first layer.

(2) One of which includes a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of a pixel. In a liquid crystal display device comprising a substrate, another substrate provided with at least a color filter and bonded to the one substrate with a small gap, and a liquid crystal filled in a gap between the one substrate and the other substrate, at least the scanning The signal line wiring includes a first layer formed of a pure chrome layer formed on the one substrate side, and a second layer formed of an alloy layer containing chromium and molybdenum as main components formed on the first layer. Wherein the side end face of the first layer has a forward tapered shape with a taper angle of 60 ° or less, and the side end face of the second layer has a shape perpendicular to the substrate surface or an inverted tapered shape. And before The thickness of the second layer was less than one-half of the thickness of the first layer.

(3) One of which includes a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of pixels. A liquid crystal display device comprising a substrate, at least a color filter, and the other substrate bonded to the one substrate with a minute gap, and a liquid crystal sealed in a gap between the one substrate and the other substrate; Having an underlayer consisting of a thin layer of insulating material on the substrate of
The wiring of the scanning signal line is made of an alloy layer containing chromium and molybdenum as main components, and a pure chrome layer is interposed between the alloy layer and the base layer, and a side end face of the first layer has a taper angle. A forward tapered shape of 60 ° or less;
The side end surface of the layer is either a shape perpendicular to the substrate surface or an inverted taper shape, and the thickness of the second layer is set to not more than half of the thickness of the first layer.

(4) A plurality of wirings including a gate line and a drain line, a video signal line, and a pixel electrode, and an active element connected to the gate line, the drain line and the video signal line to control on / off of a pixel. A liquid crystal display device in which a liquid crystal is sealed in the gap between the one substrate and the other substrate, and the other substrate provided with at least a color filter and bonded to the one substrate with a minute gap. A first layer made of a pure chrome layer formed on the one substrate side, wherein the first layer has a base layer made of a thin film layer of an insulating material on at least one of the substrates; It is a laminated structure of the formed chromium and a second layer composed of an alloy layer containing molybdenum as a main component, wherein the drain line has a single layer structure composed of an alloy layer containing chromium and molybdenum as a main component. A side end surface of the first layer has a forward taper shape having a taper angle of 60 ° or less, and a side end surface of the second layer has a shape perpendicular to a substrate surface or an inverted taper shape; The thickness of the two layers was set to not more than half the thickness of the first layer.

(5) A plurality of wirings including a gate line and a drain line, a video signal line, and a pixel electrode, and an active element connected to the gate line, the drain line, and the video signal line to control on / off of a pixel. A liquid crystal display device in which a liquid crystal is sealed in the gap between the one substrate and the other substrate, and the other substrate provided with at least a color filter and bonded to the one substrate with a minute gap. A first layer made of a pure chrome layer having a base layer made of a thin film of insulating material on at least one of the substrates, wherein the gate line and the drain line are formed on the one substrate side; A stacked structure of a chromium formed on the layer and a second layer made of an alloy layer containing molybdenum as a main component, wherein a side end face of the first layer has a forward tapered shape with a taper angle of 60 ° or less; Serial side end surface of the second layer is either vertical shape or inversely tapered shape, on the substrate surface, and the film thickness of the second layer not more than one-half of the thickness of the first layer.

(6) In the above (4) or (5),
A plurality of wirings including a gate line and a drain line, a video signal line, a pixel electrode, and a plurality of wirings including a base layer formed of a thin film layer of an insulating material on at least the one substrate; An active element was connected to the drain line and the video signal line to control on / off of the pixel.

(7) In the above (2) to (6), the gate line has a two-layer structure, and the pixel electrode is formed of an indium-tin oxide film. The additional capacitance element was formed with the insulating layer formed on the substrate.

(8) One of which includes a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of a pixel. A method for manufacturing a liquid crystal display device, comprising: a substrate, and at least a color filter, and the other substrate bonded to the one substrate with a small gap, and a liquid crystal sealed in the gap between the one substrate and the other substrate. The scanning signal line is a thin film having a laminated structure composed of a lower layer and an upper layer made of metal materials having different compositions, and this thin film is immersed in an etching chemical solution to which a corrosion potential difference adjusting liquid is added, and The corrosion potential of the upper layer is set lower than the corrosion potential of the lower layer to cause a battery reaction between the upper layer and the lower layer, and the etching rate of the upper layer having a lower corrosion potential is lower than that of the lower layer. By quickly, confers either a vertical shape or inversely tapered shape, the substrate surface on the upper side end face to form a forward taper on the lower end surface of the thin film of the laminated structure.

In each of the above structures, the upper layer is made of Cr-Mo.
An alloy layer and a lower layer are composed of a laminated film having a pure Cr layer, and an insulating film formed on the laminated film is, for example, 300 to 400 nm in thickness.
The thickness of the Cr—Mo alloy layer in which 50 wt% of Mo is mixed into Cr as a thickness that does not deteriorate the step coverage of the insulating film even if the shape of the etching side end face of the upper layer becomes vertical or reverse tapered. Is 20 nm, lower layer pure C
The film thickness of r is 180 nm, and an etchant obtained by adding ceric ammonium nitrate aqueous solution (15 wt%) to which nitric acid HNO ₃ (10 vol%) is added.

The corrosion potentials of Cr-Mo and pure Cr in this etching solution are 1100 mV and 1140 mV, and there is a 40 mV corrosion potential difference. In an aqueous solution of ceric ammonium nitrate (15 wt%) to which no nitric acid was added, the corrosion potential of each of Cr—Mo and pure Cr was 1080 mV,
At 1100 mV, the corrosion potential difference is 20 mV.

That is, the etching chemical solution to which nitric acid is added has a function of increasing the corrosion potential difference between Cr—Mo and pure Cr. By increasing the corrosion potential difference, a battery reaction between Cr-Mo and pure Cr progresses, and the taper at the etching side edge can be reduced in angle while having the same film configuration. As will be described in detail in Examples below, by setting the tapered angle of the etching side edge of the laminated film to 60 ° or less, the dielectric strength of the insulating film formed thereon becomes high, and the etching side edge is also increased. Better step coverage.

For example, three layers (Cr—Mo alloy, A
Even with a film structure of 1Cr alloy and pure Cr), by adding nitric acid to the etching solution, the corrosion potential of the Cr-Mo alloy and pure Cr can be changed. Each can be low angle.

Also, a difference is generated in the corrosion potential between the upper layer and the lower layer, and the corrosion potential of the upper layer is set lower than that of the lower layer, so that both are formed of the same etching chemical solution to which nitric acid is added as a corrosion potential difference adjusting liquid. When immersed in the lower layer, the side etching proceeds in the upper layer, and the side etching also proceeds in the upper part of the lower layer faster than in the lower part.

FIG. 5 is a schematic diagram for explaining the progress of etching by the battery reaction when the corrosion potential of the upper layer and that of the lower layer are made different.

The first layer 2A and the second layer 2 formed on the substrate 1
B, the first layer 2A, which is the lower layer of the wiring layer having a two-layer structure of two layers, is pure Cr, and the second layer, which is the upper layer, is Cr and Mo.
When the corrosion potential of the first layer 2A in the etching solution is increased (H) and the corrosion potential of the second layer 2B is decreased (L) when the alloy layer (Cr-Mo) is When immersed, a battery reaction occurs between the two. Due to this battery reaction, etching proceeds as shown by arrow E in the figure.

Under the influence of the battery reaction, the interface between the upper and lower layers has the highest etching rate, the side end surface of the entire lower layer 2A is processed into a forward tapered shape, and the side end surface of the upper layer 2B has a shape perpendicular to the surface of the substrate 1 or slightly. It is processed into a reverse taper shape.

As described above, when the etching rate of the upper layer is relatively accelerated by the battery reaction between the upper and lower layers having two different compositions, it is indispensable to set the corrosion potential of the lower layer higher than that of the upper layer. In addition, in order to process the side end face into a forward tapered shape, it is necessary that the upper layer side etching proceeds even when the lower layer is etched. Therefore,
The upper and lower layers must be made of the same alloy so that the etching proceeds with the same etching chemical, or made of a material that can be etched with the same etching chemical even if different metals are used.

If the corrosion potential difference between the two is too large, only the upper layer is rapidly etched and the etching of the lower layer does not proceed, or the taper angle becomes small even if the etching is performed. Therefore, the corrosion potential difference between the upper and lower layers is 10
It has been experimentally found that it is desirable to set the voltage between mV and 300 mV.

Among them, a desired taper angle could be obtained at 30 mV or more and 200 mV or less.

If this condition is satisfied, regardless of the etching rate of each of the upper and lower layers alone, even if the etching rate of the composition of the lower layer alone is higher than the etching rate of the upper layer, it is possible to form both of them into a laminated structure. Wiring with a desired tapered shape can be formed.

As described above, by providing the side end surface of the wiring formed on the substrate with a tapered shape, the step coverage of the insulating film formed thereon is improved, and the dielectric breakdown voltage is deteriorated and the insulating film is formed on the upper portion. A thin film (CVD) such as a CVD insulating film in a portion of another wiring (upper wiring) over the lower wiring.
This eliminates the problem that cracks are formed in the film, which causes disconnection of the drain wiring and the source wiring formed thereon.

In the above-described etching utilizing the battery reaction, if the thickness of the upper layer is reduced, even if the shape of the side end face is perpendicular to the substrate surface or an inverted tapered shape, it is formed on the upper portion thereafter. Poor step coverage of the film can be avoided.

FIG. 19 shows that the upper layer is made of a Cr--Mo alloy (20 n
m) shows the relationship between the taper angle of the etching edge of the laminated film and the withstand voltage of the insulating film when an insulating film (silicon nitride, 300 nm) is formed on the laminated film whose lower layer is Cr (180 nm). . As the taper angle becomes smaller, the dielectric strength increases.
× 10 ⁵ V / mm or more. The electric field applied to the TFT at the time of TFT characteristic inspection and characteristic correction is up to 2.5 ×
10 ⁵ V / mm. Therefore, a maximum of 2.5 × 10 ⁵ V / mm applied during TFT characteristic inspection and characteristic correction
In order to prevent dielectric breakdown of the insulating film due to the electric field (60 V in terms of the potential difference), the taper angle of the etching side edge of the laminated film is 6
Must be 0 ° or less.

FIG. 6 is an explanatory view of a change in the length of a crack entering the CVD film formed in the gate wiring portion when the thickness ratio of the upper layer and the lower layer is changed. The ratio a / b of the thickness b of the upper layer is shown by taking the crack length (nm) on the vertical axis. In addition, in the film cross-sectional view in the figure, CL indicates a crack.

As shown in the figure, when the film thickness a of the upper layer 2B is larger than the film thickness b of the lower layer 2A, that is, when a / b is 1 or more, the insulating film 6 of the CVD film to the gate wiring 2 is formed. Poor coverage and long cracks.

On the other hand, as a / b decreases, cracks become less likely to occur. When a / b is 0.5 or less, the occurrence of cracks is drastically reduced. The breakdown voltage between the drains is improved.

The upper layer 2B is formed to be thin so that a / b is 0.5 or less, preferably 0.3 or less, so that there is no crack or no problem in practical use. it can. For example, the thickness of the lower layer 2A is set to 200
When the thickness is set to nm, the film thickness of the upper layer 2B is 60 nm or less, and excellent step coverage with almost no cracks can be realized.

As the thickness of the upper layer 2B is smaller, the influence of cracks on the insulating film formed thereon can be reduced. However, the thickness required for forming the thin film over the entire surface of the substrate is 10 nm or more. The thickness of the upper layer 2B is 10 nm or more and 60 nm.
It is desirable to do the following.

Here, the mechanism of the taper etching of the laminated film structure of the pure Cr layer and the Cr—Mo alloy layer will be described.

Comparing the processing rate, ie, the etching rate, of the Cr—Mo alloy layer and pure Cr alone,
The o alloy layer is about four times faster than pure Cr. Therefore, C
When an r-Mo alloy layer is laminated on a pure Cr layer to form a multilayer film, pure Cr is more likely to undergo side etching earlier, and the Cr-Mo alloy layer is left overhanging on the pure Cr. is there. However, in reality, the Cr-Mo alloy layer performs side etching earlier than the pure Cr layer, and as a result, a favorable forward tapered shape is formed at the etching side edge. This is not only due to a mere etching rate difference, but also because a battery reaction occurs due to a potential difference between the two layers and the etching rate is reversed.

When a material is immersed in a solution, an oxidation-reduction potential of the material in the solution is developed. In a solution in a corrosive environment, the material develops an oxidation-reduction potential, that is, a corrosion potential when dissolved. When two different electrodes are immersed in the same solution, each shows a different corrosion potential. When these electrodes are connected, a potential difference occurs between the two types of electrodes, and a current flows. This configuration is called a galvanic cell, and the current is called a galvanic current.

In this galvanic cell, the one with a lower oxidation-reduction potential functions as an anode electrode, and an oxidation reaction occurs on the surface of the anode electrode, and the electrode is ionized and melted. On the other hand, the one having a lower oxidation-reduction potential functions as a cathode electrode, and a reduction reaction of water occurs on the cathode electrode side to generate hydrogen.

When the laminated structure of the Cr—Mo alloy layer and the normal Cr layer is immersed in a Cr etching solution, the Cr—Mo alloy layer and the normal C layer
A galvanic cell is formed with the r layer, an oxidation-reduction reaction occurs in a portion in contact with the etchant, and a galvanic current flows at the interface between the two layers.

In the Cr etching solution, the corrosion potential of the Cr—Mo alloy layer is about 20 mV lower than that of forward Cr, so that the Cr—Mo alloy layer serves as an anode electrode, the forward Cr layer serves as a cathode electrode, and the galvanic Electric current flows.

Originally, both the Cr—Mo alloy layer and the forward Cr layer have undergone an oxidation reaction, for example, etching represented by the following equations (1) and (2).

Cr → Cr ³⁺ + 3e (1) Mo → Mo ³⁺ + 3e (2) Here, Cr on the anode side of the galvanic cell
On the -Mo alloy layer side, an oxidation reaction, that is, an etching reaction represented by the above formulas (1) and (2) is promoted. On the other hand, on the side of the forward Cr layer on the side of the cathode electrode, hydrogen gas is generally generated by a reduction reaction of water, but an etching reaction, which is an oxidation reaction of Cr shown in the formula (1), also occurs here. In this case, the Cr ion is converted into the following equation (3).
As shown in (1), by partially reducing, the etching reaction of Cr is suppressed.

Cr ³⁺ + 3e → Cr (3) In the battery reaction as described above, the etching of the upper Cr—Mo alloy layer is completed, and the lower pure Cr layer and the upper Cr—Mo
It starts from the moment when both layers of the Mo alloy layer come into contact with the etching solution. That is, the side etching of the upper Cr-Mo alloy layer is accelerated with the completion of the etching of the Cr-Mo alloy layer in the thickness direction. As a result, the Cr-Mo alloy layer near the interface is etched fastest and recedes.

The lower pure Cr layer comes into contact with the etchant faster as it approaches the interface, so that the etchant infiltrates there and the etching of the Cr layer proceeds. Therefore, the lower the pure Cr layer, the closer to the interface with the Cr—Mo alloy layer, the more the etching retreats, and the lower pure Cr layer is processed into a forward tapered shape.

The potential difference between the Cr—Mo alloy layer and the pure Cr layer is highest at the lamination interface, and the potential difference decreases as the distance from the interface increases. Therefore, the upper layer Cr
Since the oxidation reaction of the -Mo alloy layer is smaller on the upper side (resist side), the side etching rate is smaller. As a result, the side edges of the Cr—Mo alloy layer have a slight reverse taper or a shape close to vertical.

The cross-sectional shape when a pure Cr layer and a Cr—Mo alloy layer are simply laminated is usually determined by the magnitude relation between the side etching rate of the upper layer and the side etching rate of the lower layer. Thus, the side etching of the interface can be controlled by adding a corrosion potential difference adjusting solution to the etching solution. As the corrosion potential difference adjusting liquid, nitric acid is suitable when the etching liquid is ceric ammonium nitrate.

In the prior art, especially in the case of a single layer, the side etching by the infiltration of the etching solution at the interface between the resist and the film is the side etching rate of the film itself and the side etching rate at the interface of the base. in this case,
With regard to (1), the penetration of the etching solution at the interface between the resist and the film greatly depends on the adhesion between the resist and the film. Therefore, as the screen becomes larger, it becomes more difficult to control the resist adhesion uniformly. That is, the side etching rate increases in a place where the adhesion is small. as a result,
Variations in the taper shape occur within the substrate.

On the other hand, according to the present invention, by introducing in addition to the above, it is possible to control only the oxidation-reduction potential of the material having the tapered shape laminated. Therefore,
Even if the in-plane distribution of the resist adhesion is large, the influence can be eliminated, and the cross-sectional shape can be uniformly controlled in the plane regardless of the substrate area.

FIG. 7 shows nitric acid nitrate of pure Cr and a Cr—Mo alloy.
It is explanatory drawing of the result of having measured the change of the corrosion potential in the cerium aqueous solution, changing the Mo density | concentration.

When the pure Cr, that is, the Mo concentration is 0, the corrosion potential is 1100 mV, and Cr-Mo containing 50 wt% of Mo is used.
Alloy, 1080m for Cr-50Mo alloy
V. The taper etching shown in FIG. 4 can be performed by utilizing the potential difference between the two. Since the corrosion potential of pure Mo is as low as 360 mV, the corrosion potential of the Cr—Mo alloy decreases as the Mo concentration increases.

FIG. 8 is an explanatory diagram of the change in the taper angle when the composition of the Cr—Mo alloy combined with pure Cr is changed.

As shown, when the Mo concentration is 0,
That is, in the case of pure Cr, the wiring is made of Cr alone, and the taper angle is 90 degrees (perpendicular to the substrate surface), and in the case of Cr-50Mo, it is about 60 degrees. The lower the taper angle, the better the coverage of the CVD film and the wiring film, but the larger the side etch amount, the lower the pattern accuracy. Therefore, the taper angle is selected in the range of 10 to 60 degrees as needed.

Based on the above technical matters, the present invention makes it possible to control the side etching of the interface by adding a corrosion potential difference adjusting solution to the etching solution, thereby greatly improving the taper angle distribution in the substrate surface. Things. As the corrosion potential difference adjusting liquid, nitric acid is suitable when the etching liquid is ceric ammonium nitrate.

Further, in the case of the taper processing utilizing the infiltration of the etching solution between the photoresist and the metal thin film, the taper angle increases due to the in-plane variation in the adhesion between the photoresist and the metal thin film. In some cases, the taper angle between the central portion and the peripheral portion is about twice as large. In contrast,
In the case of the present invention, since the corrosion potential difference is determined by the material used, according to the present invention utilizing the potential difference between the upper film and the lower film, the in-plane variation of the etched taper angle is extremely small. It is small and can be controlled within ± 9%.

FIG. 9 is a graph for explaining the change in corrosion potential with respect to the amount of HNO ³ added to ceric ammonium nitrate. In the figure, △ is pure Cr, □ is Cr-30Mo, ◇
Indicates the case of Cr-50Mo. The corrosion potential is Ag
-Based on the corrosion potential of AgCl. FIG. 9 shows that the corrosion potential of pure Cr was high, and that of Cr-30Mo and Cr-
It is shown that all of 50Mo are low.

FIGS. 10A and 10B are diagrams illustrating the change in galvanic current with respect to the amount of HNO ₃ added to ceric ammonium nitrate. FIG. 10A shows pure Cr and Cr-30Mo.
(B) shows the change in galvanic current of pure Cr and Cr-50Mo pair.

As can be seen from FIG. 10, the galvanic current increases as the amount of added nitric acid increases, that is, the corrosion potential difference between pure Cr and the Cr—Mo alloy increases.

FIG. 11 is a graph for explaining the change in galvanic voltage with respect to the amount of HNO ₃ added to ceric ammonium nitrate. FIG. 11A shows pure Cr and Cr-30Mo.
(B) shows the change in galvanic current of pure Cr and Cr-50Mo pair.

As can be seen from FIG. 11, the galvanic voltage difference between Cr and the Cr—Mo alloy, that is, the corrosion potential difference, increases as the amount of added nitric acid increases. When the counter electrode is Cr and the sample electrode is a Cr-Mo alloy, and the electrodes are short-circuited and immersed in the same test solution, a galvanic current flows between the electrodes to compensate for the galvanic potential. The corrosion potential difference takes a value approximately halfway between the corrosion potential of Cr and the corrosion potential of the Cr-Mo alloy. The corrosion potential increases as the amount of nitric acid increases.

FIG. 12 is a graph for explaining the change in the taper angle of the etching side edge of the laminated film with respect to the amount of HNO ³ added to ceric ammonium nitrate.
□ indicates the taper angle of the laminated film of r-30Mo, and □ indicates the taper angle of the laminated film of Cr / Cr-50Mo.

As shown in FIG. 12, Cr / Cr-3
Regardless of whether it is 0Mo or Cr / Cr-50Mo, the taper angle of the etching side edge to which the corrosion potential difference adjusting liquid (HNO ³ ) is not added does not fall below 60 ° with respect to the substrate.

On the other hand, a corrosion potential difference adjusting solution (HN
O ₃ ) in 5 vol. % / Cr / Cr-30
56 ° for Mo, 48 ° for Cr / Cr-50Mo,
The addition amount is 10 vol. %, 20 vol. %, 40vo
l. %, 52 ° and 46 °, 48 ° and 4
4 °, 45 ° and 45 °, and the amount of addition was 40 vol. %
Then, they become 16 ° and 15 °, respectively.

The phenomenon that the taper angle is reduced is caused by the concentration of 0 vo.
l. % To 40 vol. %, The above-mentioned battery reaction contributes, and 40 vol. %, The nitric acid having a strong penetrating power penetrates into the resist / thin film interface, and the effect of accelerating the etching at the interface and the effect of the above-described battery reaction are combined, so that the taper angle rapidly decreases. .

Conventionally, there is a technique of performing taper processing by adding nitric acid. However, this technique utilizes only a strong penetrating force to the resist / thin film interface, and is not used as a corrosion potential difference adjusting liquid. The present invention is characterized in that nitric acid is used as a corrosion potential difference adjusting liquid. Thus, a taper angle of 60 ° or less can be formed by adding the corrosion potential difference adjusting liquid to the etching liquid.

FIG. 13 shows Cr / Cr-Mo when only ceric ammonium nitrate was used as an etching solution.
It is a mimic view of the image which image | photographed the etching state of the laminated film with the scanning electron microscope, (a) is Cr / Cr-30Mo.
(B) shows the etching state of each section of the Cr / Cr-50Mo laminated film. In the figure, SUB indicates a substrate, and R indicates a resist.

FIG. 14 shows ceric ammonium nitrate as an etching solution and nitric acid (HN) as a corrosion potential difference adjusting solution.
O ₃ ) at 10 vol. % Cr / Cr-M
o is a mimetic diagram of an image of the etching state of the laminated film taken by a scanning electron microscope, wherein (a) is Cr / Cr-30M
(b) shows the etching state of each section of the Cr / Cr-50Mo laminated film. In the figure, SUB indicates a substrate, and R indicates a resist.

As is apparent from a comparison between FIG. 13 and FIG. 14, the taper angle of the etching side edge is not less than 60 ° in FIG. 13, but in FIG. The corrosion potential difference between the film Cr and Mo increases, and the battery reaction is promoted, so that the taper angles at the etching side edges are 52 ° and 46 °, respectively.
° down to.

FIG. 15 shows that ceric ammonium nitrate as an etchant is treated with nitric acid (H
NO ₃ ) at 60 vol. % When Cr / Cr-
It is a mimetic diagram of the picture which photoed the etching state of the Mo lamination film with the scanning electron microscope, and (a) is Cr / Cr-30.
The Mo laminated film, (b) shows the etching state of each section of the Cr / Cr-50Mo laminated film.

In FIG. 15, in addition to the effect of accelerating the battery reaction by the corrosion potential difference adjusting liquid, a nitric acid (HNO ₃ ) resist / Cr
-The taper angle is (a)
And (b) are reduced to 16 ° and 15 °, respectively. When the taper angle of the etching side edge of the laminated film becomes 45 ° or less, the taper angle of the upper layer Cr—Mo alloy becomes a forward taper shape.

As described above, according to the present invention, the taper angle of the edge on the etching side with respect to the substrate can be reduced to 60 ° or less by adding the corrosion potential difference adjusting solution to the etching solution, so that good step coverage can be obtained. Thin film electrode wiring becomes possible.

When the present invention is applied to the formation of a gate wiring in an inversely staggered TFT, an insulating film (gate insulating film) made of SiN or the like formed thereon, a-Si
The step coverage of the semiconductor film, the drain wiring, and the like is improved, and as a result, the withstand voltage is improved and the disconnection failure rate of the drain wiring is reduced.

Further, even when the upper layer containing Mo is dry-etched with a fluorine-based gas, fluoride is hardly formed,
Since it is hard to be oxidized even in an oxidizing atmosphere, good contact with another electrode formed on the electrode is maintained.

As long as the corrosion potential difference can be adjusted, a chemical solution other than nitric acid may be used as the corrosion potential difference adjusting solution.
For example, hydrogen peroxide and perchloric acid are added to an aqueous solution of ceric ammonium nitrate to form Cr and Cr.
The corrosion potential difference between −Mo can be adjusted, and the taper angle of the etching side edge of the laminated film can be set to 60 ° or less.

[0104]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

FIG. 1 is a partial cross-sectional view illustrating the structure of a main part of a liquid crystal display device according to the present invention, and FIG. 2 is a partial plan view illustrating the structure of the main part.
Substrate, 1 ′: filter substrate, 2: scanning signal line (gate wiring (electrode)), 3: video signal line (drain wiring (electrode)), 4: source wiring (electrode), 5: pixel electrode, 6: insulating Film, 7 a semiconductor layer, 7A a contact layer, 8 a protective film, 8A a contact hole, 9 a color filter, 1
0 indicates a black matrix, 11 indicates a smooth layer, 12 indicates a common electrode, TFT indicates a thin film transistor, Cadd indicates an additional capacitance element, and LC indicates liquid crystal. Reference numerals 3A and 3B denote drain wirings 3, 4A and 4B, a stacked portion of a Cr-Mo alloy layer and pure Cr forming source wiring 4, 2A a first layer (lower layer) forming gate wiring 2, 2B is the second layer (upper layer).

The lower layer 2A of the gate electrode 2 is a pure Cr layer, and the upper layer 2B is a Cr-Mo alloy layer. And
The thickness of the lower layer 2A is 180 nm, and the thickness of the upper layer 2B is 20 n.
As m, most of the side end faces of the wiring have a favorable forward taper of 60 ° or less. Although the side end surface of the upper layer 2B has a shape perpendicular to the substrate surface as shown in FIG. 1, since its layer thickness is small, it does not significantly affect the forward tapered shape of the entire wiring.

As described above, since the gate wiring 2 has a laminated structure and a favorable forward taper is formed in the first pure Cr layer, disconnection of the drain wiring 3 and the source wiring 4 formed thereon is prevented. In addition, it is possible to avoid a problem that a crack or a pinhole occurs in the insulating film 6. In addition, since the lower layer that is in contact with the substrate is a pure Cr layer, the adhesion between the gate wiring 2 and the substrate is increased, and peeling of the wiring or electrode due to thermal stress or the like can be prevented.

An insulating film 6 for interlayer insulation between the gate wiring 2 and the drain wiring 3 and the source wiring 4 as described later is formed on the entire surface of the substrate 1 on which the gate wiring 2 is formed as described above. A silicon nitride (SiN) film is formed.

Then, a thin film transistor TFT is formed above the insulating film 6 at one corner of the pixel region surrounded by the gate line 2, the drain line 3, and the source electrode 4. In a region where the thin film transistor TFT is formed, the surface of the insulating film 6 located above the gate wiring 2 above the insulating film 6 functioning as a gate insulating film is made of amorphous silicon so as to extend over the gate wiring 2. A semiconductor layer 7 made of (a-Si) is formed.

The semiconductor layer 7 has the source wiring 4
Is formed below the formation region. The reason why the source wiring 4 has a laminated structure with the semiconductor layer 7 is to prevent disconnection and to reduce the capacitance between the gate wiring 2 and the crossing.

A drain wiring 3 and a source wiring 4 are formed on the surface of the semiconductor layer 7 in the region where the thin film transistor TFT is formed, and these wirings 3 and 4 have the gate wiring 2 therebetween when viewed in plan. Are arranged facing each other.

The drain wiring 3 on the surface of the semiconductor layer 7
At the interface with the source wiring 4, a contact layer 7A in which the semiconductor layer 7 is doped with a high concentration of impurity is formed. This high-concentration impurity layer is formed on the entire surface when the semiconductor layer 7 is formed, and the impurity layer exposed from each of the wirings 3 and 4 is formed by using the wirings 3 and 4 formed thereafter as a mask. It is formed by etching.

The drain wiring 3 and the source wiring 4 are formed in the same step and of the same material. As an example of this material, the gate wiring 2
The same laminated wiring as described above is used. Further, a single-layer alloy layer of Cr and Mo may be used.

Further, as shown in FIG.
Is formed so as to extend to the formation region of the pixel electrode 5, and is configured to make contact with the pixel region 5 in this extension portion.

Here, the source wiring 4 is formed of the same material as the drain wiring 4, and alloy layers 3B and 4B of Cr and Mo are formed.
And a pure Cr layer 3AM4A. The alloy layer of Cr and Mo is formed of the above Cr-
It is not limited to 30Mo and Cr-50Mo.

A protective film 8 made of, for example, a silicon nitride film (SiN) is formed on the entire surface of the substrate 1 thus processed in order to avoid direct contact of the liquid crystal with the thin film transistor TFT. The protective film 8 has a contact hole 8A for exposing a part of the extension of the source wiring (electrode) 4.

In the pixel region on the upper surface of the protective film 8, a pixel electrode 5 made of, for example, an ITO film is formed. The pixel electrode 5 can be electrically connected to the source line 4 through the contact hole 8A.

In this case, a part of the pixel electrode 5 is a gate wiring (electrode) 2 for driving the thin film transistor TFT.
Of the insulating film 6 and the protective film 8 interposed between the pixel electrode 5 and the adjacent gate line 2 ′. An additional capacitor Cadd having a body as a dielectric film is formed.

As shown in FIG. 1, the substrate 1 on which various films are formed as described above is bonded to the other substrate (transparent substrate) 1 'with the liquid crystal LC interposed therebetween. On the liquid crystal LC side of the other substrate 1 ′, a plurality of color filters 9 partitioned by a black matrix 10, and a common electrode 12 common to each pixel region via a smooth layer 11 covering the color filters 9, for example, ITO It is formed with.

With the structure described above, disconnection and short circuit of the drain wiring (electrode) and the source wiring (electrode) are reduced, and a highly reliable liquid crystal display device can be obtained.

Next, an example of a method for manufacturing a liquid crystal display device according to the present invention will be described with reference to FIGS.

FIGS. 3 and 4 are schematic process diagrams illustrating an example of a method for manufacturing a liquid crystal display device according to the present invention. The same reference numerals as those in FIGS. 1 and 2 correspond to the same parts.

First, the first layer (lower layer) 2A of the pure Cr layer is formed over the entire main surface of the glass substrate 1 by using a sputtering method or the like.
Is formed to a thickness of 180 nm (FIG. 3A).

Next, a Cr-50Mo alloy layer was formed to a thickness of 20 nm by sputtering or the like to cover the upper layer of the first layer.
To form a second layer (upper layer) 2B,
A laminated structure serving as an r wiring is formed (FIG. 3B). This laminated structure is to be the gate wiring (electrode) 2.
By setting the amount of Mo contained in the upper layer Cr-Mo alloy to 50 wt% or less, the resist adhesion becomes good without using a resist adhesion enhancer using a silicon coupling agent such as hexamethyldisilazane, and pattern formation. The process can be simplified without compromising accuracy.

A photoresist 20 is applied to the entire upper surface of the laminated structure (FIG. 3C), and the gate electrode terminal 2 of the thin film transistor TFT formed integrally with the gate wiring 2 is formed.
The photoresist 20 is selectively exposed through a photomask 20a having a pattern such as C.

Thereafter, the photoresist 20 is developed to remove the photoresist corresponding to a region other than the formation region of the gate wiring 2 and the gate wiring terminal 2C and the like, thereby exposing the laminated structure in the removed portion. (D in FIG. 4).

Using the remaining photoresist 20 as a mask, the exposed laminated structure is immersed in an etching solution to perform an etching process. As the etching solution, a solution obtained by adding nitric acid as a corrosion potential difference adjusting solution to a ceric ammonium nitrate aqueous solution is used. At the time of this etching treatment, the corrosion potential of each of the upper and lower layers constituting the laminated structure is, as described with reference to FIG.
Mo alloy layer is 1080 mV, pure Cr under layer is 1100
mV, and a potential difference of 20 mV occurs between the two. In addition, by adding nitric acid as a corrosion potential difference adjusting liquid, the battery reaction was promoted as described in FIGS.
By making the corrosion potential of the upper layer lower than that of the lower layer, the upper layer having a lower corrosion potential is etched faster than the lower layer by the battery reaction, and both sides of the gate electrode 2 are placed at 60 ° with respect to the substrate.
The following favorable forward taper angle can be provided (FIG. 4E). At this time, since the side end surface of the upper layer has a shape perpendicular to the substrate surface or has an inverse taper, it is desirable to form the upper layer to be thinner than that of the lower layer. For example, the upper layer has a thickness of 20 nm and the lower layer has a thickness of 180 nm.

After the etching process is completed, the photoresist 20 is removed, and the gate wiring 2, the gate wiring terminal 2C and the like are formed by the laminated film remaining by the etching process (f in FIG. 4).

Hereinafter, the TFT substrate is processed in the following steps on the substrate 1 on which the gate wiring 2, the gate wiring terminal 2C, etc. are formed in the above steps.

First, the insulating layer 6 made of silicon nitride and the i-type amorphous Si (a-Si) are formed over the entire area of the main surface of the substrate 1 on which the gate wiring 2, the gate wiring terminal 2C, etc. are formed by the above steps. A semiconductor layer 7 and an amorphous Si semiconductor contact layer 7A doped with an n-type impurity are sequentially formed using, for example, a CVD method.

In this case, the manufacturing process can be simplified by successively forming the insulating layer 6, the semiconductor layer 7, and the semiconductor contact layer 7A doped with n-type impurities successively by using the same CVD apparatus. . At this time, FIG.
Is processed into a forward taper as a whole, so that a C film formed on the gate wiring 1C is formed.
The coverage of the gate insulating film by VD is improved, and defects in the gate insulating film and short-circuits between the drain wiring, source wiring, and the like formed on the gate insulating film and the gate wiring and disconnection thereof are avoided.

Then, a photoresist film is applied to the entire upper surface of the semiconductor contact layer 7A doped with the n-type impurity, and is selectively exposed through a photomask on which a pattern of the thin film transistor TFT is formed.

Thereafter, the photoresist film is developed to remove the photoresist film in a region other than the region where the thin film transistor TFT is formed. From the removed portion, the upper surface of the semiconductor contact layer 7A doped with the n-type impurity is removed. To expose.

Using the remaining photoresist film as a mask, the semiconductor contact layer 7 exposed from the mask is exposed.
A and the underlying semiconductor layer 7 are selectively etched.

In this case, the insulating film layer 6 located below the semiconductor layer 7 is left without being etched.

Thus, in the region where the thin film transistor TFT is formed, a silicon nitride film serving as a gate insulating layer,
An i-type amorphous Si semiconductor layer and an amorphous Si semiconductor layer doped with an n-type impurity serving as a contact layer are sequentially formed.

Further, a layered structure of a semiconductor contact layer 7A doped with an n-type impurity and a semiconductor layer 7 is formed below the source electrode 4 formed thereafter.

Further, a laminated structure of an alloy layer of Cr and Mo and a normal Cr layer is formed on the entire main surface of the substrate 1 processed as described above, for example, by a sputtering method.
This laminated structure includes a source wiring 4 and a drain wiring 3,
The photoresist is selectively exposed through a photomask on which a pattern such as the drain wiring terminal 3B is formed.

Thereafter, by developing the photoresist film, the photoresist film corresponding to a region other than the formation region of the source wiring 4, the drain wiring 3, the drain wiring terminal 3B and the like is removed, and from the removed portion, The above alloy film is exposed.

Then, using the remaining photoresist film as a mask, the alloy layer exposed from the mask is selectively etched.

As a result, the source wiring 4, the drain wiring 3, and the drain wiring terminal 3 depend on the remaining alloy layer.
B and the like are formed.

Further, the semiconductor contact layer 7A, which is an upper layer of the semiconductor layer 7 formed in the formation region of the thin film transistor TFT and is doped with an n-type impurity, is selectively etched by using the source wiring 4 and the drain wiring 3 as a mask. I do. As a result, the remaining semiconductor contact layer 7A doped with the n-type impurity is formed only at the interface between the semiconductor layer 7 and the source wiring 4 and the drain wiring 3, and functions as the contact layer 7A.

Next, a protective film 8 made of silicon nitride is formed on the entire main surface of the substrate 1 processed in each of the above steps, for example, by a plasma CVD method. At this time, the side edges of the source wiring 4 and the drain wiring 3 are connected to the lower gate wiring 2.
Is formed in a forward tapered shape as a whole according to the shape of the above, the step coverage by the protective film 8 is improved, and the protective film 8 with few film defects such as pinholes at the portions where the gate wiring and the drain wiring run up is obtained. be able to. Further, by processing the gate wiring and the drain wiring into a forward tapered shape, the step on the surface of the portion where the thin film transistor TFT is formed becomes gentle.

A contact hole 8A is formed in the protective film 8.
To form At this time, the protective film 8 and the gate wiring terminal 2 formed on the upper surface of the drain wiring terminal 3B at the same time.
An opening is formed in the protective film 8 formed on the upper surface on C.

Dry etching is performed using the mask used for processing the protective film 8 as it is. As a result, a through-hole is formed in the insulating layer 6, and an opening is formed in the gate wiring terminal 2C, the drain wiring terminal, 3B and a desired area until the surface of the substrate 1 is exposed. When forming a through hole with a dry etching gas, the electrode surface is exposed to the gas during the over-etching time. By making the surface of the source wiring a Cr-Mo alloy layer, the formation of fluorides and chlorides is less than in the case of a pure Cr layer, so that the contact characteristics with the upper ITO film can be greatly improved. Can be.

An ITO film is formed on the entire surface of the substrate 1 thus processed. An appropriate thickness of the ITO film is 70 to 300 nm.
nm.

A photoresist film is formed on the entire surface of the ITO film, and the photoresist film is selectively exposed through a photomask having a pattern such as a pixel electrode 5, a gate wiring, and a drain wiring terminal.

Then, the photoresist film is developed, and the photoresist film other than the formation region of the pixel electrode 5, the gate wiring, the drain wiring terminal and the like is removed.

Using the remaining photoresist film as a mask, the ITO film exposed from the mask is selectively etched. Thus, the pixel electrode 5 and the like are formed by the remaining ITO film.

The filter substrate 1 ′ shown in FIG. 1 is mounted on the TFT substrate 1 on which necessary wirings, electrodes, etc. are formed in each of the above steps.
And a liquid crystal LC is sealed in the gap between them to obtain a liquid crystal panel. Although not shown, an alignment film for initially aligning the molecules of the liquid crystal LC is formed on a surface of the active filter substrate that is in contact with the liquid crystal LC.

The liquid crystal panel manufactured as described above is assembled with various components as described with reference to FIG. 7 to obtain a liquid crystal display device.

In the above-described embodiment, as the material of the gate wiring 2, a layer on the substrate side (first layer; pure Cr is used as a lower layer, and a single-layer Cr—Mo alloy layer is used as an upper layer (second layer)). Although a single-layer Cr—Mo alloy layer is used as the drain wiring 3 and the source wiring 4, the present invention is not limited to this, and the drain wiring may have the same laminated structure as the gate wiring. The manufacturing method is the same as that of the gate wiring.

Also, instead of Cr, aluminum (A
Needless to say, l), titanium (Ti), tungsten (W), and other metal materials as wiring (electrode) materials having the processing characteristics of the present invention can be used alone or in the form of an alloy.

[0154]

As described above, according to the present invention,
Thin film transistor It is possible to form a favorable forward taper shape on the side end surface of the scanning signal line (electrode), particularly on the side end surface of the scanning signal line. Defects and short circuits between the upper and lower layers can be prevented.

Further, in particular, by adopting a laminated structure in which a pure chrome layer is a lower layer and a chromium-molybdenum alloy layer is an upper layer as a material of the scanning signal lines, other scanning signal lines and electrodes formed on the upper layer are formed. Good contact with the metal thin film. Furthermore, the use of pure chrome for the layer on the substrate side enhances the adhesion to the substrate, and prevents film peeling due to heat history, thermal stress, and the like in the subsequent processing steps.

By providing a forward tapered shape of 60 ° or less to the side end face of the lower wiring, the unevenness on the surface of the thin film transistor substrate becomes gentle, the alignment defect of the liquid crystal is reduced, and the liquid crystal display device having a good contrast. Can be provided.

Note that the present invention is not limited to the so-called vertical electric field type liquid crystal display device described in the above embodiment, but the so-called horizontal electric field type liquid crystal display device in which the common electrode is also formed on the active matrix substrate side, or The present invention can be similarly applied to other types of liquid crystal display devices having crossover portions where electrode wirings cross each other and various similar semiconductor devices.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view illustrating a main structure of a liquid crystal display device according to the present invention.

FIG. 2 is a partial plan view illustrating a main structure of a liquid crystal display device according to the present invention.

FIG. 3 is a schematic process diagram illustrating an example of a method for manufacturing a liquid crystal display device according to the present invention.

FIG. 4 is a schematic process drawing following FIG. 3 for explaining an example of the method for manufacturing a liquid crystal display device according to the present invention.

FIG. 5 is a schematic diagram illustrating the progress of etching by a battery reaction when a difference is made in the corrosion potential between the upper layer and the lower layer.

FIG. 6 is an explanatory diagram of a change in the length of a crack entering a CVD film formed in a gate wiring portion when the thickness ratio of an upper layer and a lower layer is changed.

FIG. 7 is an explanatory diagram showing the results of measuring the change in corrosion potential of pure Cr and a Cr—Mo alloy in a ceric nitrate aqueous solution while changing the Mo concentration.

FIG. 8 is an explanatory diagram of a change in a taper angle when a composition of a Cr—Mo alloy combined with pure Cr is changed.

FIG. 9: HN added to ceric ammonium nitrate
FIG. 4 is an explanatory diagram of a change in corrosion potential with respect to an added amount of O ₃ .

FIG. 10: H added to ceric ammonium nitrate
FIG. 4 is an explanatory diagram of a change in galvanic current with respect to an added amount of NO ₃ .

FIG. 11 shows H added to ceric ammonium nitrate
FIG. 4 is an explanatory diagram of a change in galvanic voltage with respect to an addition amount of NO ₃ .

FIG. 12 shows H added to ceric ammonium nitrate
FIG. 4 is an explanatory diagram of a change in a taper angle of an edge on an etching side of a laminated film with respect to an added amount of NO ₃ .

FIG. 13 is a simulated view of an image taken by a scanning electron microscope of an etching state of a Cr / Cr—Mo laminated film when only ceric ammonium nitrate is used as an etching solution.

FIG. 14 shows a case where ceric ammonium nitrate is used as an etching solution and nitric acid (HNO ₃ ) is used as a corrosion potential difference adjusting solution.
0 vol. FIG. 4 is a schematic view of an image of the etching state of the Cr / Cr-Mo laminated film when added by%, taken by a scanning electron microscope.

FIG. 15 shows ceric ammonium nitrate as an etching solution and HNO ₃ as a corrosion potential difference adjusting solution at 60 vol.
l. FIG. 4 is a schematic view of an image of the etching state of the Cr / Cr-Mo laminated film when added by%, taken by a scanning electron microscope.

FIG. 16 is an exploded perspective view illustrating the entire configuration of an active matrix liquid crystal display device using an alignment film according to the present invention.

FIG. 17 shows a TF constituting the liquid crystal display device shown in FIG. 16;
FIG. 3 is a schematic diagram illustrating a wiring structure near one pixel of a T substrate.

FIG. 18 is a partial cross-sectional view illustrating a structure near a TFT for explaining a configuration example of a liquid crystal display device according to a conventional technique.

FIG. 19 is a diagram for explaining the relationship between the taper angle of the edge on the side of etching the laminated film and the withstand voltage of the insulating film thereover.

[Explanation of symbols]

Reference Signs List 1 TFT substrate 1 'filter substrate 2 scanning signal line (gate wiring or gate electrode) 2A first layer (lower layer) constituting scanning signal line (gate wiring or gate electrode) 2B second layer (upper layer) 3 drain electrode ( Drain wiring) 4 Source electrode (source wiring) 5 Pixel electrode 6 Insulating film 7 Semiconductor layer 7A Contact layer 8 Protective film 8A Contact hole 9 Color filter 10 Black matrix 11 Smoothing layer 12 Common electrode TFT Thin film transistor Cadd Additional capacitance element.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takuya Takahashi 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Kazumi Fujii 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. Hitachi Hitachi Laboratory

Claims (8)

[Claims] A first metal layer on an insulating substrate;
And a wiring having a laminated structure in which a second layer made of a second metal layer different from the first metal layer is formed on the first layer, and a side end surface of the first layer has a taper angle. The second layer has a forward tapered shape of 60 ° or less, the side end surface of the second layer is either a shape perpendicular to the substrate surface, or an inverted tapered shape, and the thickness of the second layer is equal to that of the first layer. A liquid crystal display device characterized in that the thickness is not more than half of the film thickness. 2. A substrate having a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of a pixel. And a liquid crystal display device having at least a color filter and the other substrate bonded to the one substrate with a minute gap, and a liquid crystal sealed in a gap between the one substrate and the other substrate. A first layer made of a pure chrome layer formed on the one substrate side;
It has a laminated structure of chromium formed on the layer and a second layer composed of an alloy layer containing molybdenum as a main component, and a side end face of the first layer has a forward tapered shape with a taper angle of 60 ° or less,
The side end surface of the second layer is either a shape perpendicular to the substrate surface or an inverted taper shape, and the thickness of the second layer is not more than half the thickness of the first layer. A liquid crystal display device characterized by the above-mentioned. 3. One substrate including a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of a pixel. And a liquid crystal display device comprising at least a color filter and the other substrate bonded to the one substrate with a minute gap, and a liquid crystal sealed in a gap between the one substrate and the other substrate. A base layer made of a thin film layer of an insulating material on a substrate, wherein the wiring of the scanning signal line is made of an alloy layer containing chromium and molybdenum as main components, and a pure chrome layer is provided between the alloy layer and the base layer; The side end surface of the first layer has a forward taper shape with a taper angle of 60 ° or less, and the side end surface of the second layer has a shape perpendicular to the substrate surface or an inverted taper shape. Yes and before The liquid crystal display device, wherein the thickness of the second layer is less than one-half of the thickness of the first layer. 4. A semiconductor device comprising: a plurality of wirings including a gate line and a drain line; a video signal line; and a pixel electrode; and an active element connected to the gate line, the drain line and the video signal line to control on / off of a pixel. One substrate, the other substrate provided with at least a color filter and bonded to the one substrate with a small gap, a liquid crystal display device having a liquid crystal sealed in the gap between the one substrate and the other substrate, A first layer made of a pure chrome layer formed on the one substrate side, the first layer having a base layer made of an insulating thin film layer on at least one of the substrates, and a gate layer formed on the first layer; The drain line has a single-layer structure composed of an alloy layer mainly composed of chrome and molybdenum, and a second layer composed of a second layer composed of an alloy layer mainly composed of molybdenum. The side end surface of the first layer has a forward taper shape with a taper angle of 60 ° or less, the side end surface of the second layer has a shape perpendicular to the substrate surface, or an inverted taper shape, and A liquid crystal display device, wherein the thickness of the layer is not more than half the thickness of the first layer. 5. A semiconductor device comprising: a plurality of wirings including a gate line and a drain line; a video signal line; and a pixel electrode; and an active element connected to the gate line, the drain line and the video signal line to control on / off of a pixel. One substrate, the other substrate provided with at least a color filter and bonded to the one substrate with a small gap, a liquid crystal display device having a liquid crystal sealed in the gap between the one substrate and the other substrate, A first layer made of a pure chrome layer having an underlayer made of a thin insulating material layer on at least one of the substrates, wherein the gate line and the drain line are formed on the one substrate side; A stacked structure of a chromium formed thereon and a second layer made of an alloy layer containing molybdenum as a main component, wherein a side end surface of the first layer has a forward tapered shape with a taper angle of 60 ° or less; It is either side end surface of the layer is vertical shape or inversely tapered shape, on the substrate surface, and the second
A liquid crystal display device, wherein the thickness of the layer is not more than half the thickness of the first layer. 6. At least one of the substrates has a base layer made of a thin film of an insulating material, and a plurality of wirings including the gate line and the drain line, a video signal line, and a pixel electrode on the base layer. 6. The liquid crystal display device according to claim 4, wherein an active element is connected to the gate line, the drain line, and the video signal line to control on / off of a pixel. 7. The gate line has a two-layer structure, the pixel electrode is formed of an indium-tin oxide film, and an additional capacitance is formed by the gate line and an insulating layer formed between the pixel electrode. The liquid crystal display device according to claim 2, wherein an element is formed. 8. A substrate provided with a plurality of wirings including a scanning signal line, a video signal line, and a pixel electrode, and an active element connected to the scanning signal line and the video signal line to control on / off of a pixel. And a method of manufacturing a liquid crystal display device including at least a color filter and the other substrate bonded to the one substrate with a minute gap, and liquid crystal sealed in a gap between the one substrate and the other substrate. The scanning signal line is a thin film having a laminated structure consisting of a lower layer and an upper layer made of metal materials having different compositions, and this thin film is immersed in an etching solution to which a corrosion potential difference adjusting solution is added, and the upper layer in the etching solution is The corrosion potential of the lower layer is set lower than the corrosion potential of the lower layer to cause a battery reaction between the upper layer and the lower layer, and the etching rate of the upper layer having a lower corrosion potential is faster than that of the lower layer. Thereby forming a forward taper on the lower end surface of the thin film of the laminated structure and giving the upper end surface either a shape perpendicular to the substrate surface or an inverted taper shape. Production method.