JP2000168161A - Data-conversion processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a data-conversion processing in a simpler circuit constitution for a printer to print. SOLUTION: One-dimensional data in a main scanning direction which is read by every line by a data input part 1 and stored in a first memory part 2 is rearranged in a sub scanning direction in units of bytes by a CPU 3 and stored in a second memory part 4. The data in units of bytes stored in the second memory part and rearranged in the sub scanning direction is rearranged to data in units of bits by a bit-conversion processing part 5 constituted with use of a hardware means and output to a printing head 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of printing one-dimensional data of a main scanning sequence read in line by line in a sub-scanning direction by collectively printing a plurality of lines in the sub-scanning direction. The present invention relates to a data conversion processing device that performs a de-rasterizing process for conversion.

[0002]

2. Description of the Related Art When printing facsimile reception data and one-dimensional scanner data by a printer, the read data is one-dimensional data arranged in a main scanning direction, but the printer prints a plurality of lines in the main scanning direction. Therefore, it is necessary to convert the one-dimensional data in the main scanning order into data in the sub-scanning order. Conventionally, such data conversion processing is either software processing by a CPU or processing by a complete hardware configuration. Data conversion processing performed by a hardware configuration is described in, for example, Japanese Patent Publication No. 7-47325,
No. 79949.

[0003]

SUMMARY OF THE INVENTION However, CPU
In the software processing according to the present invention, when performing bit processing, a high-speed multi-bit CPU (16
Bit or 32 bits). Further, in the processing by the hardware configuration, a complicated process of sequentially reading data from the memory is required, so that there is a problem that the hardware configuration becomes large. Further, in either case, there is a problem that the cost cannot be reduced because the cost is high. The present invention has been made in order to solve such a problem, and an object of the present invention is to perform such a data conversion process separately by a software process and a hardware process so that the circuit configuration is improved. Is to provide a data conversion processing device that can simplify the processing and reduce the cost.

[0004]

According to a first aspect of the present invention, there is provided a data conversion processing apparatus comprising:
In a data conversion processing device for printing and outputting one-dimensional data of a main scanning sequence read line by line on a plurality of lines in a sub-scanning direction, the one-dimensional data is rearranged in a sub-scanning direction in byte units by arithmetic processing. An arithmetic processing unit and a bit conversion processing unit that rearranges byte-by-byte data rearranged in the sub-scanning direction by the arithmetic processing unit into bit-by-bit data using hardware means are provided. According to a second aspect of the present invention, in the data conversion processing device according to the first aspect, the hardware means includes a latch circuit, a shift register, and a buffer circuit.

[0005]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a system configuration diagram of the data conversion processing device of the present invention. The data conversion processing device includes a data input unit 1 for inputting one-dimensional data in a main scanning sequence, a first storage unit 2 for storing the input one-dimensional data in a main scanning sequence, and a first storage unit. 2. An arithmetic processing unit (hereinafter, referred to as CPU) for performing an arithmetic process of rearranging the one-dimensional data stored in 2 in the sub-scanning direction in byte units
3, a second storage unit 4 for storing data in byte units rearranged in the sub-scanning direction by the CPU 3, and a bit conversion process for rearranging the data stored in the second storage unit 4 into data in bit units The output of the bit conversion processing unit 5 is guided to the print head 5 as print data.

The one-dimensional data is facsimile reception data when the data input unit 1 is, for example, a facsimile machine, and is one-dimensional scanner data when the data input unit 1 is, for example, an image scanner.

FIG. 2 shows an example of a specific circuit configuration of the bit conversion processing section 5. This bit conversion processing unit 5
Are two latch circuits 51a and 51b at the front stage, 28 latch circuits 52a and 52b at the rear stage, and 56
, And seven buffer circuits 54a, 54b,..., And a front-stage latch circuit 51a, 51b and a rear-stage latch circuit 52 are provided.
are controlled by a register 55 controlled by the CPU 3, and shift registers 53a, 53b
, And the buffer circuits 54a, 54b, ... are controlled by the timing generation circuit 56.

The latch circuit 51a is a circuit for temporarily storing the input one-dimensional data of the main scanning sequence in units of one byte and outputting the same in the same order as at the time of input. Latch circuit 51
A circuit b temporarily stores the input one-dimensional data of the main scanning sequence in units of one byte, and outputs the data in the reverse order of the input. The latch circuits 52a, 52b,... Are circuits for storing and outputting data of two lines of one odd line and one even line in a proper order (in principle, alternately) in units of 1 byte.

The shift registers 53a, 53b...
The print heads 6 are arranged by the number of lines to be printed by one movement in one direction, and in the present embodiment, 56 are arranged to collectively print 56 lines. That is, in the drawing, the odd-numbered first line, the even-numbered second line, the odd-numbered third line, the even-numbered fourth line,... Therefore, the odd-numbered first line shift register 53a and the even-numbered second line shift register 53b correspond to the preceding one latch circuit 52a, and the odd-numbered third line shift register 53c and the even-numbered fourth line shift register 53d. 28 latch circuits 52a, 52b... And 56 shift registers 53a, 53b.

Also, the 56 shift registers 53a, 53
.. Represent the eight shift registers 53a, 53 from the top.
Are connected to the respective input terminals of one buffer circuit 54a at the subsequent stage, and the outputs of the next eight shift registers are connected to the next one buffer circuit at the subsequent stage (not shown).
Are connected in sequence because they are connected to the input terminal of the same.

FIG. 3 shows the configuration of the print head 6. As described in the description of the circuit of the bit conversion processing unit 5 in FIG. 2, the print head 6 according to the present embodiment prints 56 lines by one movement in one direction. . The print head 6 includes an odd line head 61 for printing only odd lines and an even line head 62 for printing only even lines in the main scanning direction.
The configuration is such that they are integrally arranged at intervals of dots. However, in the present embodiment, when the print head 6 is viewed from the front, it is assumed that the even-numbered line head 62 is located on the right side and the odd-numbered line head 61 is located on the left side. That is, when moving in the right direction (the direction of arrow R in the figure), the even-numbered line head 62 always prints ahead by 10 dots ahead of the odd-numbered line head 61.

Next, a processing operation for sub-scanning and converting one-dimensional data in a main scanning sequence using the data conversion processing device having the above configuration so as to be applicable to a print head having a structure as shown in FIG. This will be described with reference to the data configuration diagrams shown in FIGS. However, FIG. 4 shows an example of the configuration of the one-dimensional data in the main scanning arrangement stored in the first storage unit 2, and FIG.
FIG. 6 shows an example of the configuration of data in byte units rearranged in the sub-scanning direction stored in the second storage unit 4, and FIG. 6 shows an example of the configuration of data output from the bit conversion processing unit 5 to the print head 6. Is shown.

First, the one-dimensional data in the main scanning order stored in the first storage unit 2 will be described with reference to FIG. In the data configuration example shown in FIG. 4, one piece of data enclosed by a square represents one pixel (dot) representing black or white. One line of such dot data corresponds to one line of data in the main scanning direction, and is the first line, the second line,..., The 56th line from the top.

Further, each address of each line [0000]
(H) to 46DF (H)] store data for eight dots (one byte) from the first dot to the seventh dot. Each dot data has a configuration of [ABC], where A is a line number, B is a column number in byte units, and C is a bit number in the byte data.

Therefore, the A of each dot data of the first line
Stores [1] indicating the first line, and B of each of the eight dot data from the beginning of the first line contains 1
[1] indicating the byte string stores [2] indicating the second byte string in B of each of the next eight pieces of dot data. In this way, [324] indicating the 324 byte string is stored in B of the last eight pieces of dot data of the first line. In the C of each of the eight dot data from the beginning of the first line, the bit numbers in the byte data are arranged in order from the left.

[0] to [7] are provided.

Numerical values are similarly assigned to the second and subsequent lines. As a result, when each dot data is viewed vertically, the numerical value of A indicates each line. 2, 3, ..., 56. Also, since the numerical value of B indicates each column in byte units and the numerical value of C indicates the bit number in the byte data,
All have the same numerical value.

The CPU 3 performs a process of rearranging the one-dimensional data stored in the main scanning order in byte units in the sub-scanning direction in byte units as shown in FIG.
However, [*] in the data of FIG. That is, one piece of data enclosed by a square is one-byte data. At this time, as described above, the print head 6 is composed of the odd line head 61 and the even line head 62, and the even line head 62 always prints ahead by 10 dots ahead of the odd line head 61. Therefore, it is necessary to perform rearrangement in the sub-scanning direction in consideration of this. In the present embodiment, the first byte sequence and the second byte sequence of the even line are transmitted, then the data of the odd line and the even line are transmitted alternately by one byte sequence, and finally the two byte sequence of the odd line is transmitted. The rearrangement in the sub-scanning direction is performed in such a manner as to transmit data for the minute.

That is, the first line shown in FIG. 5 includes the first byte string on the second line shown in FIG. 4, the first byte string on the fourth line, the first byte string on the sixth line, and so on. As described above, the first byte string of the even-numbered lines arranged vertically is rearranged as even-line data converted horizontally. Next, on the second line shown in FIG. 5, the second byte string on the second line shown in FIG. 4, the second byte string on the fourth line, the second byte string on the sixth line, and so on. , The even number 2 obtained by converting the second byte string of the even-numbered line that is vertically arranged side by side
Sort as line data. Next, in the third line shown in FIG. 5, the first byte string in the first line shown in FIG.
The first byte string in the line, the first byte string in the fifth line,
.., Etc., the first byte string of the odd-numbered lines arranged vertically is rearranged horizontally as odd-numbered one-line data.

In this manner, the rearrangement is performed in such a manner that the even lines precede the odd lines by two bytes, and finally, the first line is the 323 byte column and the second line is the 323 byte column. .., The 323-byte column of the fifth line,.
The 23rd byte sequence is rearranged as the odd-numbered 323 line data that has been converted side by side, and further referred to as a 324 byte sequence on the first line, a 324 byte sequence on the second line, a 324 byte sequence on the 5th line, and so on. In this way, the 324 byte column of the odd-numbered lines that are vertically arranged is rearranged as odd-numbered 324-line data that is converted horizontally.

The CPU 3 stores the data rearranged in byte units in the sub-scanning direction in the second storage unit 4 and sequentially sends the stored data to the bit conversion processing unit 5. In the bit conversion processing unit 5, FIG.
The input data is the data rearranged in the sub-scanning direction in units of bytes, and a conversion process is performed to rearrange the input data in units of bits. At this time, since the print head 6 has a configuration in which the even-numbered line head 62 always prints ahead by 10 dots ahead of the odd-numbered line head 61, it is necessary to rearrange the bits in consideration of this.

That is, as shown in FIG. 7, first, data (reference numeral 71) for a 2-bit string (for 2 dots) of an even line.
), And then the data of the odd-numbered lines and the data of the even-numbered lines are alternately transmitted one bit sequence at a time.
Need to be rearranged in the sub-scanning direction in such a way as to send out. In this case, since the odd-numbered line head 61 is printed with a delay of 10 dots from the even-numbered line head 62, the even-numbered line is equivalent to a 2-bit string (2 dots).
At the time when the data of the odd line is transmitted.
1 is still 8 dots ahead of the print start position. Therefore, when transmitting the even-numbered lines from the third dot column to the tenth dot column, the odd-numbered lines transmitted during that period are the dummy data for eight dots.

It is necessary to send [0] (indicated by reference numeral 73).

Therefore, the bit conversion processing unit 5 performs the bit conversion processing as follows. That is, the even-numbered one-line data shown in FIG.
1a to 28 subsequent latch circuits 52a, 52b.
Are input in byte units, and are stored in the corresponding 28 even-numbered shift registers 53b, 53d,... From the latch circuits 52a, 52b,. Then, the shift register 53 of the even-numbered line
1 of the 8-bit data stored in b, 53d,.
Bits are assigned to corresponding buffer circuits 54a,.
4g each. At this time, the dummy data from the odd-numbered line shift registers 53a, 53c,.

[0] is transmitted.

Next, the shift register 53 of the even-numbered line
, 53d,... of the 8-bit data stored in
Bits are assigned to corresponding buffer circuits 54a,.
4g each. Also at this time, the dummy data is supplied from the odd-numbered line shift registers 53a, 53c,.

[0] is transmitted. In this way, first
The byte data is stored in the shift register 53 of the even-numbered line.
b, 53d,..., corresponding buffer circuits 54a,
, 54g and transmitted to each buffer circuit 54a,.
.., 54 g are sequentially sent to the print head.

In parallel with this, the even-numbered two-line data shown in FIG.
Are input to each of the latch circuits 52a, 52b,... In byte units, and the respective latch circuits 52a, 52b,.
Are stored in the corresponding 28 even-numbered shift registers 53b, 53d,... At appropriate timing. Then, the shift register 53 of the even-numbered line
1 of the 8-bit data stored in b, 53d,.
Bits are assigned to corresponding buffer circuits 54a,.
4g each. At this time, the dummy data from the odd-numbered line shift registers 53a, 53c,.

[0] is transmitted.

Next, the shift register 53 of the even-numbered line
, 53d,... of the 8-bit data stored in
Bits are assigned to corresponding buffer circuits 54a,.
4g each. Also at this time, the dummy data is supplied from the odd-numbered line shift registers 53a, 53c,.

[0] is transmitted. At this point, the even-numbered line head 62 prints 10 dots from the print start position (the position of t1 shown in FIG. 7), and the odd-numbered line head 61 comes to the print start position. Therefore, the subsequent data conversion processing is as follows.

That is, when even two-line data is stored in the corresponding even-line shift registers 53b, 53d,... From each of the latch circuits 52a, 52b,. The odd one-line data shown is input in bytes from the preceding latch circuit 51a to each of the subsequent 28 latch circuits 52a, 52b,..., And from each of the latch circuits 52a, 52b,.
At appropriate timing, the data is stored in the corresponding 28 odd-numbered line shift registers 53a, 53c,.
That is, at this time (time t1 shown in FIG. 7), the normal data has been stored in all the 56 shift registers 53a, 53b,.

At this time (time t1 shown in FIG. 7), the shift registers 53b, 53d,.
Since the second bit data has already been sent to the corresponding buffer circuits 54a,.
The shift registers 53b, 53d,.
When the data of the third bit (2 in numerical value) is sent to the corresponding buffer circuits 54a,..., 54g, the shift registers 53a, 53 on the odd-numbered lines
From c, the data of the first bit (0 in numerical value) is sent to the corresponding buffer circuits 54a,..., 54g. Therefore, each buffer circuit 54a,.
The bit number is assigned to each input terminal of 54g from the top (0,
2, 0, 2, 0, 2, 0, 2) 8-bit data is input.

Thus, after that, even-line data and odd-line data are shifted by 2 bits each,
Each data after the even 3-line data shown in FIG. 5 is sequentially processed. Then, the eighth bit data of the even-numbered 324 line and the sixth bit data of the odd-numbered 323 line are converted into the respective shift registers 53a, 53b,.
Are output to the corresponding buffer circuits 54a,..., 54g (at the position t2 shown in FIG. 7), and then the even-line shift registers 53b, 53d,.

[0] is transmitted for 10 dots.

In this way, the bit processing is performed by the dot conversion processing section 5, and each of the buffer circuits 54a,.
FIG. 6 summarizes data output from the printer to the print head 6.

In FIG. 6, the first byte is a buffer 54.
a, the second byte is the output data of the buffer 54b (not shown), the third byte is the output data of the buffer 54c (not shown), and the fourth byte is the output data of the buffer 54d (not shown). Is the buffer 54e
The output data (not shown), the sixth byte of which is the buffer 54
Output data of f (not shown), 7th byte is buffer 5
4 g of output data, which is one cycle of output (the first bit in a vertical line). In other words, the 8th to 14th bytes are the same for the buffer circuits 54a to 54a.
Corresponding to 54 g of output data (the second bit in the vertical line)
The next 15th to 21st bytes are the output data of the buffer circuits 54a to 54g (the third bit in the vertical direction).
It corresponds to.

Therefore, up to the output data from the 64th byte to the 70th byte (the 10th bit in the vertical line), dummy data is output to the odd line.

[0] is contained, and regular data is contained from the 71st byte (after the position of t1 shown in FIG. 7). Similarly, the output data from the 18144th byte to the 18214th byte (the last 70 bytes: after the position of t2 shown in FIG. 7) is dummy data for the output of the even-numbered line.

Contains [0].

In the above embodiment, the print head 6
Describes data processing in the case of printing in one direction (from left to right), but in the case of printing in the opposite direction (from right to left), one-dimensional data from the CPU 3 is sent to the latch circuit 51b. , And output in the reverse order of the input, so that the latch circuits 52a, 52b,.
It may be configured to input to each of. Subsequent processing is exactly the same as in the above embodiment. However, in this case, since the odd line head 61 is ahead of the even line head 62 by 10 dots, the data shown in FIG. 5 and the data shown in FIG. Is the reverse relationship, and is rearranged data.

The arrangement relationship between the odd line head 61 and the even line head 62 is not limited to that shown in FIG. 3, but may be reversed. Further, the arrangement interval between the odd-numbered line head 61 and the even-numbered line head 62 is not limited to 10 dots, and may be appropriately set according to manufacturing conditions, printing resolution, and the like.

[0034]

According to the data conversion processing apparatus of the present invention, there is provided a data conversion processing apparatus for printing and outputting a plurality of lines of one-dimensional data in a main scanning sequence read in a line in a sub-scanning direction. Processing unit for rearranging the data in the sub-scanning direction on a byte-by-byte basis by operation processing, and the data in byte units rearranged in the sub-scanning direction by the processing unit is rearranged into data in bit units using hardware means. And a bit conversion processing unit. That is, since the processing for rearranging in the sub-scanning direction on a byte-by-byte basis is performed by the arithmetic processing unit, and the bit processing is performed by the hardware means, the arithmetic processing unit uses 16 bits or 3 bits.
It is not necessary to use a high-speed multi-bit CPU such as two bits, and it is not necessary to use complicated and large-scale hardware means for sequentially reading data from a memory. Cost reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a data conversion processing device of the present invention.

FIG. 2 is a specific circuit configuration diagram of a bit conversion processing unit.

FIG. 3 is a configuration diagram of a print head.

FIG. 4 is a diagram illustrating one of main scanning arrangements stored in a first storage unit.
FIG. 4 is an explanatory diagram illustrating a configuration example of dimensional data.

FIG. 5 is an explanatory diagram showing a configuration example of byte-by-byte data rearranged in the sub-scanning direction stored in a second storage unit.

FIG. 6 is an explanatory diagram illustrating a configuration example of data output from a bit conversion processing unit to a print head.

FIG. 7 is an explanatory diagram showing output timings of even line data and odd line data.

[Explanation of symbols]

 Reference Signs List 1 data input unit 2 first storage unit 3 arithmetic processing unit (CPU) 4 second storage unit 5 bit conversion processing unit 51a, 51b latch circuit 52a, 52b latch circuit 53a, 53b shift register 54a to 54g buffer circuit

Claims (2)

[Claims] 1. A data conversion processing device for printing and outputting one-dimensional data of a main scanning sequence read for each line collectively on a plurality of lines in a sub-scanning direction. An arithmetic processing unit for rearranging the data in the scanning direction; and a bit conversion processing unit for rearranging the data in byte units rearranged in the sub-scanning direction by the arithmetic processing unit into data in bit units using hardware means. A data conversion processing device, characterized in that: 2. The data conversion processing device according to claim 1, wherein said hardware means comprises a latch circuit, a shift register, and a buffer circuit.