JP2000164806A - Intermediate potential generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a circuit, when an intermediate potential generating circuit capable of obtaining a stable output potential is constituted on the same semiconductor substrate by using MOS transistors of one conductivity type. SOLUTION: An intermediate potential generating circuit is constituted of an intermediate potential generating part 1, which consists of N-channel MOS transistors 3, 4, and an output part 2 which consists of N-channel MOS transistors 6, 7. An output voltage outputted from an output terminal 8 is applied to the gate of the transistor 4, so that the change of an output voltage which is caused by noise superposed on the output terminal 8 can be restrained. Since this intermediate potential generating circuit is constituted of only the same conductivity-type N-channel MOS transistors, there is no need for an element isolation region to be formed, when the transistors are formed on the same semiconductor substrate, and the circuit scale can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an intermediate potential generating circuit for generating and outputting a reference voltage from a power supply voltage.

[0002]

2. Description of the Related Art In a semiconductor circuit device, an input buffer is provided for temporarily receiving an external input signal and supplying the signal inside the semiconductor circuit. Then, the potential of the input signal is compared with the reference voltage, and the result of the comparison is input to the semiconductor circuit device by a GTL (Gunning Transceive).
r Logic), HSTL (High SpeedT)
transceiver Logic), SSTL (St
ub SeriesTerminated Logi
A high-speed interface buffer such as c) is used as this input buffer. As a reference voltage used by such an input buffer, an intermediate potential generated by an intermediate potential generating circuit is used.

A conventional intermediate potential generating circuit as described in Japanese Patent Application Laid-Open No. 9-246472 will be described with reference to FIG.

This conventional intermediate potential generating circuit is composed of an intermediate potential generating section 71 and an output section 72, as shown in FIG.

The intermediate potential generating section 71 is composed of P-channel MOS transistors 61 and 63 operating as resistance elements, and N-channel MOS transistors 62 and 64 operating as diodes. Then, the intermediate electron generation unit 71 supplies the intermediate terminal 69 with the intermediate potential VDD / 2 + V
Output _thn . Here, VDD is a power supply voltage, and V _t
hn is the threshold voltage of the N-channel MOS transistor 62.

The output unit 72 includes a P-channel MOS transistor 66 and an N-channel MOS transistor 6.
5, 68.

The N-channel MOS transistor 68 charges the output terminal 67 to VDD / 2 based on the intermediate potential inputted via the intermediate terminal 69. P channel MOS
Transistor 66 and N-channel MOS transistor 6
5 discharges a predetermined current from the output terminal 67. Generally, it is difficult to reduce the threshold voltage V _thnp of a P-channel MOS transistor.
Since the conventional intermediate potential generating circuit does not include a diode formed of a P-channel MOS transistor, it is easy to reduce the power supply voltage VDD.

However, since one reference voltage is supplied to a plurality of input buffers, the reference voltage is routed in the chip, and noise of other signals is picked up by the influence of adjacent wiring.

In addition, with the recent miniaturization and large scale, the above problem has become more serious, and in the worst case, a malfunction has occurred, which has been a problem.

Conventionally, no consideration has been given to this type of noise. For example, as shown in FIG. 7, the noise on the output terminal 67 becomes a fluctuation of the output potential as it is.

In this conventional intermediate potential generating circuit, there is a problem that the output potential fluctuates when noise is superimposed on the output terminal due to the influence of an adjacent wiring or the like.

Japanese Patent Application Laid-Open No. 8-171432 discloses an intermediate potential generating circuit which solves such a problem and reduces the influence of noise superimposed on the output terminal to obtain a stable output potential.

FIG. 8 shows a conventional intermediate potential generating circuit disclosed in Japanese Patent Application Laid-Open No. 8-171432.

This conventional intermediate potential generating circuit includes an intermediate potential generating section 81 and an output section 89.

The intermediate potential generator 81 includes P-channel MOS transistors 82 and 84 and N-channel MOS transistors 83 and 85.

In this conventional intermediate potential generating circuit, the output voltage output from output terminal 88 is applied to the gate of P-channel MOS transistor 82 and the gate of N-channel MOS transistor 85.
Even when noise is superimposed on 8, it is possible to prevent a change in output potential. However, when configuring the intermediate potential generating circuit, a P channel MOS transistor and an N channel
A MOS transistor of both conductivity types of the S transistor is required. When MOS transistors of different conductivity types are formed on the same semiconductor substrate, an element isolation region must be provided, which increases the circuit scale.

[0017]

In the above-mentioned conventional intermediate potential generating circuit, a P-channel MOS transistor and an N-channel MOS transistor are used.
Since a MOS transistor of both conductivity types of the channel MOS transistor is required, there is a problem that the circuit scale is increased.

An object of the present invention is to reduce the circuit scale when the intermediate potential generating circuit for obtaining a stable output potential is formed on one and the same semiconductor substrate by using one conductive type MOS transistor. .

[0019]

To achieve the above object, an intermediate potential generating circuit according to the present invention comprises a first MOS transistor having a drain and a gate connected to a power supply voltage and a source connected to an intermediate terminal. And the drain is the first MO.
A second MOS transistor having a source connected to the source, a source connected to the ground, and a gate connected to the output terminal; and a drain connected to the power supply voltage, A third N-channel MOS transistor having a gate connected to the intermediate terminal, a source connected to the output terminal, a drain connected to the output terminal, a gate connected to the intermediate terminal, and a source connected to ground An intermediate potential generating circuit having an output section composed of a fourth MOS transistor and a fourth MOS transistor, wherein the first to fourth MOS transistors are all of the same conductivity type.

According to the present invention, the output potential output from the output terminal is fed back to the intermediate potential generating section, so that the output terminal can obtain a stable output potential while suppressing the influence of the potential fluctuation received from the adjacent wiring or the like. Since the intermediate potential generating circuit is configured only by MOS transistors of the same conductivity type, the circuit scale when configured on the same semiconductor substrate can be reduced.

Further, another intermediate potential generating circuit of the present invention comprises:
A first MOS transistor having a drain and a gate connected to a power supply voltage and a source connected to an intermediate terminal; and a first MOS transistor having a drain and a source connected to each other in series to be connected in series. The drain is the first
Of a plurality of second transistors connected in series to each other and connected in series to each other, the source of the tongue is connected to ground, and the gate is connected to the output terminal.
A third N-channel MOS transistor whose drain is connected to the power supply voltage, whose gate is connected to the intermediate terminal, and whose source is connected to the output terminal; A fourth MOS transistor having a drain connected to the output terminal, a gate connected to the intermediate terminal, and a source connected to ground; To the fourth MOS transistors are all of the same conductivity type.

[0022]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a configuration of an intermediate potential generating circuit according to a first embodiment of the present invention.

The intermediate potential generating circuit of the present embodiment comprises an intermediate potential generating section 1 and an output section 2. The intermediate potential generating section 1 includes an N-channel MOS transistor 3,
4.

The N-channel MOS transistor 3 has a drain and a gate connected to the power supply voltage VDD, and a source connected to the intermediate terminal 5.

The N-channel MOS transistor 4 has a drain connected to the intermediate terminal 5, a source connected to the ground, and a gate connected to the output terminal 8.

The output section 2 includes N-channel MOS transistors 6 and 7.

The N-channel MOS transistor 6 has a drain connected to the power supply voltage, a gate connected to the intermediate terminal 5, and a source connected to the output terminal 8.

The N-channel MOS transistor 7 has a drain connected to the output terminal 8, a gate connected to the intermediate terminal 5, and a source connected to the ground.

Further, the back gates of the N-channel MOS transistors 3, 4, 6, 7 are all connected to the ground.

Next, the operation of the intermediate potential generating circuit of the present embodiment will be described in detail with reference to the drawings.

When VDD is turned on, an N-channel MOS
The output terminal 8 is precharged by the transistor 6 to the potential of VDD−threshold voltage V _tn , and the potential becomes N
The signal is transmitted to the gate of the channel MOS transistor 4.
Therefore, N-channel MOS transistor 4 is turned on, and VDD is divided by N-channel MOS transistor 3 and N-channel MOS transistor 3 to generate a voltage at intermediate terminal 5. By the voltage generated at the intermediate terminal 5, N
The channel MOS transistors 6 and 7 are turned on, and the voltage of the output terminal 8 is determined.

Next, the operation of the intermediate potential generating circuit according to the present embodiment in the case where a potential variation is applied from the outside to the output terminal 8 under the influence of adjacent wirings will be observed using the test circuit shown in FIG. The intermediate potential generation circuit 10 in FIG. 2 is the intermediate potential generation circuit of the present embodiment shown in FIG. Also, FIG.
FIG. 4 shows the results of observation by the test circuit of FIG. 2, and FIG.
FIG. 3 is a diagram showing an enlarged view of FIG.

As shown in FIG. 2, the output from the oscillator 50 is applied to the output terminal 8 of the intermediate potential generating circuit 10 via the capacitor 51. A capacitor 52 is provided between the output terminal 8 and the ground. Here, the voltage waveform applied from the oscillator 50 to the output terminal 8 is 1 V
_{This is a PP} signal.

While the output potential of the oscillator 50 rises, the potential of the output terminal 8 rises, and the potential of the intermediate terminal 5 drops. According to FIG. 4, the amount of decrease in the potential of the intermediate terminal 5 is 0.05 V
It is about. For this reason, the gate voltage V _gs of the N-channel MOS transistors 6 and 7 is reduced, and the driving capability is reduced. At this time, since the output potential 8 has also risen, the N-channel MOS
N-channel MOS transistor 6 rather than transistor 7
The variation width of the gate voltage V _gs is larger in the case of (1), and the variation in the potential of the output terminal 8 is suppressed. The fluctuation range at this time is 30 at the maximum.
It is about mV.

When the output potential of the oscillator 50 shown in FIG. 2 falls, the operation is reversed.

By this operation, the variation of the output signal with respect to the signal coupled to the output terminal is smaller than that of the conventional intermediate potential generating circuit.

The intermediate potential generating circuit of this embodiment is constituted by N-channel MOS transistors 3, 4, 6, and 7 of the same conductivity type. Therefore, when the intermediate potential generation circuit of the present embodiment is formed on one semiconductor substrate, it is not necessary to form an element isolation region, and therefore, the circuit scale can be reduced as compared with the conventional intermediate potential generation circuit. Can be.

(Second Embodiment) Next, an intermediate potential generation circuit according to a second embodiment of the present invention will be described.

FIG. 5 is a circuit diagram showing a configuration of an intermediate potential generating circuit according to a second embodiment of the present invention.

The intermediate potential generating circuit of the present embodiment is obtained by replacing the intermediate potential generating section 1 with an intermediate potential generating section 11 in the intermediate potential generating circuit of the first embodiment shown in FIG.

The intermediate potential generating section 11 is
However, N channel MOS transistor 4 is replaced with N channel MOS transistors 14 and 19.

This shows that the number of stages to which the N-channel MOS transistor is connected may be any value as long as the circuit can obtain a desired potential at the intermediate terminal 5.

(Third Embodiment) Next, an intermediate potential generating circuit according to a third embodiment of the present invention will be described.

FIG. 6 is a circuit diagram showing a configuration of an intermediate potential generating circuit according to a third embodiment of the present invention.

The intermediate potential generating circuit of this embodiment is different from the intermediate potential generating circuit of the first embodiment shown in FIG. 1 in that the MOS transistors constituting the circuit are changed from N-channel MOS transistors to P-channel MOS transistors. It has been replaced.

The intermediate potential generating circuit according to the present embodiment includes an intermediate potential generating section 21 and an output section 22.

The intermediate potential generator 21 is composed of P-channel MOS transistors 23 and 24.

The N-channel MOS transistor 23 has a drain and a gate connected to the intermediate terminal 5, and a source connected to the power supply voltage VDD. The N-channel MOS transistor 24 has a source connected to the intermediate terminal 5, a drain connected to the ground, and a gate connected to the output terminal 8.

The output section 22 includes N-channel MOS transistors 26 and 27.

The N-channel MOS transistor 26 has a source connected to the power supply voltage, a gate connected to the intermediate terminal 5, and a drain connected to the output terminal 8. The N-channel MOS transistor 27 has a source connected to the output terminal 8, a gate connected to the intermediate terminal 5, and a drain connected to the ground.

Further, P-channel MOS transistor 2
The back gates 3, 24, 26 and 27 are all connected to ground.

The operation of the intermediate potential generation circuit of the present embodiment is the same as the operation of the intermediate potential generation circuit of the first embodiment shown in FIG. 1, and a description thereof will be omitted.

The intermediate potential generating circuit according to the present embodiment is a P-channel MOS transistor 2 of the same conductivity type.
3, 24, 26, and 27. Therefore, when the intermediate potential generation circuit of the present embodiment is formed on one semiconductor substrate, it is not necessary to form an element isolation region, and therefore, the circuit scale can be reduced as compared with the conventional intermediate potential generation circuit. Can be.

This indicates that the intermediate potential generating circuit of the present invention can be configured regardless of the conductivity type of the transistor.

As in the relationship between the first embodiment and the second embodiment, the P-channel M
The number of stages of the OS transistor 24 can be changed.

Further, in the intermediate potential generating circuits of the first to third embodiments, various circuits for cutting off the steady current when not used can be added. Specifically, in the first embodiment shown in FIG. 1, a switching circuit is provided between VDD and the drain and gate of the N-channel MOS transistor 3, and a switching circuit is provided between VDD and the drain of the N-channel MOS transistor 6. When not in use, these switching circuits are cut off to prevent a steady current from flowing.

[0058]

As described above, according to the present invention, the output potential is fed back to the intermediate potential generating section, thereby suppressing the influence of the potential fluctuation which the output terminal receives from the adjacent wiring or the like and obtaining a stable output potential. The intermediate potential generating circuit can be configured only by MOS transistors of the same conductivity type, and has an effect that the circuit scale can be reduced when configured on the same semiconductor substrate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an intermediate potential generating circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a test circuit for observing an operation when a potential change is externally applied to an output terminal 8 of an intermediate potential generating circuit 10 of FIG. 1;

FIG. 3 is a diagram showing an observation result by the test circuit of FIG. 2;

4 is a diagram showing an enlarged view of FIG. 3 together with an output of an oscillator 50.

FIG. 5 is a circuit diagram showing a configuration of an intermediate potential generation circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an intermediate potential generating circuit according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a conventional intermediate potential generation circuit.

FIG. 8 is a circuit diagram showing a configuration of another conventional intermediate potential generating circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Intermediate potential generation part 2 Output part 3, 4 N channel MOS transistor 5 Intermediate terminal 6, 7 N channel MOS transistor 8 Output terminal 10 Intermediate potential generation circuit 11 Intermediate potential generation part 14 N channel MOS transistor 19 N channel MOS transistor 21 Intermediate Potential generator 22 Output unit 23, 24 P-channel MOS transistor 26, 27 P-channel MOS transistor 50 Oscillator 51, 52 Capacitor 61 P-channel MOS transistor 62 N-channel MOS transistor 63 P-channel MOS transistor 64, 65 N-channel MOS transistor 66 P Channel MOS transistor 67 Output terminal 68 N-channel MOS transistor 69 Intermediate terminal 71 Intermediate potential generating section 72 Output section 81 Intermediate potential generating section 82 P-channel MOS transistor 83 N-channel MOS transistor 84 P-channel MOS transistor 85, 86 N-channel MOS transistor 87 P-channel MOS transistor 88 Output terminal 89 Output section

Claims (6)

[Claims] 1. A first MOS transistor having a drain and a gate connected to a power supply voltage, a source connected to an intermediate terminal, a drain connected to a source of the first MOS transistor, and a source connected to ground. An intermediate potential generating section comprising a second MOS transistor having a gate connected to the output terminal; a drain connected to the power supply voltage; a gate connected to the intermediate terminal; and a source connected to the output terminal. And a fourth N-channel MOS transistor having a drain connected to the output terminal, a gate connected to the intermediate terminal, and a source connected to ground. , The first to fourth MOS transistors are all of the same conductivity type. Intermediate potential generating circuit according to claim. 2. The semiconductor device according to claim 1, wherein the first to fourth MOS transistors are all N-channel MOS transistors.
An intermediate potential generating circuit as described in the above. 3. The first to fourth MOS transistors are all P-channel MOS transistors.
An intermediate potential generating circuit as described in the above. 4. A first MOS transistor having a drain and a gate connected to a power supply voltage and a source connected to an intermediate terminal, and a drain and a source connected to each other in series and connected in series. The drain of the end in the case is connected to the source of the first MOS transistor, the source of the head in the case of series connection is connected to the ground, and the gates are connected to the output terminals, respectively. A third N-channel MOS transistor having a drain connected to the power supply voltage, a gate connected to the intermediate terminal, and a source connected to the output terminal; A fourth MOS transistor having a drain connected to the output terminal, a gate connected to the intermediate terminal, and a source connected to ground. In the intermediate potential generation circuit having an output section is composed of a static, intermediate potential generating circuit, characterized in that from the first is a 4 MOS transistor are all the same conductivity type of. 5. The semiconductor device according to claim 4, wherein the first to fourth MOS transistors are all N-channel MOS transistors.
An intermediate potential generating circuit as described in the above. 6. The first to fourth MOS transistors are all P-channel MOS transistors.
An intermediate potential generating circuit as described in the above.