JPH0983334A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the normal operation of an IC(integrated circuit) which receives the supply of two types of power voltage from the outside regardless of the application sequence of both power supplies. SOLUTION: A semiconductor IC receives the supply of the 1st and 2nd power voltage VC1 and VC2 and operates between these two power voltage and the reference voltage VSS. Then the IC outputs the 1st internal power voltage in response to the first one of both supplied voltage VC1 and VC2 and then outputs the 2nd internal power voltage in response to the second supplied power voltage when this power voltage is higher than the first one. If the second supplied power voltage is lower than the first one, a voltage switching circuit 7 maintains the output state of the 1st internal power voltage. Then the internal power voltage outputted from the circuit 7 is supplied to a substrate bias circuit 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit (IC), and more particularly to an IC to which two kinds of power supply voltages are supplied from the outside, and is used for an IC memory, for example.

[0002]

2. Description of the Related Art Conventionally, a plurality of I's are printed on a printed circuit board.
In a system in which C is mounted, the power supply voltage supplied to some ICs may be different from the power supply voltage supplied to other ICs. FIG. 6 shows an example of an IC devised so as to cope with such a case and normally transmit data between ICs having different power supply voltages.

In the IC shown in FIG. 6, 1 is a signal input terminal, 2 is an input circuit, 3 is an internal circuit, 4 is an output circuit, and 5 is a signal output terminal. In this IC, the power supply system of the input circuit 2 and the output circuit 4 and the power supply system of the internal circuit 3 are separated. In this case, the input circuit 2 and the output circuit 4 are
As the operating power supply of,
The first power supply voltage VC1 used in another IC supplied with data from this IC is supplied. As the operating power supply for the internal circuit 3, the optimum second power supply voltage VC2 is supplied to the internal circuit 3.

By the way, which of the two power supply voltages VC1 and VC2 is first applied to the IC having the two power supply systems as described above depends on the user who configures the system. When the power-on sequence of the two power supply systems is uncertain, the following inconveniences occur depending on the power-on sequence.

For example, in a CMOS type IC, a P type semiconductor substrate region in which an N channel MOS transistor is usually formed by generating a negative voltage lower than a reference potential when a power supply voltage is applied is usually used. A substrate voltage generating circuit for supplying a bias voltage to the substrate, or an N-type semiconductor substrate region in which a P-channel MOS transistor is formed by generating a positive voltage higher than the power supply voltage when the power supply voltage is applied. And a substrate voltage generating circuit for supplying a bias voltage to the substrate.

CM having such a substrate voltage generating circuit
When the OS type IC has the two power supply systems as described above, if the substrate voltage generating circuit is supplied with only the power supply voltage of one of the two power supply systems (for example, the second power supply voltage VC2), When the first power supply voltage VC1 is first applied to the CMOS type IC, the substrate voltage generating circuit does not operate at this point, so that the semiconductor substrate region is electrically floating without being supplied with the bias voltage. It will be in a state. As a result, a latch-up phenomenon occurs in the CMOS type IC, which may lead to the destruction of the IC.

[0007]

As described above, the conventional IC to which two kinds of power supply voltages are externally supplied has a problem that a latch-up phenomenon or the like may occur depending on the order of turning on the two power supplies. there were.

The present invention has been made to solve the above problems, and when two kinds of power supply voltages are externally supplied, the semiconductor integrated circuit can operate normally regardless of the order of turning on the two power supplies. The purpose is to provide.

[0009]

According to a first aspect of the invention, a first power supply voltage and a second power supply voltage are supplied, and the device operates between the first power supply voltage and the second power supply voltage and a reference voltage. In the semiconductor integrated circuit, the first internal power supply voltage is output in response to the power supply voltage supplied first among the first power supply voltage and the second power supply voltage, and the second internal power supply voltage is supplied second. If the power supply voltage is higher than the power supply voltage supplied first, the second internal power supply voltage is output in response to the power supply voltage supplied second, and the second internal power supply voltage is supplied. When the generated power supply voltage is lower than the first supplied power supply voltage, the voltage switching circuit that maintains the output state of the first internal power supply voltage and the internal power supply voltage output from the voltage switching circuit are And a circuit to be supplied. To.

A second invention is the first power supply voltage and the second power supply voltage.
Of the first power supply voltage and the second power supply voltage which are supplied in a predetermined order and operate between the first power supply voltage and the second power supply voltage and a reference voltage.
Output a first internal power supply voltage in response to the first supplied power supply voltage, and a second internal power supply voltage in response to the second supplied power supply voltage. And a circuit to which the internal power supply voltage output from the voltage switching circuit is supplied.

A third invention is directed to a first power supply voltage and a second power supply voltage.
Of the first power supply voltage and the second power supply voltage.
In a semiconductor integrated circuit operating between the power supply voltage and the reference voltage, the first integrated circuit responds to the first power supply voltage when both the first power supply voltage and the second power supply voltage are supplied.
Of the first power supply voltage and the second power supply voltage, the first power supply voltage is output in response to the first power supply voltage. Output the internal power supply voltage, and when the second power supply voltage is supplied thereafter, the output state of the first internal power supply voltage is maintained, and the first power supply voltage and the second power supply voltage When the second power supply voltage is first supplied, the second internal power supply voltage is output in response to the second power supply voltage, and then the first power supply voltage is supplied. Further includes a voltage switching circuit that outputs the first internal power supply voltage, and a circuit to which the internal power supply voltage output from the voltage switching circuit is supplied.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a circuit block of a CMOS type IC according to the first embodiment of the present invention.

In the IC shown in FIG. 1, 1 is a signal input terminal, 2 is an input circuit, 3 is an internal circuit, 4 is an output circuit, 5 is a signal output terminal, 6 is a substrate voltage generating circuit (substrate bias circuit), and 7 is a circuit. Is a voltage switching circuit.

The IC is supplied with the first power supply voltage VC1 and the second power supply voltage VC2, and operates between the above-mentioned VC1 and VC2 and the reference voltage VSS. In this case, the first power supply voltage VC1 is supplied to the input circuit 2 and the output circuit 4 as the optimum operating power supply. Further, the second power supply voltage VC2 is supplied to the internal circuit 3 as an optimum operating power supply.

The substrate bias circuit 6 is supplied with the internal power supply voltage output from the voltage output node 10 of the voltage switching circuit 7 to generate a negative voltage lower than the reference potential VSS and form it as an NMOS transistor. A negative voltage generating circuit (not shown) for supplying a bias voltage to the P-type substrate region for use, and the internal power supply voltage is also supplied to the first power supply voltage VC1 and the second power supply voltage VC2. Generate a high positive voltage and drive it to PMO
A positive voltage generating circuit (not shown) is supplied to the N-type substrate region for forming the S transistor (P-channel MOS transistor) as a bias voltage.

The voltage switching circuit 7 outputs the first internal power supply voltage in response to the first power supply voltage of the first power supply voltage VC1 and the second power supply voltage VC2, When the second supplied power supply voltage is higher than the first supplied power supply voltage, a second internal power supply voltage is output in response to the second supplied power supply voltage, It is configured to maintain the output state of the first internal power supply voltage when the second supplied power supply voltage is lower than the first supplied power supply voltage.

A specific example of the voltage switching circuit 7 is a first node 11 to which a first power supply voltage VC1 is applied.
A first NMOS transistor (N-channel MOS transistor) N1 whose gate and drain are connected to each other and whose source is connected to the voltage output node 10, and a second power supply voltage V
The gate and drain are connected to the second node 12 to which C2 is applied, and the source and the second NMOS transistor N2 are connected to the voltage output node 10.

Next, the operation of the voltage switching circuit in FIG. 1 will be described. Here, the gate threshold voltage of the NMOS transistor is represented by Vth. Further, it is assumed that the supply order of the power supply voltage to the IC is indefinite.

First, for example, when VC1 is supplied as the first power supply sequence, VC1 is applied to the first node 11. At this time, the first NMOS transistor N1 is turned on, and the first internal power supply voltage (VC1
-Vth) is output.

Next, VC2 is set as the second power supply sequence.
Is supplied to the second node 12, VC2 is supplied. At this time, if VC1 <VC2, the second NMOS transistor N2 is turned on and the second internal power supply voltage (VC2-Vth) is output to the voltage output node 10, but if VC1> VC2, the second NMOS transistor N2 is output. The transistor N2 is not turned on, and the voltage output node 10 maintains the state in which the first internal power supply voltage (VC1-Vth) is output.

In other words, during normal operation when both VC1 and VC2 are supplied to the IC, if VC1 <VC2, then VC2-Vth is output to the voltage output node 10, and if VC1> VC2, then to the voltage output node 10. VC1-Vth is output.

Therefore, the internal power supply voltage output from the voltage output node 10 of the voltage switching circuit 7 is (VC1-Vt).
If the substrate bias circuit 6 is configured to operate regardless of either h) or (VC2-Vth), the operation starts regardless of the order in which the two power supply voltages VC1 and VC2 are applied. The substrate region of the IC does not electrically float, there is no risk of a latch-up phenomenon in the CMOS IC, and the IC operates normally.

In the voltage switching circuit 7, the power supply voltage is supplied to the IC in the order of VC1 and VC2, and
Assuming that VC1 <VC2, the operation will be described below.

That is, first, VC1 is applied to the first node 11, the first NMOS transistor N1 is turned on, and V1
In response to C1, the first internal power supply voltage (VC1-Vth) is output to voltage output node 10. Next, VC2 is applied to the second node 12, the second NMOS transistor N2 is turned on, and in response to VC2, the second internal power supply voltage (VC2-Vt
h) is output to the voltage output node 10.

Further, the voltage switching circuit 7 has VC1,
Assuming that the relation of the level of VC2 is VC1> VC2, and the supply order of the power supply voltage to the IC is indefinite,
It operates as described below.

That is, when VC1 is first applied to the first node 11, the first internal power supply voltage (VC1-Vth) is output to the voltage output node 10 in response to VC1, and then the second node When VC2 is applied to the node 12, the voltage output node 10 maintains the state in which the first internal power supply voltage (VC1-Vth) is output.

On the other hand, when VC2 is first applied to the second node 12, the second internal power supply voltage (VC2-Vth) is output to the voltage output node 10 in response to VC2,
After that, when VC1 is applied to the first node 11, the first internal power supply voltage (VC1-Vth) is output to the voltage output node 10 in response to VC1.

FIG. 2 shows the circuit configuration of the voltage switching circuit 7a according to the second embodiment of the present invention and the connection between the voltage switching circuit 7a and the substrate bias circuit 6. Here, the substrate bias circuit 6 is designed to operate optimally when the second power supply voltage VC2 is supplied.

The voltage switching circuit 7a shown in FIG. 2 includes a first PMOS transistor P1 having a source / substrate region connected to a first node 11 to which a first power supply voltage VC1 is applied, and the first PMOS transistor P1. A source is connected to the drain of the PMOS transistor P1, a drain / substrate region is connected to the voltage output node 10, and a gate is connected to the gate of the first PMOS transistor P1. A third PMOS transistor P3 having a source / substrate region connected to the second node 12 to which the power supply voltage VC2 is applied, and a source connected to the drain of the third PMOS transistor P3 having the drain / substrate region described above. A fourth PM connected to the voltage output node 10 and having a gate connected to the gate of the third PMOS transistor P3. It has an OS transistor P4.

Further, the voltage switching circuit 7a includes a fifth PMOS transistor P5 having a source / substrate region connected to the second node 12, and the fifth PMOS transistor P5.
The source is connected to the drain of the transistor P5, and the drain / substrate region is the first PMOS transistor P1.
And a sixth PMOS transistor P6 connected to the gate interconnection point of the second PMOS transistor P2,
A third NMOS transistor N having a drain connected to the drain (node O2) of the sixth PMOS transistor P6 and a source / substrate region connected to the reference potential VSS.
And 3.

Further, the voltage switching circuit 7a includes a seventh PMOS transistor P7 whose source / substrate region is connected to the first node 11 and the seventh PMOS.
The source is connected to the drain of the transistor P7, and the drain / substrate region is the fifth PMOS transistor P.
5, the sixth PMOS transistor P6 and the third NM
An eighth PMOS transistor P8 connected to the gate interconnection point of the OS transistor N3 and also connected to the gate interconnection points of the third PMOS transistor P3 and the fourth PMOS transistor P4;
Drain of the PMOS transistor P8 (node O1)
The drain is connected to the source and the substrate region is the reference potential V
The gate of the seventh PMOS transistor P7 is connected to SS and the gate of the seventh PMOS transistor P7 and the eighth PMOS transistor P8.
Is commonly connected to the gates of the first PMO and
A fourth NMOS transistor N4 connected to the gate interconnection point of the S transistor P1 and the second PMOS transistor P2, and the fourth NMOS transistor N
The drain of the fourth NMOS transistor N5 has a drain connected to it, a source / substrate region thereof is connected to the reference potential VSS, and a gate thereof is connected to the second node 12.

In FIG. 3, the power supply voltage is supplied to the IC having the voltage switching circuit 7a shown in FIG.
And the potentials of VC1 and VC2 are waveform diagrams showing the operation of the voltage switching circuit 7a when VC1 has a larger voltage value than VC2 in the steady state.

In FIG. 4, the power supply voltage is supplied to the IC incorporating the voltage switching circuit 7a shown in FIG. 2 in the order of VC2 and VC1.
And the potentials of VC1 and VC2 are waveform diagrams showing the operation of the voltage switching circuit 7a when VC1 has a larger voltage value than VC2 in the steady state.

Next, the operation of the voltage switching circuit in FIG. 2 will be described in detail with reference to FIG. First, the first
When VC1 is applied to the node 11 of, the first internal power supply voltage VC1 is output to the voltage output node 10 in response to VC1,
Next, when VC2 is applied to the second node 12, the second internal power supply voltage VC2 is applied to the voltage output node 10 in response to VC2.
Output to

That is, at time t1, VC1 is turned on and the level of VC1 rises. At this time, VC2 has not been turned on and is 0V. At this time, the sixth PMO
The drain (node O2) of the S transistor P6 is at 0V.

Next, at time t2 when the level of VC1 becomes higher than the absolute value of the threshold voltage of the PMOS transistor.
Then, the seventh PMOS transistor P7 and the eighth PM
The OS transistor P8 is turned on, and the drain (node O1) of the eighth PMOS transistor P8 rises as the level of VC1 rises. At this time, the node O
The third PMOS transistor P3, whose gate is connected to 1, remains off.

On the other hand, at the time t2, the first PMOS transistor P1 and the second PMOS transistor P2 whose gates are connected to the node O2 which is 0V as described above are turned on.

As a result, the voltage output node 10 responds to an increase in the level of VC1 of the first node 11 connected through the first PMOS transistor P1 and the second PMOS transistor P2 which are in the ON state. V
Ascends to C1.

Next, at time t3, VC2 is turned on, and the level of VC2 rises. The above VC2 level is the fifth NM
When it becomes higher than the threshold voltage of the OS transistor N5,
Fifth NMOS in which the level of VC2 is applied to the gate
The transistor N5 is turned on, and the drain (node O1) of the eighth PMOS transistor P8 is discharged to 0V.

Then, the third PMOS transistor P3 to the sixth PM whose gates are connected to the node O1 are connected.
The OS transistors P6 are turned on, the third NMOS transistor N3 whose gate is also connected to the node O1 is turned off, and the sixth PMOS transistor P6 is turned on.
Since the drain (node O2) of 6 is charged to VC2, the first PMOS transistor P1 is turned off.

As a result, the voltage output node 10 raises the level of VC2 of the second node 12 connected through the third PMOS transistor P3 and the fourth PMOS transistor P4 which are turned on as described above. Is set to VC2 accordingly.

Next, the operation of the voltage switching circuit in FIG. 2 will be described with reference to FIG. 4 when the power supply voltage is supplied in the order of VC2 and VC1. First, the second node 12
When VC2 is applied to the voltage output node 10, the second internal power supply voltage VC2 is output to the voltage output node 10 in response to VC2, and even if VC1 is applied to the first node 11, The state in which the second internal power supply voltage VC2 is output is maintained.

That is, at time t4, VC2 is turned on and the level of VC2 rises. At this time, VC1 has not been applied yet and is 0V. At this time, the drain (node O1) of the eighth PMOS transistor P8 is at 0V.

Next, at time t5 when the level of VC2 becomes higher than the absolute value of the threshold voltage of the PMOS transistor.
And a fifth PMOS transistor P5 and a sixth PM
The OS transistor P6 is turned on, and the drain (node O2) of the sixth PMOS transistor P6 rises as the level of VC2 rises. At this time, the first PMOS transistor P whose gate is connected to the node O2 is
1 remains off. At the time t5, the fifth NMOS transistor N5 having the gate to which the level of VC2 is applied is turned on, and the node O1 is maintained at 0V.

On the other hand, at the time t5, the third PMOS transistor P3 and the fourth PMOS transistor P4 whose gates are connected to the node O1 which is 0V as described above are turned on.

As a result, the voltage output node 10 responds to an increase in the level of VC2 of the second node 12 connected through the third PMOS transistor P3 and the fourth PMOS transistor P4 which are in the ON state. V
Ascends to C2.

Next, at time t6, VC1 is turned on and the level of VC1 rises. However, even if the level of VC1 rises, the seventh PMOS transistor P7 whose gate is connected to the node O2, which rises in accordance with the rise of the level of VC2 as described above, remains off. ,
The node O1 maintains 0V.

Therefore, the third PMOS transistor P3 and the fourth PMOS transistor P4, whose gates are connected to the node O1, maintain the ON state, and the first PMOS transistor whose gate is connected to the node O2. P1 remains off.

As a result, the voltage output node 10 has the third PMOS transistor P3 in the ON state as described above.
And continues to output VC2 of the second node 12 connected through the fourth PMOS transistor P4.

In the second embodiment of the present invention as described above, during the normal operation in which both VC1 and VC2 are supplied to the IC, the substrate bias circuit 6 supplies optimum VC2 as the power supply voltage. To be done. When either VC1 or VC2 is supplied to the IC, the supplied voltage is supplied as the power supply voltage of the substrate bias circuit 6.

Therefore, by supplying either one of VC1 or VC2 to the IC, the substrate bias circuit 6 always operates so that the substrate region of the IC is not electrically floating and the CMOS IC The IC operates normally without the risk of the latch-up phenomenon in FIG.

FIG. 5 shows the circuit configuration of the voltage switching circuit 7b according to the third embodiment of the present invention and the connection between the voltage switching circuit 7b and the substrate bias circuit 6. Here, the substrate bias circuit 6 is designed to operate with the power supply voltage that is turned on first. That is, the voltage switching circuit 7b is configured to continue to output the power supply voltage that is turned on first.

The voltage switching circuit 7b shown in FIG. 5 has a node O compared to the voltage switching circuit 7a shown in FIG.
The first voltage conversion circuit 51 is inserted in place of the circuit portion from 2 to the node O1, and the second voltage conversion circuit 52 is further inserted between the node O1 and the gates of the PMOS transistors P1 and P2. Since the points are different and the others are the same, the same reference numerals as those in FIG. 2 are given.

The first voltage conversion circuit 51 is for converting the input voltage of the VC2 system to the output voltage of the VC1 system and supplying it to the gates of the PMOS transistors P3 and P4, and has a normal configuration. can do. That is, the first voltage conversion circuit 51 has an NMOS transistor N11 whose one end is connected to the input node O2 and whose gate is supplied with VC1, and an NMOS transistor N1 whose one end is connected to the input node O2 and whose gate is supplied with VC2. N12
And the drains are connected to the other ends of the NMOS transistors N11 and N12, and VC1 is applied to the source,
A PMOS transistor P11 having a gate connected to the node O1, a gate connected to the drain of the PMOS transistor P11, and a source supplied with VC1
The MOS transistor P12, the PMOS transistor P12 and the gate are connected to each other, and the drain is the PM
N, which is connected to the node O1 together with the drain of the OS transistor P12 and whose source is supplied with the reference potential VSS.
It is composed of a MOS transistor N13.

The second voltage conversion circuit 52 is for converting the input voltage of the VC1 system to the output voltage of the VC2 system and supplying it to the gates of the PMOS transistors P1 and P2, and has a normal configuration. can do. That is, the second voltage conversion circuit 52 has an NMOS transistor N15 whose one end is connected to the input node O1 and whose gate is supplied with VC1, and an NMOS transistor N1 whose one end is connected to the input node O1 and whose gate is supplied with VC2. N16
And the drains are connected to the other ends of the NMOS transistors N15 and N16, and VC2 is applied to the source,
A PMOS transistor P13 having a gate connected to the gates of the PMOS transistors P1 and P2;
A PMOS transistor P whose gate is connected to the drain of OS transistor P13 and whose source is given VC2
14, the PMOS transistor P14 and the gate are connected to each other, and the drain is the PMOS transistor P1.
4 together with the drain of the PMOS transistor P1,
It is composed of an NMOS transistor N17 which is connected to the gate of P2 and whose source is supplied with the reference potential VSS.

Although each of the above-described embodiments shows an example in which the present invention is applied to the switching of the power supply of the substrate bias circuit 6, the present invention is not limited to this, and another internal circuit (for example, a memory IC) is used.
It goes without saying that the present invention can be applied to the power supply switching of the address buffer circuit).

[0057]

As described above, according to the present invention, an IC to which two kinds of power supply voltages are externally supplied can be operated normally regardless of the order of turning on the two power supplies.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a timing waveform chart showing an operation example of the voltage switching circuit in FIG.

FIG. 4 is a timing waveform chart showing another operation example of the voltage switching circuit in FIG.

FIG. 5 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 ... Signal input terminal, 2 ... Input circuit, 3 ... Internal circuit, 4 ...
Output circuit, 5 ... Signal output terminal, 6 ... Substrate voltage generating circuit (substrate bias circuit), 7, 7a ... Voltage switching circuit,
10 ..., voltage output node, 11 ... first node, 12 ...
Second node, N1 to N5 ... NMOS transistor, P
1 to P8 ... PMOS transistors.

Claims (6)

[Claims] 1. A first circuit to which a first power supply voltage is supplied, a second circuit to which a second power supply voltage is supplied, and one of the first power supply voltage and the second power supply voltage. First
The first internal power supply voltage is output in response to the second supplied power supply voltage, and the second supplied power supply voltage is the first internal power supply voltage.
If the voltage is higher than the second supplied power supply voltage, the second
The second internal power supply voltage is output in response to the second supplied power supply voltage, and when the second supplied power supply voltage is lower than the first supplied power supply voltage, the first internal power supply voltage is output. 1. A semiconductor integrated circuit comprising: a voltage switching circuit that maintains the output state of the internal power supply voltage 1; and a third circuit to which the internal power supply voltage output from the voltage switching circuit is supplied. 2. A first circuit to which a first power supply voltage is supplied, a second circuit to which a second power supply voltage is supplied, and the first power supply voltage and the second power supply voltage. First
A voltage switching circuit that outputs a first internal power supply voltage in response to a second supplied power supply voltage, and outputs a second internal power supply voltage in response to a second supplied power supply voltage; A third circuit to which an internal power supply voltage output from the switching circuit is supplied. 3. A first circuit supplied with a first power supply voltage, a second circuit supplied with a second power supply voltage, and both the first power supply voltage and the second power supply voltage. When supplied, the first internal power supply voltage is output in response to the first power supply voltage, and the first power supply voltage is first supplied from among the first power supply voltage and the second power supply voltage. In this case, the first internal power supply voltage is output in response to the first power supply voltage, and when the second power supply voltage is subsequently supplied, the output state of the first internal power supply voltage is maintained. However, when the second power supply voltage is first supplied from the first power supply voltage and the second power supply voltage, the second internal power supply voltage is output in response to the second power supply voltage. However, when the first power supply voltage is supplied thereafter, the first internal power supply voltage is output. Pressure switching circuit and a semiconductor integrated circuit internal power supply voltage is characterized by comprising a third circuit which is supplied to the output from the voltage switching circuit. 4. A first circuit supplied with a first power supply voltage, a second circuit supplied with a second power supply voltage, and a first node to which the first power supply voltage is applied. A first NMOS transistor having a gate and drain connected to it and a source connected to the voltage output node, and a gate and drain connected to a second node to which a second power supply voltage is applied and having a source connected to the voltage output node. A semiconductor integrated circuit comprising: a second NMOS transistor connected to the second output circuit; and a third circuit to which a power supply voltage output from the voltage output node is supplied. 5. A first circuit supplied with a first power supply voltage, a second circuit supplied with a second power supply voltage, and a first node to which the first power supply voltage is applied. A first PMOS transistor having a source / substrate region connected thereto, a source connected to the drain of the first PMOS transistor, a drain / substrate region connected to a voltage output node, and a gate connected to the first PMOS transistor. A second PMOS transistor connected to the gate, a third PMOS transistor whose source / substrate region is connected to a second node to which the second power supply voltage VC2 is applied, and a drain of the third PMOS transistor A source connected to the drain, a drain / substrate region connected to the voltage output node, and a gate connected to the gate of the third PMOS transistor. A PMOS transistor, a fifth said source substrate region to the second node is connected
Source is connected to the drains of the PMOS transistor and the fifth PMOS transistor, and the drain / substrate region has the third PMOS transistor and the fourth P-type transistor.
A sixth PMOS transistor connected to a gate interconnection point of the MOS transistor; a first NMOS transistor having a drain connected to the drain of the sixth PMOS transistor and a source / substrate region connected to a reference potential; A seventh embodiment in which a source / substrate region is connected to the first node
Source is connected to the drain of the seventh PMOS transistor and the drain / substrate region is connected to the gate interconnection point of the fifth PMOS transistor, the sixth PMOS transistor and the first NMOS transistor. And an eighth PMOS transistor connected to the gate interconnection point of the third PMOS transistor and the fourth PMOS transistor, a drain connected to the drain of the eighth PMOS transistor, and a source / substrate region as a reference. Connected to the electric potential,
A second NMOS whose gate is commonly connected to the gates of the seventh PMOS transistor and the eighth PMOS transistor and to the gate interconnection point of the first PMOS transistor and the second PMOS transistor A transistor, a drain of the second NMOS transistor is connected to the drain, and a source / substrate region is connected to a reference potential,
A third NMOS whose gate is connected to the second node
A semiconductor integrated circuit comprising a transistor and a third circuit to which a power supply voltage output from the voltage output node is supplied. 6. The semiconductor integrated circuit according to claim 1, wherein the third circuit is a substrate voltage generation circuit for supplying a substrate potential of the semiconductor integrated circuit. Semiconductor integrated circuit.