JP2000156507A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily obtain a MOS transistor with a plurality of threshold voltages on the same substrate by providing a region where a P-type impurity is ion-implanted and a region where an N-type impurity is ion-implanted on the same gate electrode. SOLUTION: A P-type impurity is ion-implanted into a channel region 3, and an N-type impurity region and a P-type impurity region are provided at a gate electrode 6 at the side of a source region 4 and at a gate electrode at the side of a drain region 5 by ion implantation. By changing the area of the N-type impurity region and P-type impurity region of the gate electrodes 6 and 7, the threshold voltage of a MOS transistor can be changed. By increasing the surface ratio of the gate electrode 7 of the P-type impurity region, a threshold voltage becomes higher than a normal MOS transistor where the gate electrode 6 of the N-type impurity region is the gate electrode on the entire surface, thus approaching the threshold voltage of the MOS transistor where the P-type impurity is ion-implanted onto the entire surface of the gate electrode as the surface area of the gate electrode 7 of the P-type impurity region becomes larger.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an N-type MOS transistor and a P-type MOS transistor having a plurality of threshold voltages on an SOI wafer having a semiconductor film formed on a supporting substrate via an insulating film. The present invention relates to a required semiconductor device. In particular, the present invention provides
The present invention relates to forming an electrostatic protection transistor that requires a reduction in leakage current.

[0002]

2. Description of the Related Art FIG. 4 shows a plan view and a sectional view of a conventional MOS transistor. A source region 4, a drain region 5, a channel region 34 between the source region 4 and the drain region 5 formed on the semiconductor substrate 33, and a gate oxide film 13 and a gate electrode 3 formed on the channel region 34.
Consists of zero.

Here, when forming a MOS transistor aiming at low voltage operation, the conductivity type of the ions of the gate electrode 30 and the conductivity type of the ions implanted into the source / drain regions 4 and 5 are the same. Often do. That is, in the case of a MOS transistor in which N-type ions are implanted into the source region 4 and the drain region 4, the gate electrode 30 also has the N-type conductivity.

In order to control the threshold voltage of a MOS transistor in a semiconductor device, a channel region 3
The ion implantation concentration of P-type or N-type is changed. Therefore, in a conventional semiconductor device,
In a semiconductor device aiming for low-voltage operation, the internal M
The threshold voltage of the OS transistor is set low. However, if an electrostatic protection transistor is formed at the same threshold voltage, the leakage current increases,
The threshold voltage of the electrostatic protection transistor has been increased by increasing the ion implantation concentration in the channel region to increase the threshold voltage and reduce the leakage.

[0005]

In a conventional semiconductor device using a MOS transistor, only one type of threshold voltage MOS transistor can be obtained in one ion implantation step into a channel region. Therefore, in a semiconductor device having a plurality of threshold voltage MOS transistors on the same substrate, the mask is changed according to the type of the threshold voltage and the ion implantation process is performed. Was higher.

In particular, in a semiconductor device aiming at low-voltage operation, if an electrostatic protection transistor is formed with the same threshold voltage as the threshold voltage of an internal MOS transistor, the leakage current increases, so Although only the threshold voltage of the protection transistor is set high, this increases the number of masks and increases the manufacturing cost. An object of the present invention is to eliminate the above problems.

[0007]

The present invention employs the following means in order to achieve the above object. A MOS transistor comprising a source region, a drain region, a channel region between a source and a drain, a gate oxide film and a gate electrode formed on the channel region, on a semiconductor film formed on a supporting substrate via an insulating film. In the above structure, a region where a P-type impurity is ion-implanted and a region where an N-type impurity is ion-implanted are provided on the same gate electrode. Thus, MOS transistors having a plurality of threshold voltages can be easily obtained on the same substrate.

Furthermore, in a semiconductor device intended for low-voltage operation, only the threshold voltage of the electrostatic protection transistor can be set high, so that the leakage current of the electrostatic protection transistor does not have to be considered. In addition, the channel region has a structure in which N-type impurities and P-type impurities are ion-implanted in parallel and alternately with the source region and the drain region. This makes it possible to arbitrarily control the threshold voltage of the MOS transistor. Further, not only can transistors with a plurality of threshold voltages be easily obtained on the same substrate, but also the sub-threshold region of the MOS transistor can be obtained. Can rise steeply.

[0009]

Embodiments of the present invention will be described below. Although all of the embodiments described herein are limited to the N-channel MOS transistor, the P-channel MOS transistor is described in the embodiment when the types of ion-implanted impurities described in the embodiment are reversed. The same effect can be obtained.

(Embodiment 1) FIG. 1 is a plan view and a sectional view showing a MOS transistor according to a first embodiment of the present invention. The MOS transistor includes gate electrodes 6 and 7, a gate oxide film 13, a source region 4, a drain region 5, and a channel region 3. Further, the connection between the source region 4 and the drain region 5 is performed by metal wirings 11 and 12 via contacts 10, and the connection between the gate electrodes 6 and 7 is performed by metal wiring via gate electrode contacts 8 and 9. .

Here, a P-type impurity is ion-implanted in the channel region 3, an N-type impurity region is formed in the gate electrode 6 on the source region 4 side, and a P-type impurity region is formed in the gate electrode 7 on the drain region 5 side. It is provided by ion implantation. By changing the areas of the N-type impurity region and the P-type impurity region of the gate electrodes 6 and 7, the threshold voltage of the MOS transistor can be changed. When an N-type impurity is ion-implanted on the entire surface of the gate electrode, the threshold voltage is reduced. On the other hand, when a P-type impurity is ion-implanted on the entire surface of the gate electrode,
It is already known that the threshold voltage increases. In the MOS transistor according to the present invention, as shown in FIG. 1, if the area ratio of the gate electrode 7 in the P-type impurity region is increased, the gate electrode 6 in the N-type impurity region is larger than the conventional MOS transistor having the entire gate electrode. As the threshold voltage increases and the area ratio of the gate electrode 7 in the P-type impurity region increases, the threshold voltage approaches the threshold voltage of a MOS transistor in which P-type impurities are ion-implanted over the entire gate electrode.

In the present invention, the method of forming the gate electrode 6 of the N-type impurity region and the gate electrode 7 of the P-type impurity region is as follows. After forming LOCOS 14,
A gate oxide film 13 is formed, and polysilicon is formed thereon. Next, ion implantation is performed separately on the portion of the gate electrode 6 in the N-type impurity region and the portion of the gate electrode 7 in the P-type impurity region. Next, silicide is formed on the polysilicon, and the silicide and the polysilicon are etched to form gate electrodes 6 and 7. Then, ions are implanted into the source region 6 and the drain region 7 to form source / drain regions. Next, an interlayer insulating film is formed, holes are formed in the portions of the gate electrode contacts 8, 9 and the contacts 10 by etching, and a metal is formed thereon and patterned to form metal wirings 11, 12, and 15, Connect. Here, while the ion implantation of the source / drain regions 4 and 5 is an N-type impurity, the gate electrode 7 is a P-type impurity region. May be implanted. However, according to the manufacturing method of the present invention, since the silicide is formed on the polysilicon after the polysilicon is implanted into the gate electrodes 6 and 7, the gate is not implanted during the ion implantation of the source / drain regions 4 and 5. N-type impurities are not implanted into the electrode 7.

Next, the operation of the electrostatic protection transistor using the MOS transistor of the present invention will be described with reference to FIG. In the electrostatic protection transistor of the present invention connected to the pad 16 of the semiconductor device, the metal wiring 12 of the drain region 5 is connected to the pad 16 and the internal circuit of the semiconductor device, and the metal wiring 15 of the gate electrodes 6 and 7 is connected to the source region. 4 is connected to the metal wiring 11 of the source region 4.
Is connected to the ground terminal. Static electricity that has entered the pad 16 of the semiconductor device enters the drain region 5 of the electrostatic protection transistor. Here, the gate oxide film 13 and the drain region 4
Surface breakdown occurs at a voltage determined by the shape and the like.
Then, the charge flows to the channel region 3. next,
As the charges flow toward the channel region 3, a voltage drop occurs, and the potential of the channel region 3 increases. Then, the bipolar operation between the drain region 5, the channel region 3 and the source region 4 is turned on, and the drain region 5
The electricity flows toward and discharges the static electricity.

Here, the gate electrode 7 on the drain region 5 side
Has a high threshold voltage because of the P-type impurity region. Therefore, leakage current when the transistor is off is smaller than that of a transistor whose gate electrode is entirely an N-type impurity region. Therefore, an internal circuit using a transistor with a low threshold voltage and an electrostatic protection transistor with reduced leakage current can be realized over the same substrate by a method for manufacturing a CMOS transistor.

Further, a P-type impurity region is provided in the gate electrode 6 on the source region 4 side and an N-type impurity region is provided in the gate electrode 7 on the drain region 5 side by ion implantation. The leak current is further suppressed as compared with the implanted MOS transistor. (Embodiment 2) FIG. 3 is a plan view and a sectional view showing a MOS transistor according to a second embodiment of the present invention. An N-type impurity region I on the gate electrode 20 on the source region 4 side, an N-type impurity region II on the gate electrode 22 on the drain region 5 side,
A P-type impurity region is provided in the central gate electrode 21 in the channel length direction by ion implantation. Further, the channel regions 23, 24, 25 are provided with a P-type impurity channel region 23 below the gate electrode 20 and N-type impurity channel regions 24, 25 below the gate electrodes 21, 22. When the voltage applied to the gate electrodes 20, 21, and 22 is increased, first, the gate electrode 22, which is the N-type impurity region II, reaches the threshold voltage. When the voltage is further increased, N
The gate electrode 20, which is the type impurity region I, reaches the threshold voltage. Finally, the gate electrode 21, which is a P-type impurity region, reaches the threshold voltage. Therefore, in the MOS transistor according to the present invention, the effective channel length is short, and the length of the gate electrode 21 is the effective channel length. Therefore, when compared with the conventional MOS transistor at the same size and the same threshold voltage, the rise of the sub-threshold region becomes steep as the effective channel length is shorter.

Further, as another embodiment according to the present invention,
A P-type impurity region I is formed on the gate electrode 20 on the source region 4 side.
A P-type impurity region I is formed on the gate electrode 25 on the drain region 5 side.
I, an N-type impurity region is provided in the central gate electrode 21 in the channel length direction by ion implantation. Further, in the channel regions 23, 24, and 25, N-type impurity channel regions 24 and 25 are provided below the gate electrodes 21 and 22, and a P-type impurity channel region 23 is provided below the gate electrode 20. As a result, when the voltage applied to the gate electrodes 20, 21, and 22 is increased, the gate electrode 21 first reaches the threshold voltage, and when the voltage is further increased, the P-type impurity region II
Gate electrode 22 reaches the threshold voltage. Finally, the gate electrode 20, which is the P-type impurity region I, reaches the threshold voltage. Therefore, the MOS transistor according to the present invention has a short effective channel length,
Is the effective channel length. Therefore, the conventional M
Comparing the OS transistor with the same size and the same threshold voltage, the sub-threshold region rises steeply due to the short effective channel length, and the P-type impurity channel region 23 of the channel region causes the sub-threshold region to enter the channel region. Since the supply of electrons is suppressed, the leakage current can be reduced.

[0017]

As described above, according to the present invention, the following effects can be obtained. A MOS transistor comprising a source region, a drain region, a channel region between a source and a drain, and a gate oxide film and a gate electrode formed on the channel region on a semiconductor film formed on a supporting substrate via an insulating film. In the above structure, a region where a P-type impurity is ion-implanted and a region where an N-type impurity is ion-implanted are provided on the same gate electrode. Thus, MOS transistors having a plurality of threshold voltages can be easily obtained on the same substrate.

Further, if the P-type impurity region and the N-type impurity region on the gate electrode are provided alternately in parallel with the source region and the drain region, the threshold voltage of the MOS transistor can be easily controlled. Further, in a semiconductor device aiming at low-voltage operation, only the threshold voltage of the electrostatic protection transistor can be set high, so that the leakage current of the electrostatic protection transistor does not have to be considered.

The channel region has a structure in which an N-type impurity channel region and a P-type impurity channel region are ion-implanted in parallel with and alternately with the source region and the drain region. This makes it possible to arbitrarily control the threshold voltage of the MOS transistor. Further, not only can transistors with a plurality of threshold voltages be easily obtained on the same substrate, but also the current of the sub-threshold region can be controlled. The rise can be steep.

[0020]

[Brief description of the drawings]

[0021]

1A and 1B are a plan view and a cross-sectional view illustrating the structure of a MOS transistor according to the present invention.

[0022]

FIG. 2 is a connection diagram of an electrostatic protection transistor according to the present invention.

[0023]

3A and 3B are a plan view and a cross-sectional view illustrating a structure according to a second embodiment of the present invention.

[0024]

4A and 4B are a plan view and a cross-sectional view illustrating a structure of a conventional MOS transistor.

[0025]

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Support substrate 2 Insulating film on a support substrate 3, 23, 24, 25, 34 Channel region 4 Source region 5 Drain region 6, 7, 20, 21, 22, 30 Gate electrode 8, 9, 26, 27, 28, DESCRIPTION OF SYMBOLS 31 Gate electrode contact 10 Contact 11, 12, 15, 32 Metal wiring 13 Gate oxide film 14 LOCOS 16 Pad 33 Semiconductor substrate

Claims (4)

[Claims] A semiconductor film formed on a supporting substrate via an insulating film; a source region, a drain region, and a channel region between source and drain formed on the semiconductor film; A semiconductor device comprising: a formed gate oxide film and a gate electrode; and a region formed on the same gate electrode and implanted with a P-type impurity and an ion implanted with an N-type impurity. . 2. The semiconductor device according to claim 1, wherein the region into which the P-type impurity is ion-implanted and the region into which the N-type impurity is ion-implanted are alternately introduced in parallel to the source region and the drain region. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein an N-type impurity and a P-type impurity are introduced into said channel region by ion implantation. 4. The semiconductor device according to claim 1, wherein an N-type impurity and a P-type impurity are introduced into said channel region in parallel with and alternately with said source region and said drain region by ion implantation. Semiconductor device.