JP2000152187A - Synchronization detector, its method and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely obtain synchronization even on the occurrence of an error of a synchronization pattern on the way of a sector. SOLUTION: In the case that no synchronization is detected, an inertia circuit 18 generates a synchronization pulse based on synchronization detection information fed from a SYNC RAM 17. An output control circuit 20 outputs data of a delay line 19 based on the synchronization pulse and counts the number of times of the synchronization pulses. When the count reached a prescribed number or over, a Fab-SYNC is outputted. When receiving both the Fab-SYNC and a pulse at synchronization detection, a phase control circuit 16 generates a write address of the synchronization detection information to a SYNC RAM 17 so that the synchronization detection information is written in an address of the SYNC RAM 17 where the inertia circuit 18 generates the synchronization pulse in tracing forward by a prescribed amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a data block for detecting a synchronization pattern from a data block reproduced from a recording medium by returning to a portion where the synchronization pattern has not been detected for a predetermined period or more. The present invention relates to a synchronization detection device and method for specifying the phase of a signal, and a playback device.

[0002]

2. Description of the Related Art In recent years, digital video tape recorders, which use a magnetic tape as a recording medium and record and reproduce digital video signals and digital audio signals, are becoming widespread.

In such an apparatus, digital video data and digital audio data are stored in units of packets of a predetermined length, and each packet has a synchronization pattern for detecting synchronization, a block ID for identifying each packet, and a data. The sync block is configured by adding an ID representing the contents of the above and a parity for error correction.
Then, the sync blocks are grouped into sectors according to the type of data, and are recorded on the magnetic tape as serial data in sector units. Recording is performed by a helical scan method in which tracks are formed diagonally on a magnetic tape by a rotating head.

At the time of recording, the length of each sync block in the same sector is made the same, and
IDs in which D is continuous and represent data contents have the same value.

FIG. 23 schematically shows an example of the arrangement of each sector on a track. The rotating head traces from the left side to the right side of the figure to form a track. As described above, the track is actually formed obliquely with respect to the magnetic tape, and one frame of video data is recorded using a plurality of, for example, four tracks. A plurality of audio sectors for recording audio data are arranged between video sectors for recording video data. In this example, C
Since audio signals for eight channels from h1 to Ch8 can be handled, eight audio sectors A1 to A8 are arranged.

[0006] Between each sector, an edit gap (E) in which audio data is not recorded is inserted so that, for example, insert editing can be performed in sector units of an audio signal.
G) is arranged. A preamble is provided at the beginning of the track. In the preamble, a signal that makes it easy for the PLL for the reproduction clock to lock during reproduction, for example, data of “FF (hexadecimal notation)” is repeatedly recorded. Further, the shortest recording wavelength on the recording medium depends on the data amount for one track.

At the time of reproduction, tracks on the magnetic tape are traced by the rotating head, and a reproduction signal is obtained.
The edge of the signal in the preamble portion of the reproduced signal is detected, and the PLL for the reproduced clock is locked using the edge interval. Then, from the reproduced signal, a sync pattern is detected from the reproduced bit string synchronized with the reproduced clock by the sync detection circuit, and the head position of each sync block is detected. Then, the packets in the detected sync block are rearranged according to the block ID number and the data content ID, and the original data sequence is decoded. That is, by utilizing the fact that the bit sequence and appearance period of the synchronization pattern at the head of the sync block and that the block ID number is continuous and the ID indicating the data content is the same within the same sector, the phase of the sync block is changed. Specified.

For example, the same pattern is detected at a position where the bit string of the synchronization pattern matches the unique pattern and is delayed by the sync block length.
If the number is correct, the phase of the sync block is specified.

Here, consider a case where an error has occurred in the data string when decoding the data string. Here, it is assumed that the bit intervals of the data string are always the same, and only a random error is added. In this case, the bit interval between the synchronization patterns is always the same within the same sector. Therefore, if the synchronization can be detected at the beginning of the sector, the flywheel processing is performed based on the block length, and then the beginning of the subsequent synchronization block is obtained. The phase can be specified. Therefore, in this case, it is sufficient that the synchronization detection probability at the head position of the sector is sufficiently ensured.

[0010] The flywheel process is a process for continuously generating a synchronizing signal at a previously detected cycle, and is realized by an inertia circuit.

In this example, the synchronization detection is performed with reference to the data input point and the point delayed by the block length. Therefore, in order to perform the synchronization detection at the head of the sector, two bits are detected at the head of the sector. It is necessary to detect the synchronization pattern continuously. FIG. 24 shows an example in which two consecutive synchronization patterns cannot be detected at the beginning of a sector. FIG. 24A is an example in which there are four consecutive errors at the head of a sector. 24B-2
4E is an example in which three out of the first four sectors have an error. FIGS. 24F to 24H are examples in which two out of the first four sectors have an error and two consecutive ones are not detected.

On the other hand, in FIG. 24I, up to three out of four heads of a sector are detected, but two heads are not detected continuously. In this case, it is possible to detect the synchronization by returning the synchronization pattern back from the latter two synchronization patterns that are continuously detected.

Here, consider the probability that a synchronization pattern cannot be detected. The probability is: byte error occurrence probability: Pbytes Synchronization pattern 4 byte error probability: Ps = 1- (1-Pbytes) ⁴ ... (1) Synchronization pattern detection error probability: Pse = Ps ⁴ + 4 × Ps ³ × (1-Ps) + 3 × Ps ² × (1-Ps) ² + Ps × (1-Ps) ³ (2) It is obtained as described above.

For example, a non-interlaced (progressive) scan having 480 effective scanning lines and a video rate of 9
In the case of 0 Mbps, the frequency of occurrence of the head of the sector is 3596 times / s. Error frequency due to synchronization pattern error
When Tbytes is set to Pbytes = 1 × 10 ⁻³ , Tse = 14.3 times / s based on the above equations (1) and (2).

Next, in the case shown in FIG. 24I described above, an example in which synchronization is detected retroactively will be considered.
That is, since the synchronization patterns at the positions 3 and 4 can be detected, the positions of the synchronization patterns 1 and 3
It can be calculated by going back from the position. The probability that the synchronization pattern cannot be detected in the case of performing this forward processing is as follows: Pse = Ps ⁴ +4 × Ps × (1-Ps) ³ +3 × Ps ² × (1-Ps) ⁴ (3) ) It can be calculated by equation (3). If Pbytes = 1 × 10 ^-3 , Tse = 0.175 times / s. That is, by performing the forward return processing, the synchronization detection ability is dramatically improved.

FIG. 25 shows an example of a configuration of a synchronization detecting circuit adapted to perform a backward process according to the conventional technique.
This circuit corresponds to a sync block whose data length is L. The input data supplied from the terminal 300 is supplied to the shift register 301 corresponding to the data length L and to one input terminal of the comparison circuit 303.
The other input terminal of the comparison circuit 303 is supplied with the input data delayed by the shift register 301. The data string output from the shift register 301 is delayed by 6 L via the delay line 307, and
8 is supplied.

FIG. 26 schematically shows an example of input data read from the head of a sector. “×” is data having an error in the synchronization pattern. “○” is data having no error in the synchronization pattern. In terms of time, data 1 is newer and data a is oldest. Here, it is assumed that data a is the head of a sector. For example, in the delay line 307, data a is stored in the fourth L, and data b, data c,
Data d is stored. Data e is stored in the shift register 301. The data f has arrived at the input terminal 300. The input data is also supplied to the sync comparison circuit 302 and is latched internally. Then, the latched input data is compared with a synchronization pattern consisting of 8 bits at each bit position. As a comparison result, a detection result of the synchronization pattern and a bit shift amount indicating at which bit position the pattern matches are supplied to the comparison circuit 303. The comparison circuit 303 detects a sync block from the data strings supplied to one and the other input terminals based on the detection result. Based on the detection result, the sync detection circuit 304 determines the validity of the sync block and specifies the phase of the sync block, as described above, based on the block ID number and the data content ID stored in the sync block.

The sync detection circuit 304 compares the ID information (ID number) stored in the sync block containing the detected synchronization pattern with the ID number of the first sync block of the sector, which is known in advance as a system function. Based on this, the relative position of the sector to the head sync block (data a) is calculated. At this time, in this example, the data e in the shift register 301 and the delay line 3
Calculation of the relative position is performed based on the leading data d of 07.

The relative position information is supplied to the phase control circuit 305. For the relative phase information, a write address is calculated by the phase control circuit 305, and is written to the sink RAM 306 having a length of (6L + K). A start signal for starting the inertia circuit 309 and synchronization pattern detection information are also written into the address.

The information supplied and written from the phase control circuit 305 moves in the sync RAM 306 in accordance with the movement of the data in the delay line 307, and moves to the position L from the rear end of the sync RAM 306. When you come,
It is supplied to the inertia circuit 309. As a result, a synchronization pulse is output from the inertia circuit 309. The synchronization pulse is led out to the terminal 310 and the variable shifter 30
8 is supplied.

In the variable shifter 308, the sync RAM 30
6 and the inertia circuit 30
The data a output from the delay line 307 is phase-shifted based on the synchronization pulse supplied from No. 9 and synchronized with the synchronization pulse to be output to the output terminal 311 as a sync block. The sync block at the head of the sector is output in synchronization with the synchronization pulse.

[0022]

In the configuration shown in FIG. 25, various signals are formed by the sync detection circuit 304 based on information that is known in advance as the ID of the head of the sector, and only the return processing at the head of the sector is performed. Is performed. For this reason, there is a problem that the backward processing cannot be performed when the synchronization pattern cannot be detected in the middle of the sector, such as data h to data j shown in FIG. 25, for example.

For example, in a reproducing apparatus that performs non-tracking reproduction, one track is traced by a plurality of reproducing heads.
The signal is reproduced from the middle of the track. At this time, it is necessary to detect the synchronization pattern from the middle of the sector and operate the inertia circuit. However, as described above, in the conventional method, when a specific number in a sector is detected, the rewind process is performed. Therefore, the rewind process cannot be performed on data from the middle of the sector. There was no problem.

Further, conventionally, only one type of sync block length can be simultaneously supported, and there is a problem that it cannot be used in a recording format having a plurality of different sync block lengths.

Therefore, an object of the present invention is to be able to reliably obtain synchronization even if a synchronization pattern error occurs in the middle of a sector, and to cope with a recording format in which a plurality of different sync block lengths are mixed. An object of the present invention is to provide an apparatus and method for detecting synchronization which can be performed, and a reproducing apparatus.

[0026]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a synchronization detecting apparatus for detecting a synchronization from a bit string input with a synchronization pattern for detecting synchronization added for each data length. A synchronization pattern of the input data is detected by detecting a synchronization pattern of the input data, and synchronization detection information including information indicating that synchronization has been detected and data length information based on the detected synchronization interval is created. A synchronization detecting means, a first memory means for sequentially storing a plurality of input data as data blocks corresponding to synchronization, and a first memory means for storing synchronization detection information by the synchronization detecting means and having a length corresponding to the first memory means. When the synchronization is not detected by the memory means of the second and the synchronization detecting means, the second
A synchronization signal generating means for generating a synchronization signal corresponding to the data length based on the position of the synchronization detection information written in the memory means and the data length information of the synchronization detection information; Count the number of times
When the count value is equal to or more than the predetermined value and the synchronization is detected by the synchronization detecting means, the second memory means is detected at a position which is moved back by a predetermined length from the position at which the synchronization is detected. And phase control means for controlling to write synchronization detection information accompanying the synchronization.

According to the present invention, there is provided a reproducing apparatus for detecting synchronization from a bit string reproduced from a recording medium to which a synchronization pattern for detecting synchronization is added for each data length. Synchronization detection means for detecting the synchronization of the reproduced data, generating synchronization detection information comprising information indicating that the synchronization has been detected and data length information based on the detected synchronization interval, and synchronizing the reproduced data. First memory means for storing a plurality of data blocks in order as corresponding data blocks, second memory means for storing synchronization detection information by the synchronization detection means and having a length corresponding to the first memory means; If the synchronization is not detected, the data length corresponds to the position of the synchronization detection information written in the second memory means and the data length information of the synchronization detection information. A synchronization signal generating means for generating a that synchronization signal, counts the number of times the synchronizing signal is generated by the synchronizing signal generating means, the count value becomes a predetermined value or more,
When the synchronization is detected by the synchronization detection means, the synchronization detection information associated with the detected synchronization is written to the second memory means at a position which is returned by a predetermined length from the position at which the synchronization is detected. Phase control means for controlling
An output control means for outputting a data block stored in the first memory means based on the synchronization signal generated by the synchronization signal generation means or the synchronization detected by the synchronization detection means. .

According to another aspect of the present invention, there is provided a synchronization detecting method for detecting a synchronization from an input bit string to which a synchronization pattern for detecting synchronization is added for each data length. A synchronization detection step of generating synchronization detection information including information indicating that synchronization has been detected and data length information based on the detected synchronization interval, and input data corresponding to the synchronization. Storing a plurality of data blocks in the first memory in order, storing the synchronization detection information in the second memory having a length corresponding to the first memory, and detecting the synchronization; If the synchronization is not detected in step (2), the data is determined based on the position of the synchronization detection information written in the second memory and the data length information of the synchronization detection information. A synchronization signal generation step for generating a synchronization signal corresponding to the data length, and counting the number of times a synchronization signal has been generated by the synchronization signal generation step. When the synchronization is detected, the phase control of the second memory is performed such that the synchronization detection information accompanying the detected synchronization is written to a position which is returned by a predetermined length from the position where the synchronization is detected. And a synchronization detecting method.

As described above, according to the present invention, a plurality of input data are sequentially stored in the first memory as data blocks corresponding to synchronization, and the synchronization detecting means detects a synchronization pattern of the input data and synchronizes the input data. And generates synchronization detection information including information indicating that synchronization has been detected and data length information based on the detected synchronization interval. The synchronization detection information by the synchronization detecting means is stored in a second memory having a length corresponding to the first memory. The synchronization signal generation means generates a synchronization signal corresponding to the data length based on the position of the synchronization detection information written in the second memory and the data length information of the synchronization detection information when the synchronization is not detected. The number of times the synchronization signal is generated by the synchronization signal generation means is counted, and when the count value becomes equal to or greater than a predetermined value and the synchronization is detected by the synchronization detection means, the second phase control means stores the data in the second memory means. On the other hand, control is performed so that synchronization detection information associated with the detected synchronization is written at a position that is returned by a predetermined length from the position where the synchronization is detected. Therefore, the synchronizing signal generation means generates a synchronizing signal by returning to a position where no synchronization is detected.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

In this embodiment, a video signal is compression-encoded based on the MPEG2 system, and an audio signal is handled uncompressed. As is well known, MPEG2 is
This is a combination of motion compensation predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer from the lowest level.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I-picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock predicting the future from the past, and backward (Backward) interframe prediction macroblock predicting the future from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP contains at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern aligned in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration on the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

The video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX except when necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection circuit 132 via the reproduction amplifier 131. For the playback signal,
Equalization and waveform shaping are performed. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, and the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of the shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is secured in accordance with the maximum length of the macroblock, as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to the AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this embodiment, recording of a signal on a magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is constituted by two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged at both ends, and an audio sector in which audio data is recorded is interposed between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since data for one field is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data of two ECC blocks (including the outer code parity) is divided into four sectors, and as shown in FIG. 3, the data is dispersedly recorded on four tracks. Two ECCs
A plurality of sync blocks included in the block are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, the video data is shuffled (interleaved) for four ECC blocks for one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks. However, depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, the data recorded on the tape is composed of a plurality of equally spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction, more specifically. In this embodiment, one or two macroblocks of data (VLC data) are stored for one sync block according to the format of video data to be recorded, and the size of one sync block is reduced. The length is changed according to the format of the video signal to be handled. As shown in FIG. 5A, one sync block is
From the beginning, a 2-byte SYNC pattern, a 2-byte I
D, a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). Note that the data area is also called a payload.

The first two bytes of the SYNC pattern are used for synchronization detection and have a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, length information LT indicating the length of the following macroblock is arranged in the first three bytes.
The length information LT may or may not include its own length. 5C shown in FIG.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.
The length information LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT describes the length of the video AUX data. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, the length of the payload, which is the data storage area of each sync block, is not set equal to each other because the video sync block and the audio sync block are optimally set. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

In the stream converter 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

In the stream converter 106, the variable-length coded and arranged DCT coefficients are once decoded by decoding the variable-length code to detect a break of each coefficient, and the frequency is spread over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows packing processing of a macroblock in packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 9A, the lengths of the eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing and shuffling unit 107. A SYNC pattern, ID, and DID are added to each row of the VLC data, and a parity of an inner code is added to form one SYNC block.

That is, a 10-byte parity of the outer code is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID, and VLC data (or outer) are aligned in the horizontal direction. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the lengths of VLC data in one SYNC block are different at 59.94 Hz, 25 Hz, 23.
This is because the frame frequency of video data is different, such as 976 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz.
And one sample is quantized to 16 bits. One sample may be converted into another bit number, for example, 24 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of even-numbered and odd-numbered audio samples and audio AUX as data.

Next, the synchronization detecting circuit 132 described above with reference to FIG. 2 will be described in more detail. FIG.
1 shows an example of the configuration of a synchronization detection circuit 132 according to the present invention. The synchronization detection circuit 132 can automatically detect sync blocks having different data lengths, and can perform a backward process even if a synchronization pattern error occurs in the middle of a sector. This is the gist of the present invention.

In the following, the synchronization detection circuit 132
Then, 2 such that [L> K] and [2K> L]
It is assumed that sync blocks having different data lengths L and K are detected. The data lengths L and K correspond to L and K clocks of a clock of a predetermined frequency.

When the bit serial input data is input to terminal 1
Is entered for This input data is supplied to a shift register L10, a shift register K11, a comparison (L) circuit 12
, One input terminal of a comparison (K) 13 circuit, and a sink comparison circuit 14.

Shift register L10 and shift register K11 have bit lengths corresponding to data lengths L and K, respectively. The output of the shift register L10 is 6L
A delay line 19 having a delay of one minute and the other input terminal of the comparison (L) circuit 12 corresponding to the synchronization pattern of length L are supplied. The output of the shift register K11 is the length K
Is supplied to the other input terminal of the comparison (K) circuit 13 corresponding to the synchronization pattern of The synchronization pattern detection result by the sync comparison circuit 14 and bit shift amount information indicating at which bit position the synchronization pattern matches are supplied to the comparison (L) circuit 12 and the comparison (K) circuit 13, respectively.

The detection result and the shift amount in the comparison (L) circuit 12 are supplied to the sync detection circuit 15 as a signal CL. Similarly, the detection result and shift amount in the comparison (K) circuit 13 are supplied to the sync detection circuit 15 as a signal CK. In the sync detection circuit 15, the signal CL or the signal C
Based on K, detection and hold of the sync information are performed. The held sync information is supplied to the phase control circuit 16. The phase control circuit 16 determines the write address of the sync information to the sync RAM 17 based on this information.

The sync information is written into the sync RAM 17 based on this address. The sink RAM 17 has a length of (7L−K) as a whole, and the written data is moved to an address corresponding to the data length based on, for example, a clock, and is finally output from the sink RAM 17. In addition, as shown in FIG.
The output to the inertia circuit 18 is made from the middle of the first half 17A of the length (6L-K) and the second half 17B of the length L.

The sync RAM 17 by the phase control circuit 16
By controlling the address, the phase of the data is controlled, and the return processing is performed. The sync information is output from the first half 17A of the sync RAM 17, and the inertia circuit 1
8 is supplied.

On the other hand, the output control circuit 20
From M17, the sync information delayed by the amount based on the address control of the phase control circuit 16 is supplied, and the synchronization pulse generated by the inertia circuit 18 is supplied.
Input data stored in the delay line 19 is read out based on the supplied sync information and synchronization pulse, and is derived to the output terminal 21 as a sync block. Further, the synchronization pulse generated by the inertia circuit 18 is also output to the output terminal 22.

When no synchronization pulse is detected and the output data is synchronized only by the synchronization pulse from the inertia circuit 18, the signal F from the output control circuit 20 is output.
ab-SYNC is output. This signal Fab-SYN
C is supplied to the phase control circuit 16 and a return process is performed.

Next, the processing in the synchronization detection circuit 132 will be described in more detail. As mentioned above,
In the sync block, a synchronization pattern is provided in the first two bytes, an ID number (ID0) is provided in the third byte, and additional information (ID1) is provided in the fourth byte. The type of data stored in the sync block is described in the additional information.

In practice, the sync block simply handles serial data reproduced from the recording medium in units of one byte, which is serial-parallel converted for every 8 bits. Are input in a bit-shifted state. This is shown in FIG. The input data is simply 8 as shown in FIG.
Bits (1 octet) are treated as a unit. FIG.
B, as shown in an example, the delimiter of the input data does not always correspond to the delimiter of the original (recording) data, and the data of each byte is, for example, as shown in FIG. In this example, the input data is shifted by 3 bits with respect to the division of the input data.

The bit shift amount between the input data and the original data is determined by detecting how much the data is shifted to obtain a unique synchronization pattern when the synchronization pattern is detected. Here, a description will be given assuming that the bit shift amount of the input data string is 0 and matches the original data. In this example, reference is made to input data and data delayed by L and K clocks with respect to the input. Then, the data is verified whether the bit-shifted value matches the unique synchronization pattern, the continuity of the ID number and the identity of the ID information, and if all the data are correct, the synchronization pattern is detected. It is judged that it was done.

FIG. 13A shows an example of input data input from the input terminal 1. The length of each sync block starting from the sync pattern is indicated by L. This input data is supplied to the input terminal 1 and sequentially supplied to the shift register L10 and the shift register K11. When data is continuously input, the register in the shift register L10 enters a state as shown in FIG. 14A. In FIG. 14A,
SYNC (L) indicates the first eight bits of the synchronization pattern, and SYNC (H) indicates the second eight bits.

The input data directly from the input terminal 1 and the output of the shift register L 10 are supplied to one and the other input terminals of the comparison (L) circuit 12. For example, data supplied to one input terminal of the comparison (L) circuit 12 is:
The data at the position “A” in FIG. 14A and the data supplied to the other input terminal are the data at the position “B”.

The comparison (L) circuit 12 has, for example, a configuration as shown in FIG. The comparison (K) circuit 13 has the same configuration. Shift register L10
Is input from a terminal 30, and 8 bits are stored in 8-bit parallel registers 31 and 32, respectively. Similarly, input data from the input terminal 1 is input from a terminal 34, and 8-bit parallel registers 35 and 36 store 8 bits each. The EXOR circuits 33, 37 and NO determine whether the data stored in the registers 31, 32 and the data stored in the registers 35, 36 match.
A check is made using the R circuit 38. This is shown in FIG. 14B. The comparison result is output to the output terminal 39.

It is to be noted that the input data is checked beforehand by the sync comparison circuit 14 as to whether it matches the synchronization pattern, and the result is compared with the comparison (L) circuit 12 and the comparison (K) circuit 13.
Respectively. In the sink comparison circuit 14, FIG.
As shown in an example in FIG. 6, input data latched internally is compared with an 8-bit synchronization pattern at each bit position. From the sync comparison circuit 14, the comparison (L) circuit 12 and the comparison (K) circuit 13 provide a detection result indicating whether a synchronization pattern has been detected and, if a synchronization pattern has been detected, which bit A bit shift amount indicating whether the positions match is supplied.

By performing such processing, when a synchronization pattern is input at intervals of the data length L, the comparison (L) circuit 12 performs synchronization at the same bit position detected by the sync comparison circuit 14. It can be detected that the patterns match. Then, the detection result and the bit shift amount are output as the signal CL. As a result, FIG.
The position of each sync block shown in FIG. 3A can be confirmed.

On the other hand, in the shift register K11,
Since the bit length of the register is shorter than the number of bytes of the input sync block, the state shown in FIG. 14A is not obtained. This detection circuit does not detect the synchronization pattern.

Similarly, when sync blocks having a data length of K are successively input, at this time, the shift register K11 and the comparison (K) circuit 13 operate as shown in FIG.
Since the state shown in FIG. 4A and the state shown in FIG. 14B are obtained, it is possible to detect the coincidence of the synchronization patterns. In this case, the shift register L10 and the comparison (L) circuit 12
14B, the synchronization pattern is not detected on the detection circuit side.

As described above, a plurality of sync blocks can be detected by using the circuit of FIG. 11 without specially providing data length information on input data. In principle, by providing a shift register and a comparison circuit for each data length to be detected, the types of data lengths that can be detected simultaneously can be increased.

Next, a method of generating a synchronization pulse indicating the head position of a sync block when outputting input data will be described. Originally, the synchronization detection circuit 132
The data handled in step (1) is data to which sync blocks are continuously input as shown in FIG. 13A. However, there is a possibility that only a part of data or a certain continuous section has been lost due to an error or the like generated in the process of recording and transmission. Since the data portion of the sync block, that is, the data packet, forms an error correction code, even if a part of the data including the synchronization pattern is lost, there is a possibility that the error can be corrected. However, in order to execute the error correction process, the head of the error correction code, that is, the position of the head of the sync block needs to be correctly detected.

Considering that sync blocks of the same length are continuously recorded in the same sector, once a synchronization pattern is detected with a specific data length, the data length at that time is detected. It is highly probable that the sync blocks are arranged at intervals of. Therefore, even if the synchronization pattern cannot be detected, there is a possibility that data can be reproduced based on the synchronization pulse by continuing to output the previously detected synchronization pulse until the next synchronization pattern is detected. For example, as shown in FIG. 13C, the sync block can be correctly reproduced based on the synchronization pulse corresponding to the sync block length as shown in FIG. 13B.

As means for this purpose, a circuit is used in which once a synchronization pattern has been detected, a pulse is output at regular intervals in synchronization with the start of output data. The above-mentioned inertia circuit 18 corresponds to this circuit.

FIG. 17 shows an example of the configuration of the inertia circuit 18 described above. This circuit 18 has data lengths L and K
This corresponds to the two types of data length. An identification signal L / K for determining the data length to be either L or K is supplied to the terminal 50. Identification signal L / K
For example, the detection of the synchronization pattern
This is an identification signal indicating whether the operation was performed using L or the shift register K11. Further, a signal (start pulse) corresponding to the timing of detecting the synchronization pattern is supplied to the terminal 51.

The start pulse is supplied to the start terminal ST of the L / K counter 52 and is also supplied to one input terminal of the OR circuit 58 via the switch circuit 54 whose terminal 51 is initially selected. The output of the OR circuit 58 is supplied to a load input terminal of a counter 59 described later.

The identification signal L / K input to the terminal 50 is
It is supplied to the enable terminal EN of the L / K counter 52 and is used as a selection control signal of the switch circuit 53. Switch circuit 53 selects input terminals 53A and 53B according to the content of identification signal L / K. In response to the selection of the input terminals 53A and 53B, initial values corresponding to the data lengths L and K are supplied and loaded from, for example, a system controller (not shown) to the load data terminal of the counter 59.

The counter 59 counts down from the loaded initial value based on a predetermined clock. And the count value is

When [0] is reached, a synchronization pulse is output for one clock. The output sync pulse is
The signal is output to the output terminal 60 and supplied to the other input terminal of the OR circuit 58. When the synchronization pulse is output, the initial value is loaded again via the switch circuit 53, and the countdown is restarted.

The count by the counter 59 is determined by the OR circuit 5
The process is started with the pulse output from 8 as a starting point. That is, the start point is either the start pulse supplied from the terminal 51 or the synchronization pulse output from the counter 59. And even during the counting,
When the pulse is supplied from the OR circuit 58, the initial value is loaded from the load data terminal, and the countdown from the initial value is started. Therefore, even if the detection position of the synchronization pattern of the input data changes, the initial value is loaded during the counting, so that the synchronization pulse following the input data can be output. The switch circuit 54 is appropriately selected according to the operation of the circuit 18. Depending on the selection of the switch circuit 54, L /
The output from the K counter 52 is the starting point.

FIG. 18 shows an example of the operation timing of the inertia circuit 18 when the data length is L. The counter 59 counts down based on the clock of FIG. 18A. For example, a start pulse and an identification signal L / K are input at timing A (FIGS. 18B and 18C). Then, at the next clock, the initial value corresponding to the data length L is input from the load data terminal, and the countdown from the initial value is performed (FIG. 18D). And the count value is

When it reaches [0] (timing B), a synchronization pulse is output as shown in FIG. 18E even if no start pulse is input. Thus, once started, a synchronization pulse can be output at regular intervals.

As shown at timing C, the counter 5
If a start pulse is input during the countdown by 9, the initial value is loaded at that time. further,
Like timing D, the count value

Even when the input of [0] and the input of the start pulse are performed at the same time, the initial value is loaded at that time in the same manner as at the timing B described above.

As described above, the synchronization pulse is output L clocks after the start pulse is input. on the other hand,
Even when the data length is K, (L
-K) The delay for the clock is adjusted (described later),
Thereafter, the countdown by the counter 59 is started. Therefore, when outputting the output data (sync block), it is necessary to delay by L clocks. This delay of the output data is performed using the delay 19B in the delay line 19 in FIG.

Next, a method of transmitting the detection result of the synchronization pattern to the inertia circuit 18 will be described with reference to FIGS. First, the case where the data length is L will be described with reference to FIG. FIG. 19 shows a synchronization pattern in which the timing A is input at the latest time,
Synchronization pattern for input terminal 1 is F, E, D, C, B
And A in the order shown. In addition,
The sync blocks corresponding to the synchronization patterns input at the respective timings of A, B, C, D, E, and F are referred to as sync blocks A, B, C, D, E, and F, respectively.

When the data length is L, these sync blocks A to F are applied to the shift register L10 and the delay line 19 at the time when the sync block A is input to the shift register L10 as shown in FIG. Is stored. That is, the sync block A is stored in the shift register L10, and the sync blocks BF are sequentially stored in the delay line 19 from the top. It is also assumed that sync block F is the first sync block of the sector.

In FIG. 19, it is assumed that a synchronization pattern cannot be detected at positions F to C, and a synchronization pattern has been detected at positions B and A. In this case, the inertia circuit 18 must be activated for the sync block B. On the other hand, the sync block B is stored at the head of the delay line 19 (FIG. 20). At this position, the sync block cannot be output yet, so the sync pattern detection information must be stored. Therefore, the sink RAM 17 is used.

As shown in FIG. 20, the detection information of the synchronization pattern, that is, the information indicating that the synchronization has been detected, the data length information, and the bit shift amount are (7L−K).
From the beginning of the sink RAM 17 having a length of (L-
K), that is, 6L from the rear end.

Here, the position where the synchronization pulse is generated and synchronization is performed is indicated by F in FIG. 19 corresponding to the head of the sector. Then, the synchronization pattern detection information may be stored at the position of F in the sync RAM 17 shown in FIG. Also,
As shown in FIG. 20, detection information of the synchronization pattern is output to the inertia circuit 18 from a position returned by 1 L from the rear end side of the sync RAM 17. Thereby, the timing of the sync block F stored in the delay line 19 coincides with the timing of the synchronization pulse.

Similarly, an example when the data length is K is shown in FIG.
Shown in Basically, the operation is the same as when the data length is L. However, when the data length is K, the write position of the synchronization pattern information in the sync RAM 17 is from the top of the sync RAM 17. As a result, the position of the sync block stored in the delay line 19 corresponds to the position of the synchronization pattern information stored in the sync RAM 17. Even when the data length is K, the output to the inertia circuit 18 is output to the sink RAM 17.
From the rear end side by 1L.

In the above, the relational expression between the write position counted from the top of the sync RAM 17 and the forward return amount of the synchronous pattern detection information is as follows: For data length L: write position ML = L−K + return amount × L + α (1) For data length K: write position MK = return amount × K + α (2) Here, α is a delay correction amount due to the processing. The return amount is the return amount shown in FIG. In this example, since the ID numbers are continuous within the sector, the return amount is obtained from the difference between the ID number at the position B and the known ID number at the head of the sector.

As described above, the sector (1) in the data string composed of the sync blocks having different lengths from each other.
A sector is composed of a sync block of a single length).

Next, a description will be given of the forward return processing when a synchronous pattern cannot be detected in the middle of a sector.
During the reading of the sector, the synchronization pattern cannot be detected continuously, and then, when the synchronization pattern can be detected again in the sector, an earlier pulse is sent backward by a certain number of sync blocks. Perform the process to generate.

First, the output control circuit 20 determines whether a synchronization pattern cannot be detected for a predetermined number of sync blocks or more. As described above, the synchronous pattern detection information is supplied from the sink RAM 17 to the output control circuit 20 and the inertia circuit 18
Supplies a synchronization pulse. The output control circuit 20 makes this determination using these signals and information. That is, the sync RA
Check the output of M17.

FIG. 22 shows an example of a configuration for performing this processing. The output of the AND circuit 72 is connected to the enable terminal CE of the counter 73, and the inverted synchronization detection bit in the synchronization pattern detection information from the sync RAM 17 supplied from the terminal 71 and the signal supplied from the terminal 70. A with the synchronization pulse from the inertia circuit 18
The value obtained by taking ND is supplied. As a result, when no synchronization pulse is detected and only the synchronization pulse generated by the inertia circuit 18 is used (this state is referred to as Fab-S
The counter 73 counts up to “YNC”.

The counter 73 is reset when the synchronization pattern is detected and the synchronization pattern detection bit of the terminal 71 is set.

The output of the counter 73 is input to the data terminal of the comparison circuit 75. To the Ref terminal of the comparison circuit 75, for example, a Fab-SYNC detection level supplied via a terminal 74 from a system controller (not shown) is input. When the count value of the counter 73 exceeds the Fab-SYNC detection level, the comparison circuit 75 outputs, for example, a Fab-SYNC detection signal whose value is [1].
For example, if Fab-SYNC continues for five or more sync blocks, a Fab-SYNC detection signal is output. This signal is supplied to the phase control circuit 16 from the terminal 76.

In the phase control circuit 16, Fab-SYNC
When the value of the detection signal is [1], and when the fact that the synchronization pattern has been detected is received from the sync detection circuit 15, the forward return processing is performed by a preset forward return amount.
A write address of the synchronous pattern detection information to the sync RAM 17 is created. Then, the received synchronization pattern detection information is stored in the sink RAM 1 based on this address.
Write to 7. The forward return process according to this is shown in FIGS.
1 is performed in the same manner as described above.

In the phase control circuit 16,
If the forward return process at the head of the sector and the forward return process in the middle of the sector overlap, the forward return process at the head of the sector is preferentially performed.

Further, the Fab-SYNC detection signal is shown in FIG.
In addition to the configuration shown in FIG. 2, for example, as shown by a dotted line in FIG.
A circuit 55 may be provided to output the signal. That is, the Fab-SYNC circuit 55 is a counter that counts up by a synchronization pulse output from the counter 59. This counter is reset by a start pulse supplied from the terminal 51. Fa
The count value of the b-SYNC circuit 55 is Fab-SYNC
The signal is output to the terminal 56 as a C signal. Fab-SYNC
The signal is supplied to the phase control circuit 16.

The synchronization pattern detection information is reflected on the output data. That is, the output control circuit 2 which is the final output stage
At 0, the output data from the delay line 19 is shifted by the bit shift amount based on the output of the inertia circuit 18 and the synchronization pattern detection information, and
Restore byte by byte.

In the above description, the synchronization pattern is referred to at intervals of data lengths L and K, but this is not limited to this example. That is, in the same processing, L,
, NL, K, 2K, 3K, ..., mK
It is also possible to refer to the synchronization pattern at intervals of.

Further, in the above description, the magnetic tape is used as the recording medium, but this is not limited to this example. The present invention can be applied to a disk-shaped recording medium such as a hard disk and a magneto-optical disk. Further, the present invention can be applied not only to a recording medium but also to data transmitted via communication such as a network.

[0151]

As described above, according to the present invention, sync blocks having different data lengths are automatically detected, and information for controlling the output of the synchronization pulse by the inertia circuit is synchronized with the data length. Writing is performed corresponding to the position of the RAM where the backward processing is to be performed.
Therefore, there is an effect that the rewind process at the head of the sector, which is indispensable as a circuit for detecting a synchronization signal, can be realized by recording formats having different sync block lengths.

Further, according to the present invention, Fab-SYN
By the C detection signal, there is an effect that the backward processing of the synchronization detection can be performed even in the middle of the sector.

In a reproducing apparatus that performs non-tracking reproduction, since one track is traced by a plurality of heads, the data reproduced from the middle of the track must be processed in the output from each head. I have to. That is, synchronization needs to be re-established other than at the head of the sector. According to the present invention, it is possible to perform the rewinding process even in the middle of a sector, so that there is an effect that the synchronization detection capability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a block diagram showing an example of a configuration of a synchronization detection circuit according to the present invention.

FIG. 12 is a schematic diagram for explaining bit shift of input data.

FIG. 13 is a schematic diagram for explaining input data and a synchronization pulse.

FIG. 14 is a schematic diagram for explaining sync detection using a shift register.

FIG. 15 is a block diagram illustrating an example of a configuration of a comparison (L) circuit and a comparison (K) circuit.

FIG. 16 is a schematic diagram for explaining synchronization pattern detection in the sync comparison circuit.

FIG. 17 is a block diagram showing an example of a configuration of an inertia circuit according to the present invention.

FIG. 18 is a timing chart showing an example of operation timing in the inertia circuit.

FIG. 19 is a schematic diagram for explaining a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 20 is a schematic diagram illustrating a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 21 is a schematic diagram illustrating a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 22 is a block diagram illustrating an example of a configuration for outputting a Fab-SYNC detection signal.

FIG. 23 is a schematic diagram schematically showing an example of the arrangement of each sector on a track.

FIG. 24 is a schematic diagram illustrating an example in which two consecutive synchronization patterns cannot be detected at the beginning of a sector.

FIG. 25 is a block diagram illustrating an example of a configuration of a synchronization detection circuit that performs a return process according to a conventional technique.

FIG. 26 is a schematic diagram schematically showing an example of input data read from the head of a sector;

[Explanation of symbols]

10 shift register L, 11 shift register K, 12 ... comparison (L) circuit, 13 ... comparison (K) circuit, 14 ... sync comparison circuit, 15 ... sync detection Circuit, 16 ... Phase control circuit, 17 ... Sink RAM, 18 ... Inertia circuit, 19 ... Delay line, 20 ... Output control circuit, 59 ... Counter, 73 ... Counter , Comparison circuit, 100...
Recording / reproducing device, 114 ... AUX adding circuit, 116
..Outer code encoders, 117... Shuffling, 1
18 ... ID addition circuit, 119 ... inner code encoder, 120 ... synchronization addition circuit, 123 ... magnetic tape, 132 ... synchronization detection circuit, 133 ... inner code decoder, 134 ... -ID interpolation circuit, 151 ... deshuffling circuit, 152 ... outer code decoder, 153
... AUX separation circuit, 155 ... interpolation circuit, 156
... Output unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/907 H04N 5/92 H 5/92 F term (Reference) 5C018 CA05 GA05 HA05 KA02 LA03 5C052 AA01 AB05 CC02 CC03 CC06 CC11 CC12 GA04 GA07 GB02 GB06 GB07 GB09 GC06 GD01 GD05 GD06 GD09 GF04 5C053 FA22 GA16 GB01 GB06 GB07 GB08 GB10 GB11 GB15 GB18 GB22 GB26 GB30 GB38 HA01 HA33 JA12 JA21 JA26 KA08 KA09 KA19 KA20 KA21 BG07 GM27

Claims (5)

[Claims] 1. A synchronization detecting device for adding a synchronization pattern for detecting synchronization for each data length and performing synchronization detection from an input bit sequence, wherein a synchronization pattern of the input data is detected to synchronize the input data. A synchronization detecting means for generating synchronization detection information comprising information indicating that the synchronization has been detected and data length information based on the detected synchronization interval; and First memory means for sequentially storing a plurality of data blocks as data blocks, and storing the synchronization detection information by the synchronization detection means;
A second memory unit having a length corresponding to the first memory unit; and a position of the synchronization detection information written in the second memory unit when the synchronization is not detected by the synchronization detection unit. Based on the data length information of the synchronization detection information,
Synchronizing signal generating means for generating a synchronizing signal corresponding to the data length; counting the number of times the synchronizing signal is generated by the synchronizing signal generating means; Is detected, the synchronization detection information associated with the detected synchronization is written into the second memory means at a position which is returned by a predetermined length from the position at which the synchronization is detected. And a phase control means for controlling the synchronization. 2. The synchronization detecting device according to claim 1, wherein said second memory means is shorter than said data block by a length which is an integral multiple of the length of said data block, and is shorter than said data block. The phase control means has a length obtained by subtracting the length of another data block exceeding half the length of the data block. If the synchronization corresponding to the data block is detected by the synchronization detection means, From the rear end side of the second memory means from an integer multiple of the data block length. When the synchronization detecting means detects the synchronization corresponding to the other data block, the synchronization detecting information is written A synchronization detecting device, wherein writing is performed from a position of an integral multiple of the length of the other data block from the head of the second memory means. 3. A reproducing apparatus for performing synchronization detection from a bit string to which a synchronization pattern for detecting synchronization is added for each data length, reproduced from a recording medium, wherein the synchronization pattern of the reproduction data is detected to detect the synchronization pattern. Synchronization detection means for generating synchronization detection information comprising information indicating that the synchronization has been detected and data length information based on the detected synchronization interval, and synchronizing the reproduced data with the synchronization data. A first memory unit for sequentially storing a plurality of data blocks as data blocks corresponding to the above, and storing the synchronization detection information by the synchronization detection unit;
A second memory unit having a length corresponding to the first memory unit; and a position of the synchronization detection information written in the second memory unit when the synchronization is not detected by the synchronization detection unit. Based on the data length information of the synchronization detection information,
Synchronizing signal generating means for generating a synchronizing signal corresponding to the data length; counting the number of times the synchronizing signal is generated by the synchronizing signal generating means; Is detected, the synchronization detection information associated with the detected synchronization is written into the second memory means at a position which is returned by a predetermined length from the position at which the synchronization is detected. Output means for outputting the data block stored in the first memory means based on the synchronization signal generated by the synchronization signal generation means or the synchronization detected by the synchronization detection means. A playback device, comprising: a control unit. 4. The reproducing apparatus according to claim 3, wherein said second memory means is shorter than said data block by a length which is an integral multiple of the length of said data block and is shorter than said data block. The phase control unit has a length obtained by subtracting the length of another data block exceeding half the length, and the synchronization detection unit detects the synchronization detection information when the synchronization corresponding to the data block is detected by the synchronization detection unit. Writing is performed from the rear end side of the second memory means at a position which is an integral multiple of the data block length, and when the synchronization corresponding to the other data block is detected by the synchronization detecting means, the synchronization detection information is written to the second memory block. A reproducing apparatus characterized in that writing is performed from a position of an integral multiple of the length of the other data block from the head of the second memory means. 5. A synchronization detection method for adding a synchronization pattern for detecting synchronization for each data length and performing synchronization detection from an input bit string, wherein a synchronization pattern of the input data is detected to synchronize the input data. Detecting and generating synchronization detection information including information indicating that the synchronization has been detected and data length information based on the detected synchronization interval; and synchronizing the input data with the synchronization. Storing a plurality of data blocks in the first memory in order in the first memory; storing the synchronization detection information in the synchronization detection step in a second memory having a length corresponding to the first memory; If the synchronization is not detected in the synchronization detection step, the position of the synchronization detection information written in the second memory and the synchronization A synchronizing signal generating step of generating a synchronizing signal corresponding to the data length based on the data length information of the output information; and counting the number of times the synchronizing signal is generated by the synchronizing signal generating step. Is greater than or equal to a predetermined value, and when the synchronization is detected in the step of detecting the synchronization, the second memory is returned to a position which is returned by a predetermined length from the position where the synchronization is detected.
A phase control step of controlling to write the synchronization detection information accompanying the detected synchronization.