JP2000149426A - Memory accessing device and method therefor, and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the efficiency of accessing memory. SOLUTION: Data are inputted/outputted to/from a main memory for record processing (packing, shuffling, and encoding of error correction code). The main memory has four banks, and each bank is addressed by column, and row address. The main memory 1 is divided into logical units of a capacity more than the data amount of one Sync block, and each logical unit has an index. In the logical unit, a burst is performed in the direction of a column address. Since 8-word addressing in a burst is successive, only the leading address is designated. When the burst succeeds more than once, it is developed in the bank direction. Namely, a bank is switched over when the burst has once been completed. And, when the burst has made a tour of four banks, the column address is proceeded further. The above addressing is repeated. When a column address has been used up, a row address is proceeded to the next.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access device and method applied to, for example, recording compressed image data on a recording medium and reproducing the image data from the recording medium, and a data processing device.

[0002]

2. Description of the Related Art Digital VCR (VIdeo Cassette Reco)
A data recording / reproducing apparatus which records a digital image signal on a recording medium and reproduces the digital image signal from the recording medium, as typified by rder), is known. A recording processing unit in a digital image recording device can be roughly divided into an input processing unit, a main processing unit, and an output processing unit. The input processing unit stores video and audio digital data in packets of a predetermined length. The main processing unit encodes information indicating data contents and an error correction code in packet units. The output processing unit outputs a synchronization pattern, ID, and the like for packetized data, parity of an error correction code, and the like.
Are added to form a sync block, the sync blocks are grouped according to the type of data, and converted into serial data in units of the sync blocks. A rotary head for recording on a tape as a recording medium is connected to the output processing unit.

In a process of storing digital data in a packet, a process of error correction coding, and the like, data is processed through a main memory. As the main memory, a large-capacity memory is used because it is necessary to store a large amount of audio data and video data. In the current technology, even if the recording processing unit is configured as an integrated circuit, the main memory has a large capacity, so that it is difficult to integrate it on the same semiconductor substrate, and the cost increases. Therefore, a single device (element) independent of the recording processing unit is used as the main memory. To construct the main memory at the lowest possible cost, DRAM (Dynamic R
andom Access Memory), EDO (Extended data out) −
RAM, SDRAM (Synchronous Dynamic Random Acce
It is realistic to use a DRAM device such as an ss memory. Furthermore, considering speed, SDRA
It is reasonable to choose M.

There are some technical difficulties when using a DRAM-based device such as an SDRAM. That is, the address space is divided into banks, columns, and rows, and is not a linear space like an SRAM (Static Random Access Memory). The column and the row have a relationship like the X axis and the Y axis, and data can be accessed by specifying both. First, a row address is given, and then a column address is given. The output can immediately follow the change in the column address.
In addition, if the row address is determined, a plurality of words, for example, eight words can be collectively obtained as an output (burst output). On the other hand, for a change in the row address, the output changes after a certain delay (command delay time). This means that in a situation where the row address is frequently switched, the efficiency is low and the data output is delayed.

In the case of an SDRAM, there are a plurality of RAMs composed of columns and rows.
Is called a bank. When data is to be obtained continuously over a long word, it is necessary to switch one row after another since the data cannot be stored only by the column address in the address control. However, in this method, a command delay time occurs as described above, and the address efficiency is poor. In such a case, the command delay time can be eliminated by switching to another bank and specifying a row address in that bank.

FIG. 16 schematically shows a process for accessing the SDRAM, for example, a process for writing eight words. FIG.
5A shows a clock ckm, and FIG. 15B shows a process in a case where bank switching is involved. First, when a row address is given to the bank A by a command ACT, writing of a burst unit, for example, 8 words is started in the bank A by a command WT delayed from the ACT. In consideration of the delay time, the command ACT is applied to the bank B before the writing to the bank A is completed. Thus, when the writing of the burst unit of the bank A is completed, 8 words of the burst unit can be continuously written to the bank B. According to this method, the influence of the waiting time due to the precharge for changing the row address can be prevented.

On the other hand, when the bank switching is not adopted, the burst unit is written only in the same bank, for example, bank A. As shown in FIG. 15C, in this case, the row address is given by the command ACT a predetermined time after the end of the writing in the burst unit, so that a delay occurs until the next burst unit is written.

[0008]

Conventionally, for a memory device having a property in which bank switching is effective, a data storage method is used in which all banks, all columns, and all rows are simply connected and can be handled linearly. Was. However,
In the memory access using this address, it is necessary to uniquely determine the timing design. If the rate of data written to or read from the memory fluctuates greatly, timing design becomes extremely difficult.
This problem is a major obstacle in realizing a digital VCR capable of recording / reproducing a plurality of video / audio data of different formats or different data rates. Further, when the main memory is used for processing both video data and audio data, or when the main memory is used for a plurality of processings of video data, an interface having a plurality of input / output ports for the main memory is used. Is required. In such a situation, the timing design still has a problem.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a memory access device and method capable of efficiently accessing memory when storing data, and a data processing device.

[0010]

In order to solve the above-mentioned problems, the invention according to claim 1 has a plurality of banks, each of which has an address specified by a row and column address, and a unit of a plurality of words. In a memory access device that accesses a burstable memory accessed as a unit, a logical unit having a capacity equal to or larger than the data unit amount at the time of transmission or recording is set, bursting is performed in the column address direction of the logical unit, and continuous. This memory access device is characterized in that when a burst occurs, the bank is switched, the operation of advancing the column address is repeated when the number of banks has reached one cycle, and the addressing is performed so that the row address is advanced by one when the column address is exhausted.

According to a second aspect of the present invention, there is provided a data processing apparatus for transmitting or recording digital information data as a data unit delimited by a synchronization signal, wherein the data processing apparatus has a plurality of banks. A memory in which digital information data is input or output in units of data, which is designated and can be accessed in units of a plurality of words, and an error correction encoder for encoding an error correction code using the memory; A means for recording or transmitting data that has been error-correction-encoded by a correction encoder. Performs a burst and switches banks when a continuous burst occurs Repeating the operation of number of banks advances the column address Once round is a data processing apparatus and performs addressing to advance one row address Once exhausted the column address.

The invention according to claim 6 has a plurality of banks,
In a memory access method in which each bank is addressed by a row and column address and accesses a burstable memory accessed in units of a plurality of words, a logic having a capacity equal to or larger than the data unit amount during transmission or recording is provided. Set the unit, perform burst in the column address direction of the logical unit, and when a continuous burst occurs, switch the bank, repeat the operation of advancing the column address when the number of banks reaches one cycle, and increase the row address by one when the column address is exhausted. This is a memory access method characterized by performing addressing so as to proceed.

When digital information data (video data, audio data, etc.) is recorded and transmitted, it is usually divided into data units called sync blocks. When there are a plurality of data amounts in a data unit, even if a memory access device is designed for one data unit length, it is difficult to design a timing for another unit length.
According to the present invention, a plurality of logical units having a capacity equal to or larger than a certain data unit amount are set to correspond to a plurality of data units. And
By performing addressing in this logical unit and further devising addressing in the logical unit, data is not interrupted.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Recording and recording of video signals of multiple different formats
It enables playback. For example, a signal (480i signal) having 480 effective lines in the interlaced scanning based on the NTSC system and a signal (576 signals) having 576 effective lines in the interlaced scanning based on the PAL system.
i) are recorded with almost no hardware changes.
It is possible to reproduce. Furthermore, a signal having 1080 lines (1080i signal) in interlaced scanning,
In progressive scanning (non-interlace), the number of lines is 480, 720, and 1080, respectively.
Recording / reproduction such as 0p signal, 720p signal, and 1080p signal) can also be performed.

In this embodiment, a video signal and an audio signal are compression-coded based on the MPEG2 system. As is well known, MPEG2 is a combination of motion compensated prediction coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer,
A slice layer, a picture layer, a GOP (Group Of Picture) layer, and a sequence layer are provided.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I picture (Intra-coded picture) uses information that is closed only in one picture when it is encoded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as a macro block type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock predicting the future from the past, and backward (Backward) interframe prediction macroblock predicting the future from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP contains at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not provided with the identification codes arranged in byte units.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

The recording area in which the recording data of one frame is recorded is predetermined. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration of the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the overflow portion that protrudes from the fixed frame is sequentially packed in an area vacant with respect to the size of the fixed frame. Further, system data such as a time code is supplied from the input terminal 108 to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to a shuffling unit 110, and shuffling is performed so that the order is changed over a plurality of ECC blocks in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling performed by the shuffling unit 110 may be referred to as interleaving. The output of the shuffling unit 110 is supplied to the mixing unit 111 and mixed with the audio data. The mixing unit 111 is configured by a main memory, as described later.

Audio data is supplied from an input terminal 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX unless otherwise necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, where the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of the shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code (unequal length data) is restored. Further, in the deshuffling and depacking section 138, the system data is separated and taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component over the DCT block, even if the DCT coefficients are ignored from a certain point onward, even if the macro block is ignored. , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is secured in accordance with the maximum length of the macroblock, as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with the input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this embodiment, recording of a signal on a magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is composed of two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is arranged between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since one field of audio data is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data (including the outer code parity) of the two ECC blocks is divided into four sectors.
As shown in (1), the data is recorded separately on four tracks. 2
A plurality of sync blocks included in the ECC blocks are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, the video data is shuffled (interleaved) for four ECC blocks for one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks. Depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this embodiment, one or two macroblocks of data (VLC data) are stored for one sync block according to the format of video data to be recorded, and the size of one sync block is reduced. The length is changed according to the format of the video signal to be handled. As shown in FIG. 5A, one sync block is
From the beginning, a 2-byte SYNC pattern, a 2-byte I
D, a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). Note that the data area is also called a payload.

The first two bytes of the SYNC pattern are used for synchronization detection and have a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example where video data (unequal length data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, a data length indicator LT indicating the length of unequal length data corresponding to the macroblock is arranged in the first three bytes. The data length indicator LT may or may not include its own length. Also,
In the example shown in FIG. 5C in which two macroblocks are stored, the data length indicator LT of the first macroblock is arranged at the beginning, and the first macroblock is arranged subsequently. Then, the data length indicator LT indicating the length of the second macroblock is arranged following the first macroblock, and
Are arranged. The data length indicator LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The first data length indicator LT describes the length of the video AUX data. Following this data length indicator LT, 5 bytes of system information, 12 bytes of PICT information, and 9 bytes
Two bytes of user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, the length of the payload, which is the storage area for the data of each sync block, is not optimally set for the video sync block and the audio sync block, and is therefore not equal to each other. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

The stream converter 106 rearranges the DCT coefficients of the supplied signal. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

In the stream converter 106, the variable-length coded and arranged DCT coefficients are once decoded by the variable-length code to detect a break of each coefficient, and the frequency is spread over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows the processing of packing macroblocks in the packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time matches the data length of the sync block, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity,
Assume that one frame contains eight macroblocks.

As shown in an example in FIG. 9A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, compared to the length of the data area of one sync block, which is a fixed frame, the data of the macro blocks # 1, # 3 and # 6 are each longer,
The data of the macro blocks # 2, # 5, # 7 and # 8 are short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of unequal-length data corresponding to each macroblock can be checked in advance by the stream converter 106. As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing and shuffling unit 107. A SYNC pattern, ID, and DID are added to each row of the VLC data, and a parity of an inner code is added to form one SYNC block.

That is, a 10-byte outer code parity is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID, and VLC data (or external data) aligned in the horizontal direction are generated. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the difference between the lengths of VLC data in one SYNC block is 59.94 Hz, 25 Hz, and 23.97.
This is because the frame frequency of video data is different, such as 6 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz, and one sample is quantized to 24 bits. One sample may be converted to another number of bits, for example, 16 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of even-numbered and odd-numbered audio samples and audio AUX as data.

FIG. 11 shows a more specific configuration of the recording side configuration according to an embodiment of the present invention. In FIG. 11, 16
Reference numeral 4 denotes an interface of the main memory 160 external to the IC. The main memory 160 is an SDRAM
It is composed of With the interface 164,
The write / read operation of the main memory 160 is controlled. The packing and shuffling unit 107 is constituted by the packing unit 107a, the video shuffling unit 107b, and the packing unit 107c.

FIG. 12 shows an example of the address configuration of the main memory 160. The main memory 160 is, for example, an SD
It is composed of RAM. The main memory 160 has a video area 250, an overflow area 251 and an audio area 252. The video area 250 includes four banks (vbank # 0, vbank # 1, and vbank # 2).
And vbank # 3). Each of the four banks can store digital video signals of one equal length unit. One equalization unit is a unit for controlling the amount of generated data to a substantially target value, for example, one picture (I
Picture). A part A in FIG. 12 shows a data part of one sync block of the video signal. Data of a different number of bytes is inserted into one sync block depending on the format (see FIG. 5A). In order to support a plurality of formats, the data size of one sync block is equal to or more than the maximum number of bytes and is a number of bytes convenient for processing, for example, 256 bytes.

Each bank in the video area is further divided into a packing area 250A and an output area 250B to the inner encoding encoder. Overflow area 251
Consists of four banks, corresponding to the video area described above. Further, the main memory 160 has an area 252 for audio data processing.

In this embodiment, by referring to the data length indicator LT of each macro block, the packing unit 107a separates the fixed frame length data and the overflow data that is beyond the fixed frame into separate data in the main memory 160. It is stored separately in areas 250 and 251. The fixed frame length data is data shorter than the length of the data area of the sync block, and is hereinafter referred to as block length data. The area for storing the block length data is the packing processing area 250A of each bank. If the data length is shorter than the block length, an empty area is created in the corresponding area of the main memory 160. The video shuffling unit 107b performs shuffling by controlling the write address. Here, the video shuffling unit 107b shuffles only the block length data, and the overflow portion is written to the area assigned to the overflow data without shuffling.

Next, the packing section 107c performs processing of packing and reading the overflow portion into the memory for the outer code encoder 109. That is, 1 is prepared from the main memory 160 to the outer code encoder 109.
The data of the block length is read into the memory of the ECC block, and if there is an empty area in the data of the block length, an overflow portion is read there to block the data to the block length. When the data for one ECC block is read, the reading process is temporarily suspended, and the outer code encoder 109 generates the parity of the outer code. The outer code parity is the outer code encoder 10
9 is stored in the memory. When the processing of the outer code encoder 109 is completed for one ECC block, the outer code encoder 1
From 09, the data and the outer code parity are rearranged in the order of performing the inner code, and are written back to the packing processing area 250A of the main memory 160 and another output area 250B.
The video shuffling unit 110 performs shuffling on a sync block basis by controlling an address at the time of writing back the data on which the encoding of the outer code has been completed to the main memory 160.

As described above, the block length data and the overflow data are separated and the data is written into the first area 250A of the main memory 160 (first packing process), and the overflow data is packed into the memory of the outer code encoder 109. (The second packing process), the generation of the outer code parity, and the data and the outer code parity in the second area 250 of the main memory 160.
The process of writing back to B is performed in units of one ECC block.
Since the outer code encoder 109 includes the memory having the size of the ECC block, the frequency of access to the main memory 160 can be reduced.

A predetermined number of Es contained in one picture
When the processing of the CC block (for example, 32 ECC blocks) is completed, the packing of one picture and the encoding of the outer code are completed. The data read from the area 250B of the main memory 160 via the interface 164 is processed by the ID addition unit 118, the inner code encoder 119, and the synchronization addition unit 120, and the output data of the synchronization addition unit 120 is output by the parallel / serial conversion unit 124. Is converted to bit serial data. The output serial data is processed by the partial response class 4 precoder 125. This output is digitally modulated as necessary, and supplied to the rotary head via the recording amplifier 121.

A sync block in which valid data called null sync is not arranged in the ECC block is introduced.
The flexibility of the configuration of the C block may be provided. The null sink is generated in the packing unit 107a of the packing and shuffling block 107,
Written to main memory 160. Therefore, since the null sync has a data recording area, it can be used as a recording sync for the overflow portion.

In the case of audio data, even-numbered samples and odd-numbered samples of one-field audio data form different ECC blocks. Since the ECC outer code sequence is composed of audio samples in the input order, the outer code encoder 116 generates an outer code parity each time an outer code sequence audio sample is input. The address control when writing the output of the outer code encoder 116 to the area 252 of the main memory 160 causes the shuffling unit 117 to perform the shuffling (channel unit and sync block unit).

Further, a CPU interface indicated by 126 is provided, and can receive data from the CPU 127 functioning as a system controller. This data includes shuffling table data, parameters related to the format of the recording video signal, and the like. The shuffling table data is stored in a video shuffling table (RAM) 128v and an audio shuffling table (RAM) 128a. The shuffling table 128v performs an address conversion for shuffling the video shuffling units 107b and 110. Shuffling table 128a
Performs address conversion for audio shuffling 117.

The present invention relates to the main memory 160 described above.
Applies to access to Main memory 1
As 60, a 64 Mbit SDRAM is used. The specific specifications are as follows.

Total number of bits: 67108864 Bit width per word: 32 Number of banks: 4 Number of rows: 2048 Number of columns: 256 Burst (number of words): Select 8 out of 1, 4, 8 Total number of bits: It is the product of the number of banks, the number of rows, the number of columns, and the bit width.

The above-mentioned specification will be further described.
The fact that the bit width per word is 32 bits / word means that the size of data represented by one address is one word, that is, 32 bits (4 bytes).
Means that One row has 256 column addresses and 256 words, that is, 10
24 bytes can be stored. Further, the fact that the burst is 8 means that continuous data can be read / written in units of 8 words (= 32 bytes).

In the case of a recording device such as a digital VCR, the recording / reproducing operation is performed in units of sync blocks, and in the recording / reproducing process, input / output of video / audio data in units of sync blocks is simplified. It is convenient for conversion. As described above, this embodiment can handle a plurality of formats, and the data of the sync block excluding the sync signal, ID, and inner code parity of the sync block does not exceed 256 bytes for both video data and audio data. . In view of this, a configuration is adopted in which 256 bytes are used as logical breaks in the main memory 160 as well.

Although 256 bytes are treated as a logical unit (called a box) capable of storing one sync block, a new virtual address is introduced in order to improve access efficiency. The size of 256 bytes in one box is 64 words, which corresponds to 8 bursts. From such a relationship, as described below, the 256
Make up the bytes.

A burst (8 words / times) is performed in the column address (sdram col) direction. Since addressing of eight words in a burst is continuous, only the head address is specified.

If the burst continues a plurality of times, the bank (sdr
am bank). That is, when one burst is completed, the bank is switched.

When the four banks make one cycle, the column address is advanced. The above addressing is repeated.
When the column address is used up, the row address (sdram ro
w) Step forward one step.

FIG. 13 schematically shows data storage in the main memory 160 described above. FIG. 13A
, Each of the banks # 0 to # 3 has 256
Column addresses and 2048 row addresses. As shown in FIG. 13B, a number is assigned to a box on the main memory that stores the sync block, and the number is called an index (sdram index). In addition, it indicates the number of the burst in the index (sdram
burst) is introduced.

FIG. 13C shows the contents of an index, for example, # 0. 256 bytes of the box of one sync block (= 6
4 words) are eight bursts. First bank #
Eight words from head column address # 0 to # 7 are addressed by row # 0 of 0. Next, the bank is switched to # 1 in order to continuously address data in burst units. Similarly, data is stored in burst units. When the data storage up to bank # 3 is completed, the column address is advanced. That is, the head column address # 8 is designated, and similar data storage in burst units is performed. By eight burst units,
A box of one sink block is formed.

As for index 1, the head column address is set to # 16, and data is stored in the same manner as in FIG. 13C. Since the column addresses are # 0 to # 255, when a burst is performed with the column addresses # 248 to # 255, the process returns to # 0. At this time, the row address is advanced by one from # 0 to # 1.

The address (bank, row, column) described above, the index, and the physical quantity indicating the number of the burst within the index make it possible to address the main memory 160 based on the sync block number. The bank, row, and column addresses and indexes have the following relationship.

Sdram burst [2: 0] = ｛sdram col [3], sdra
m bank [1: 0]｝; sdram index [14: 0] = ｛sdram row [10: 0], sdram col [7:
4]｝; or conversely, sdram bank [1: 0] = sdram burst [1: 0],｝; sdram col [7: 0] = ｛sdram index [3: 0], sdram burst
[2], 3'b000｝; sdram row [10: 0] = sdram index [14: 4]; The lower 3 bits of sdram col are 3'b000 because the burst made in the column address direction is a word burst and the address is continuous.
This is because only the head address of the burst needs to be managed. The bank, row, and column addresses obtained in this way are linked to form a virtual address (interface address) mprm adrs [20: 0] of the main memory 160.

Mprm adrs [20: 0] = ｛sdram bank [1: 0], sdra
m row [10: 0], sdram col [7: 0]}; FIG. 14 shows the correspondence between the bit numbers 0 to 20 of the concatenated virtual address and each address.

FIG. 13B shows the capacity of the main memory 160 as an index. The vertical axis represents the index, and the horizontal axis represents the burst direction for convenience. FIG. 13C shows the content of one index with the burst direction as the vertical axis.

As shown in FIG. 12, both the audio data and the video data are roughly addressed by an index (sdram index) corresponding to a box of a sync block, and the data inside the data is a burst (sdram burst).
It is possible to indicate by using.

The present invention is applicable to a case where a recording medium such as an optical tape other than a magnetic tape, an optical disk (a magneto-optical disk, a phase change type disk) or the like is used, and a case where data is transmitted via a transmission line. Can be applied.

[0112]

According to the present invention, even when there are a plurality of data units (sync blocks), since a logical unit larger than the maximum data amount is set, transmission and recording of a plurality of formats can be supported. Further, by introducing a virtual address different from the physical address of the memory, the memory can be accessed efficiently. Further, by associating a logical unit with a sync block, memory management in data recording or reproduction processing can be facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a more specific block diagram of a recording signal processing unit.

FIG. 12 is a schematic diagram illustrating a memory space of a memory to be used.

FIG. 13 is a schematic diagram for explaining memory addressing;

FIG. 14 is a schematic diagram illustrating a virtual address.

FIG. 15 is a timing chart for explaining one example and another example of a memory access.

[Description of Reference Numerals] 107: Packing and shuffling unit, 10
9, 116 ... outer code encoder, 110, 117
..Shuffling section, 118... ID adding section, 120
... Synchronization addition unit, 160 ... Main memory

Claims (6)

[Claims] 1. A memory access device having a plurality of banks, each of which is designated by a row and column address and accesses a burstable memory accessed in units of a plurality of words. Alternatively, a logical unit having a capacity equal to or greater than the data unit amount at the time of recording is set, and a burst is performed in the column address direction of the logical unit,
A memory access device characterized in that when a continuous burst occurs, the bank is switched, the operation of advancing the column address is repeated when the number of banks has reached one cycle, and the addressing is performed so that the row address is advanced by one when the column address is used up. 2. A data processing apparatus for transmitting or recording digital information data as a data unit delimited by a synchronization signal, comprising a plurality of banks, each bank having an address designated by a row and column address, and a plurality of words. A memory in which digital information data is input or output in data units, an error correction encoder for encoding an error correction code using the memory, and an error correction encoder. Means for recording or transmitting error-correction-encoded data; a logical unit having a capacity equal to or greater than the data unit amount at the time of transmission or recording is set in the memory, and bursts in the column address direction of the logical unit Do
A data processing apparatus characterized in that when a continuous burst occurs, the bank is switched, the operation of advancing the column address is repeated when the number of banks has reached one cycle, and the addressing is performed so that the row address is advanced by one when the column address is used up. 3. The apparatus according to claim 1, wherein a plurality of data unit amounts at the time of transmission or recording are made possible. 4. The apparatus according to claim 1, wherein the logical unit is accessed by changing only the column address without changing the row address and repeating bank switching a plurality of times. 5. The device according to claim 1, wherein the logical unit is 256 bytes. 6. A memory access method comprising a plurality of banks, each of which is designated by a row and column address and accesses a burstable memory accessed in units of a plurality of words. Alternatively, a logical unit having a capacity equal to or greater than the data unit amount at the time of recording is set, and a burst is performed in the column address direction of the logical unit,
A memory access method comprising: switching a bank when a continuous burst occurs; repeating an operation of advancing a column address when the number of banks has reached one cycle; and performing addressing such that a row address is advanced by one when the column address is used up.