JP2000298614A - Memory interface and data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve transfer efficiency between a memory and a signal processing block and also to make it possible to use the memory whose operation speed is slow in the signal processing block. SOLUTION: An arbitration block outputs a busy signal showing a period being accessible to an internal block and a period being inaccessible to it. The internal block makes a burst start signal showing the heads of an address and data a high level before a busy signal becomes a low level (showing accessibility) as shown in C when a burst is written to a memory. The arbitration block processes the burst start signal received as what arrives in the case the burst start signal received from the internal block is at the high level while the busy signal outputted by the arbitration block itself is at the low level. It is possible to prevent space from occurring on data to be transferred by processing the burst start signal by two clocks fast.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory interface and a data processing apparatus which are used for, for example, recording compressed image data on a recording medium and reproducing the image data from the recording medium.

[0002]

2. Description of the Related Art Digital VTR (Video Tape Recorder)
As represented by r), there is known a data recording / reproducing apparatus for recording a digital image signal on a recording medium and reproducing the digital image signal from the recording medium. A recording processing unit in a digital image recording device can be roughly divided into an input processing unit, a main processing unit, and an output processing unit. The input processing unit stores video and audio digital data in packets of a predetermined length. The main processing unit encodes information indicating data contents and an error correction code in packet units. The output processing unit outputs a synchronization pattern, ID, and the like for packetized data, parity of an error correction code, and the like.
Are added to form a sync block, the sync blocks are grouped according to the type of data, and converted into serial data in units of the sync blocks. A rotary head for recording on a tape as a recording medium is connected to the output processing unit.

In a process of storing digital data in a packet, a process of error correction coding, and the like, data is processed through a main memory. As the main memory, a large-capacity memory is used because it is necessary to store a large amount of audio data and video data. In the current technology, even if the recording processing unit is configured as an integrated circuit, the main memory has a large capacity, so that it is difficult to integrate it on the same semiconductor substrate, and the cost increases. Therefore, a single device (element) independent of the recording processing unit is used as the main memory. To construct the main memory at the lowest possible cost, DRAM (Dynamic R
andom Access Memory), EDO (Extended data out) −
RAM, SDRAM (Synchronous Dynamic Random Acce
It is realistic to use a DRAM device such as an ss memory. Furthermore, considering speed, SDRA
It is reasonable to choose M.

There are some technical difficulties when using a DRAM-based device such as an SDRAM. That is, the address space is divided into banks, columns, and rows, and is not a linear space like an SRAM (Static Random Access Memory). The column and the row have a relationship like the X axis and the Y axis, and data can be accessed by specifying both. First, a row address is given, and then a column address is given. The output can immediately follow the change in the column address.
In addition, if the row address is determined, a plurality of words, for example, eight words can be collectively obtained as an output (burst output). On the other hand, for a change in the row address, the output changes after a certain delay (command delay time). This means that in a situation where the row address is frequently switched, the efficiency is low and the data output is delayed.

In the case of an SDRAM, there are a plurality of RAMs composed of columns and rows.
Is called a bank. When data is to be obtained continuously over a long word, it is necessary to switch one row after another since the data cannot be stored only by the column address in the address control. However, in this method, a command delay time occurs as described above, and the address efficiency is poor. In such a case, the command delay time can be eliminated by switching to another bank and specifying a row address in that bank.

FIG. 20 schematically shows a process for accessing the SDRAM, for example, a process for writing eight words. FIG.
0A shows the clock ckm, and FIG. 20B shows the processing when bank switching is involved. First, when a row address is given to the bank A by a command ACT, writing of a burst unit, for example, 8 words is started in the bank A by a command WT delayed from the ACT. In consideration of the delay time, the command ACT is applied to the bank B before the writing to the bank A is completed. Thus, when the writing of the burst unit of the bank A is completed, 8 words of the burst unit can be continuously written to the bank B. According to this method, the influence of the waiting time due to the precharge for changing the row address can be prevented.

On the other hand, when the bank switching is not adopted, the burst unit is written only in the same bank, for example, bank A. As shown in FIG. 20C, in this case, the row address is given by the command ACT a predetermined time after the end of the writing in the burst unit, so that a delay occurs until the next burst unit is written.

Further, the main memory is shared by a plurality of data processing circuits for respectively processing a plurality of data such as video data and audio data. Since access requests to the main memory from a plurality of data processing circuits may collide, an arbitration circuit is provided between the plurality of data processing circuits and the main memory. When the arbitration block receives a write request from the internal block,
Write data must be supplied to the SDRAM so that no bus space is generated. When the arbitration block cannot process an access request from another block, it is necessary to notify the state to the internal block. A busy signal is used as a signal for that purpose.
If the busy signal is high level, for example, the SDRAM
Is defined as a period during which access to is not possible.

FIG. 21 shows internal blocks 301 and 30.
2 shows a schematic configuration in which an arbitration block 303 is provided between an SDRAM 304 and a main memory. The arbitration block 303 provides a busy signal to the internal blocks 301 and 302 indicating whether or not access (ie, write or read) is possible. In FIG. 21,
As an example, the internal block 301 performs a write operation on the SDRAM 304 and the internal block 302
A read operation is performed on the AM 304. Arbitration block 3
A data bus and a control bus are provided between the SDRAM 304 and the SDRAM 304.

FIGS. 22 and 23 are schematic block diagrams used for explaining problems. FIG. 22 shows only a configuration when the internal block 301 writes data to the SDRAM 304. FIG.
01 or 302 shows a configuration in which the RAM 305 is included therein, and data read from the RAM 305 is supplied to the arbitration block 303 via the flip-flop 306.

In a state where the busy signal indicates a period during which access is possible, the internal block 301 generates a burst start signal as an access start signal. The start position of the write address and the start position of the write data are indicated by the burst start signal. Following the address, write data is supplied from the internal block 301 to the arbitration block 303.

The internal block 302 stores the data in the SDR in a state indicating that the busy signal can be accessed.
To read from the AM 304, a burst start and read address are provided to the arbitration block 303,
The read data is received from the arbitration block 303. In this case, the arbitration block 303 generates an enable indicating the valid period of the read data. As an example, a busy signal, a burst start signal, and an enable
Bits, the address bus is 21 bits wide, and the data bus is 32 bits wide.

FIG. 2 is a timing chart of the configuration of FIG.
It is shown in FIG. FIG. 24A shows a clock signal as a timing reference, a burst start signal, and an address. The internal block 301 recognizes that the busy signal is at the low level, and sends a burst start signal, an address and data to the arbitration block 303. The burst start signal indicates the start of a burst, that is, the position of an address and data. The address is 21 bits wide, and one of the four banks is specified by the upper two bits.

FIG. 24B illustrates an interface between the internal block 301 and the arbitration block 303 during a write operation. During the write operation, the internal block 30
1 to the arbitration block 303. Eight words of D0 to D7 are one burst, and when the writing of one burst is completed, a burst start signal and an address are sent again from the internal block 301 to the arbitration block 303, and the bank is switched. 8 words of the burst are written. A busy signal that goes high during a write operation is supplied to the internal block 301. When the busy signal goes low, the next burst start signal and address are supplied to the arbitration block 303. Then, write data is generated on the SDRAM bus between the arbitration block 303 and the SDRAM 304 after a delay of the number of clocks according to the configuration of the arbitration block 303.

FIG. 24C illustrates an interface between the internal block 302 and the arbitration block 303 during a read operation. By providing the burst start signal and the address shown in FIG. 24A from the internal block 302 to the arbitration block 303, a read operation is performed. FIG. 24C is read from SDRAM 304,
It shows read data generated on the SDRAM bus, a busy signal from the arbitration block 303 to the internal block 302, read data (two bursts), and an enable signal synchronized with valid read data. The internal block 302 can recognize that the read data exists during the period when the enable signal is at the high level.

FIG. 24 shows both the write operation and the read operation in a state in which other internal blocks are not processed, that is, the operation at the maximum speed. If other internal blocks are processed, the length of the busy signal is
It is longer than that shown in FIG.

[0017]

In the configuration shown in FIGS. 21 and 22, the internal block 301 has an SDRAM 304.
During the write operation of writing data to the memory, when it is recognized that the busy signal has fallen to the low level and the write operation is started, extra time is required for processing, and the SDR
There is a problem that efficient access to the AM 304 cannot be performed. This problem will be described with reference to FIG.

FIG. 25A shows a clock and a busy signal. When the internal block 301 receives such a busy signal from the arbitration block 303, it is desirable that the internal block 301 supplies the burst start signal, the address, and the write data to the arbitration block 303 at the timing shown in FIG. 25B. However, the internal wiring delay between the internal block 301 and the arbitration block 303 is large ASIC (Application Specific Integrated
Circuit). Therefore, the internal block 3
When a busy signal and a burst start signal are transmitted between 01 and the arbitration block 303, flip-flops are provided on each of the side for outputting these signals and the side for inputting these signals for stabilizing timing.

Therefore, as shown in FIG.
Is generated from the arbitration block 303, a delay of one clock occurs because the internal block 301 receives the busy signal by the flip-flop. The burst start signal is generated by recognizing that the busy signal taken into the flip-flop is at the low level. Since a flip-flop is interposed to transmit the generated burst start signal to the arbitration block 303, the burst start signal as the flip-flop output is delayed by one clock.

Therefore, a desirable control timing (FIG. 25)
B), the burst start signal and the address generated from the internal block 301 have a delay of two clocks as shown in FIG. 25C. As a result, the internal block 301 and the arbitration block 3
For data transmitted between the data of the bank A and the data of the next bank B, a vacancy of two clocks occurs between the data of the bank A and the data of the next bank B.

As another problem, as shown in FIG.
Data of an internal block to be written to the SDRAM 304 is stored in the internal RAM 305, and when the data is read therefrom and output to the SDRAM 304, the data stored in the RAM 30 is smaller than that of a circuit such as a flip-flop.
Because of the low access speed of No. 5, continuous reading by the clock may not be possible.

The internal RAM 305 is a synchronous RAM. In a large-scale ASIC, a clock synchronous RAM is employed in order to improve the operation speed of the RAM. Data is read from the address given to the internal RAM 305, and the read data is output to the arbitration block 303 via the flip-flop 306.

FIG. 26A shows a clock, and FIG. 26B shows an address. As shown in FIG. 26C, the internal RAM 30
5 is short, the addresses A0, A
1, A2,... Corresponding to the read data D0, D
Are generated from the internal RAM 305. The access time is the time from the timing of the clock until the data is output. The read data is sampled by the flip-flop 306, and the write data is transmitted to the arbitration block 303 in synchronization with the clock, as shown in FIG. 26D. In FIG. 26C, hatched data represents invalid data.

However, if the access time of the internal RAM 305 is long, valid data cannot be read from the internal RAM 305 as shown in FIG. 26E. Accordingly, the access time of the internal RAM 305 restricts the clock frequency from increasing. As described above, since the clock frequency cannot be increased, the frequency of the data transfer clock for the arbitration block 303 cannot be increased, resulting in a problem that the transfer efficiency is reduced.

It is, therefore, an object of the present invention to provide a memory interface and a data processing device capable of preventing a decrease in data transfer efficiency caused by a delay caused by inputting / outputting via a flip-flop.

Another object of the present invention is to provide a memory interface and a data processing device capable of preventing a decrease in data transfer efficiency caused by a long access time of an internal RAM.

[0027]

In order to solve the above-mentioned problems, a first aspect of the present invention provides a memory interface in which a signal processing block accesses a memory via an arbitration block. The arbitration block gives a busy signal indicating a period during which the memory can be accessed and a period during which the memory cannot be accessed to the signal processing block, and the signal processing block accesses the start signal indicating the start of the address and data. A memory interface, which occurs prior to indicating a possible period, and wherein the arbitration block performs processing in response to the start signal when the busy signal can be accessed, assuming that the start signal has arrived. It is. According to a second aspect of the present invention, there is provided a data processing apparatus including the memory interface according to the first aspect.

According to a third aspect of the present invention, in a memory interface in which access to a memory from a signal processing block is performed through an arbitration block, when a write operation is performed on the memory, a period during which the memory can be accessed and a period during which the memory cannot be accessed are defined. The arbitration block gives the busy signal to the signal processing block, and the signal processing block
Data is read from an internal memory in synchronization with a first clock, and the read data is supplied to an arbitration block in synchronization with a second clock having a frequency that is an integral multiple of the first clock. Is a memory interface. According to a fourth aspect of the present invention, there is provided a data processing apparatus including the memory interface according to the third aspect.

According to the first and second aspects of the present invention, the start signal indicating the position of the write data and the address is generated before the busy signal goes to a low level (accessible period). If the start signal is at the high level when the busy signal is lowered to the low level, it is processed as if the start signal has arrived. Therefore, it is possible to prevent the occurrence of data vacancy due to the interposition of the flip-flop for the input and output of the busy signal.

According to the third and fourth aspects of the present invention, the internal RA
When the access time of M is long, the RAM is read with the first clock clock2, and the read data is sampled by the flip-flop, so that the second clock clock1 having a frequency twice as high as that of the first clock is used. Synchronous transfer to arbitration block. Thereby, a RAM with a long access time can be used. In other words,
A clock faster than the operating speed of the RAM can be used for the interface.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital VTR employing an inter-block interface according to the present invention will be described below. Prior to the description of the digital VTR, FIG.
This will be described with reference to FIG. 1, 2 and 3
FIG. 3 is a block diagram used to explain an inter-block interface.

1 and 2, reference numeral 311 denotes an internal block, and reference numeral 314 denotes an SDRAM as a main memory accessed by the internal block 311. SD
The RAM 314 is shared by a plurality of internal blocks that respectively process a plurality of data such as video data and audio data. The internal block 311 is one of the blocks. S from multiple internal blocks
Since an access request to the DRAM 314 may collide, the arbitration block 313 is provided between the plurality of internal blocks and the SDRAM 314. Internal block 3
11 is one of a plurality of internal blocks. A data bus and a control bus are provided between the arbitration block 313 and the SDRAM 314.

To perform efficient access to the SDRAM 314, the arbitration block 313 receives the write request from the internal
It is necessary to supply write data so that no space is generated in data transferred on the bus. When the arbitration block 313 cannot process an access request from another internal block, the state is changed to the internal block 3.
11 need to be taught. A busy signal is used as a signal for that purpose. If the busy signal is at a high level, for example, it is defined as a period during which the SDRAM cannot be accessed.

The internal block 311 generates a burst start signal, which is an access start signal. The start position of the write address and the start position of the write data are indicated by the burst start signal. Following the address, write data is supplied from the internal block 311 to the arbitration block 313. As an example, each of the busy signal and the burst start signal is 1 bit, the address bus is 21 bits wide, and the data bus is 32 bits wide.

FIG. 1 shows that the internal block 311 is an SDRAM.
3 shows a configuration when data is written to 314. With reference to FIG. 1, a first example of an inter-block interface according to the present invention will be described. FIG. 2 shows a configuration in which the internal block 311 has a RAM 315 therein. Data read from the RAM 315 is supplied to the arbitration block 313 via the flip-flop 316. FIG. 3 shows an inter-block interface when an internal block is configured as shown in FIG. A second example of the inter-block interface according to the present invention will be described with reference to FIGS.

A first example of the inter-block interface of the present invention applied to the configuration of FIG. 1 will be described with reference to the timing chart of FIG. FIG. 4A shows a clock signal as a timing reference, a burst start signal, and an address. Internal block 311
Sends a burst start signal, address and data to the arbitration block 313. The burst start signal indicates the start of a burst, that is, the position of an address and data. The address is 21 bits wide, and one of the four banks is specified by the upper two bits.

FIG. 4B shows the internal block 3 during a write operation.
11 illustrates an interface between the H.11 and the arbitration block 313. During a write operation, the internal block 311
Supplies write data to the arbitration block 313.
Eight words of D0 to D7 are one burst, and when the writing of one burst is completed, the burst start signal and the address are changed from the internal block 311 to the arbitration block 3 again.
13, the bank is switched, and 8 words of the next burst are written to another bank. During the write operation, the internal block 311 is at a high level, and during that period, a busy signal indicating that access is not possible is supplied to the internal block 311. When the busy signal goes low, the next burst start signal and address are
13. And the arbitration block 313 and SD
Write data is generated on the SDRAM bus between the RAMs 314 after a time delay of the number of clocks according to the configuration of the arbitration block 313.

FIG. 4B is a timing chart of desirable control, as in FIG. 24B. However, as described above, when transmitting the busy signal and the burst start signal between the internal block 311 and the arbitration block 313,
To stabilize the timing, flip-flops are provided on each of the side outputting these signals and the side receiving these signals. Therefore, the burst start signal and address generated from the internal block 311 are two clocks. As a result, the data transmitted between the internal block 311 and the arbitration block 313 has a vacancy of two clocks between the data of the bank A and the data of the next bank B.

FIG. 4 shows a state in which other internal blocks are not processed, that is, the operation at the maximum speed. If other internal blocks are being processed,
The length of the busy signal is longer than that shown in FIG.

In the first example of the inter-block interface according to the present invention, the internal block 311 is expected to output data to the arbitration block 313, instead of lowering the busy signal to low before accessing. In this case, in the section where the busy signal is at the high level, the burst start signal is set to the high level in advance, and the address is also output. And the internal block 311
When the busy signal drops, lower the burst start signal,
If the burst start signal is at a high level when the busy signal output by itself is lowered, the arbitration block 313 determines that the burst start signal has arrived and performs processing.

FIG. 4C shows the timing of such a first example. The busy signal in FIG.
From the internal block 311,
When 1 receives this busy signal at the flip-flop, the busy signal is taken into the internal block 311 one clock later as shown in FIG. 4C.

The internal block 311 is shown in FIG.
As indicated by reference numeral 320, in a section in which the busy signal is at a high level, the burst start signal is set to a high level in advance, an address is also output, and when the busy signal drops to a low level, the burst start signal also drops to a low level. . When the burst start signal falls to a low level, the head word D0 of the burst is output.

The burst start signal is output to the arbitration block 313 with a delay of one clock by passing through a flip-flop as indicated by 321. The arbitration block 313, as indicated by reference numeral 322 in FIG.
As indicated by 323, if the received burst start signal is at a high level, it is recognized that the received burst start signal is a burst start signal.
322 and 323 are the same timing defined by the clock. At this next clock timing, even if the burst start signal is at a high level, it is ignored.

By controlling in this way, FIG.
Since the burst start signal is processed two clocks earlier than the method shown in the timing chart of FIG.
It is possible to prevent the data sent from the internal block 311 to the arbitration block 313 from becoming empty. Note that the burst start signal can be set to a high level in advance for the very first data.

Next, a second example of the inter-block interface according to the present invention will be described. As in the configuration shown in FIG. 2, data of an internal block to be written to the SDRAM 314 is stored in the internal RAM 315, and when data is read therefrom and output to the SDRAM 314, a circuit such as a flip-flop is used. R
Since the access speed of the AM 315 is low, there is a possibility that continuous reading with a clock cannot be performed. Internal RAM 31
5 is a synchronous RAM. In large ASICs, RA
In order to improve the operating speed of M, a clock synchronous RA
M is adopted. Data is read from the address given to the internal RAM 315, and the read data is transferred to the arbitration block 3 via the flip-flop 316.
13 is output.

As described with reference to FIG. 26E, if the access time of the internal RAM 315 is long, valid data cannot be read from the internal RAM 315.
Therefore, depending on the access time of the internal RAM 315,
Higher clock frequencies were constrained. Since the clock frequency cannot be increased in this manner, the frequency of the data transfer clock for the arbitration block 313 cannot be increased, resulting in a problem that the transfer efficiency is reduced.

The second example is to solve such a problem. As shown in FIG. 2, when the internal RAM 315 has a long access time, the internal RAM 315 has a half of the frequency of the clock clock1 for the flip-flop 316.
Is supplied to the internal RAM 315, and data is read from the internal RAM 315 in synchronization with the clock2. Also, as shown in FIG. 3, a burst type signal is newly provided on the interface between the internal block 311 and the arbitration block 313. The high level of the burst type signal indicates that data is interfaced every two clocks. The high level / low level of the burst type signal is determined by the value when the burst start signal is at the high level.

FIG. 5 shows the second block interface.
6 is a timing chart showing the operation of the example. FIG. 5A shows a clock clock2, and FIG. 5B shows an address that changes in synchronization with the clock clock2. As shown in FIG. 5C, since the access time of the internal RAM 315 is long, the read data D corresponding to the addresses A0, A1, A2,.
0, D1, D2,... Occur in the latter half of one cycle of the clock clock2. This read data is sampled in the flip-flop 316 by the clock clock1 shown in FIG. 5D. Therefore, flip-flop 3
From 16, as shown in FIG. 5H, data output once every two clocks of clock 1 is supplied as write data. Clock1 by flip-flop 316
Is delayed by one cycle. Flip-flop 316
Is supplied to the arbitration block 313 as write data.

At the same timing as the burst start signal shown in FIG. 4F, the burst type signal is set to the high level as shown in FIG. 4E, and the write address is generated as shown in FIG. 4G. Since the burst type signal is high when the burst start signal is high, the arbitration block 313
Can be identified as valid every two clocks.

The burst type signal is transmitted to the internal block 311.
Interface between the internal block 311 and the arbitration block 313, so that the data supplied from the internal block 311 to the arbitration block 313 is dynamically set for each clock or every two clocks in accordance with the access time of the internal RAM 311. it can. If the access time of the internal RAM 315 is always slow, there is no need to supply a burst start signal to the arbitration block 313. Note that the arbitration block 313 has a RAM to enable high-speed processing.
Instead of having a flip-flop buffer,
Data can be continuously output to the SDRAM 314 via the flip-flop.

Since a plurality of internal blocks are connected to the arbitration block 313, if one of the internal blocks has a long access time to the internal RAM 315, the clock frequency cannot be increased, and the internal RA
Internal RAM without M or short access time
Therefore, there is a problem that the frequency of the clock for transferring data from another internal block having the above to the arbitration block 313 cannot be increased, resulting in a decrease in transfer efficiency. However, according to the second example of the inter-block interface of the present invention, clock1 having a high frequency can be used as a data transfer clock between the internal block and the arbitration block, and such a problem does not occur.

In the above description, the high level of the burst type signal is transferred once every two clocks.
The transfer can be realized as a transfer once every four clocks or the like. Also, clock2, which is obtained by dividing clock clock1 by １ ／, is given to the internal RAM.
Even if the same clock as that of ock1 is applied, the same control can be performed by controlling the enable signal. Further, the number of bits of the address and the number of bits of the data are not limited to the values described above.

A digital VTR employing the above-described inter-block interface according to the present invention will be described below. This digital VTR is suitable for use in a broadcasting station environment, and enables recording and reproduction of video signals of a plurality of different formats. For example, in an interlaced scan based on the NTSC system, a signal (480i signal) having 480 effective lines and a PAL
57 effective lines in interlaced scanning based on
Both of the six signals (576i signals) can be recorded and reproduced with almost no hardware change. Further, a signal having 1080 lines (1080i signal) in interlaced scanning, and 480, 720 and 1 in progressive scanning (non-interlaced), respectively.
080 signals (480p signal, 720p signal, 108
0p signal) can also be recorded and reproduced.

In a digital VTR, a video signal and an audio signal are compression-coded based on the MPEG2 system. As is well known, MPEG2 is a combination of motion compensated prediction coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP (Group Of Pictur)
e) layer and sequence layer.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock predicting the future from the past, and backward (Backward) interframe prediction macroblock predicting the future from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP contains at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not provided with the identification codes arranged in byte units.

The macro block is composed of one screen (picture).
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. Considering this point, one GO
P is composed of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame of a predetermined length.

FIG. 6 shows an example of the configuration on the recording side of a digital VTR. At the time of recording, a digital video signal is input from a terminal 101 via a receiving unit of a predetermined interface, for example, SDI (Serial Data Interface). SD
I is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals and additional data. The input video signal is subjected to DCT (Discrete Cosine Transform) processing in the video encoder 102, converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to the stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the overflow portion that protrudes from the fixed frame is sequentially packed into an area that is vacant with respect to the size of the fixed frame. Further, system data such as a time code is supplied from the input terminal 108 to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

Video data and system data from the packing and shuffling unit 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to a shuffling unit 110, and shuffling is performed so that the order is changed in units of sync blocks over a plurality of ECC blocks. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling performed by the shuffling unit 110 may be referred to as interleaving. The output of the shuffling unit 110 is supplied to the mixing unit 111 and mixed with the audio data. The mixing unit 111 is configured by a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In the digital VTR of this example, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown).
Alternatively, the data is separated by the SDTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to the AUX adding unit 114 via the delay unit 113. Delay unit 113
Is for time alignment of audio and video signals. Audio AU supplied from input terminal 115
X is auxiliary data, which is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX except when necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be subjected to scramble processing as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 7 shows an example of the configuration on the reproduction side of a digital VTR. Rotating head 122 from magnetic tape 123
Is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detection block 132 is supplied to the inner code encoder 133, and the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 13
The ID of the sync block, which has been supplied to the block No. 4 and made an error by the inner code, for example, a sync block number is interpolated. I
The output of the D interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to the reverse processing of the shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code (unequal length data) is restored. Further, in the deshuffling and depacking section 138, the system data is separated and taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain point onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

Further, for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is ensured in accordance with the maximum length of the macroblock as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. SDTI transmission unit 1
The system data, reproduced audio data, and AUX are also supplied to 44, although the path is not shown.
It is converted into a stream having a data structure of the I format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 6 and 7, a timing generator for generating a timing signal synchronized with input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In a digital VTR, signals are recorded on a magnetic tape by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 8 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and the audio signal can also be recorded in the same tape format as in FIG.

One segment is constituted by two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 8, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is arranged between the video sectors. FIG. 8 and FIG. 9, which will be described later, show the arrangement of audio sectors on a tape.

In the track format of FIG. 8, audio data of eight channels can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 8, since one field of audio data is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data (including the outer code parity) of the two ECC blocks is divided into four sectors, and FIG.
As shown in (1), the data is recorded separately on four tracks. 2
A plurality of sync blocks included in the ECC blocks are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, the video data is shuffled (interleaved) for four ECC blocks for one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 8, SAT1 (Tr) and SAT2 (Tm) are areas in which servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 8 shows an example in which data per frame is recorded on eight tracks. However, depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 9A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 9B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 9C schematically shows the configuration of a sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 9B) to form, for example, a video sector (FIG. 9A).

FIG. 10 shows the minimum unit of recording / reproduction.
A data structure of a sync block of video data will be shown more specifically. In a digital VTR, one or two macroblocks of data (VL) for one sync block are adapted to the format of video data to be recorded.
C data) and the length is changed according to the format of the video signal handled by the size of one sync block. As shown in FIG. 10A, one sync block is a 2-byte SYNC pattern from the beginning, a 2-byte ID, a 1-byte DID, for example, 112 bytes to 2 bytes.
Data area variably defined between 06 bytes and 1
It consists of a 2-byte parity (inner code parity). Note that the data area is also called a payload.

The first two-byte SYNC pattern is for synchronization detection and has a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 11A shows an example of the bit assignment of ID0 and ID1. The ID has important information unique to the sync block, and has 2 bytes (I
D0 and ID1) are assigned. ID0 is
The identification information (SYNC ID) for identifying each of the sync blocks in one track is stored. SYN
The C ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

[0100] ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 11B shows an example of bit assignment of DID in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 11C shows an example of bit assignment of DID in the case of audio. Bits 7 to 4 are
Reserved. Whether the data stored in the payload in bit 3 is audio data,
Indicates whether the data is general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data. Bit 2 to bit 0 correspond to 5 in the NTSC system.
Field sequence information is stored. That is,
In the NTSC system, the sampling frequency of an audio signal for one field of a video signal is 48 k.
In the case of Hz, it is either 800 samples or 801 samples, and this sequence is prepared every 5 fields.
Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 10, FIGS. 10B to 10E show examples of the above-mentioned payload. FIGS. 10B and 10C show examples in which video data (unequal length data) of 1 and 2 macroblocks is stored in the payload, respectively. In the example shown in FIG. 10B where one macroblock is stored, a data length indicator LT indicating the length of unequal-length data corresponding to the macroblock is arranged in the first three bytes. The data length indicator LT
May or may not include its own length. In the example shown in FIG. 10C in which two macroblocks are stored, the data length indicator LT of the first macroblock is arranged at the beginning, and the first macroblock is arranged subsequently. Then, after the first macroblock, the second macroblock
, A data length indicator LT indicating the length of the macro block is arranged, followed by a second macro block. The data length indicator LT is information necessary for depacking.

FIG. 10D shows an example in which video AUX (auxiliary) data is stored in the payload.
The first data length indicator LT describes the length of the video AUX data. Subsequent to the data length indicator LT, 5 bytes of system information, 12 bytes of PICT information, and 92 bytes of user information are stored. The remaining portion of the payload length is reserved.

FIG. 10E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In the digital VTR of this example, the length of the payload, which is the data storage area of each sync block, is optimally set for the video sync block and the audio sync block. Absent. In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 12A shows a DCT of an MPEG encoder.
4 shows the order of DCT coefficients in video data output from the circuit. Starting from the upper left DC component in the DCT block, DCT coefficients are output in a zigzag scan in the direction in which the horizontal and vertical spatial frequencies increase. As a result, as shown in an example in FIG. 12B, a total of 64 (8 pixels × 8 lines) DCT coefficients are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to the V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Accordingly, the variable-length coded output for the coefficient data of the AC component is obtained by converting AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

In the stream converter 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 13 shows the stream converter 10.
6 schematically shows the rearrangement of DCT coefficients in FIG.
In the case of a (4: 2: 2) component signal, one macroblock is composed of four DCT blocks (Y ₁ , Y ₂ , Y ₃ and Y ₄ ) based on a luminance signal Y and chromaticity signals Cb and C.
r, two DCT blocks (C
b ₁ , Cb ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 13A, DCT coefficients are arranged in order of frequency components from DC components and low frequency components to high frequency components for each DCT block. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

The stream converter 106 decodes the variable-length coded and arranged DCT coefficients once by decoding the variable-length code to detect a break of each coefficient, and extends the frequency over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 13B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are described with reference to FIG.
Each variable length code is assigned to a set consisting of a run and a subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 14 schematically shows a packing process of macroblocks in packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time matches the data length of the sync block, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 14, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 14A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of the data area of one sync block, which is a fixed frame, the data of the macro blocks # 1, # 3 and # 6 are longer, respectively.
The data of the macro blocks # 2, # 5, # 7 and # 8 are short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 14B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the portion (overflow portion) that protrudes from the sync block length is packed in an area that is vacant in order from the beginning, that is, after the macroblock whose length is less than the sync block length.

In the example of FIG. 14B, macro block # 1
The portion that is out of the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, a portion of the macro block # 6 that protrudes from the sync block length is packed behind the macro block # 7, and a portion that protrudes further from the macro block # 7.
Stuffed behind 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of the unequal length data corresponding to each macroblock can be checked in advance by the stream converter 106. As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 15 shows an example of an error correction code used in a digital VTR. FIG. 15A shows one ECC block of an error correction code for video data.
FIG. 15B shows one ECC block of an error correction code for audio data. In FIG. 15A, VLC
The data is data from the packing and shuffling unit 107. SYNC for each row of VLC data
One SYNC block is formed by adding a pattern, ID, and DID, and further adding an inner code parity.

That is, a 10-byte outer code parity is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID and VLC data (or external data) aligned in the horizontal direction are generated. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 15A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
In 5A, the difference in the length of VLC data in one SYNC block is 59.94 Hz, 25 Hz, and 23.97.
This is because the frame frequency of video data is different, such as 6 Hz.

As shown in FIG. 15B, the product code for audio data is similar to that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz, and one sample is quantized to 24 bits. One sample may be converted to another number of bits, for example, 16 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of the even-numbered and odd-numbered audio samples and the audio AUX as data.

FIG. 16 shows a more specific configuration of the recording side. In FIG. 16, reference numeral 164 denotes an interface of the main memory 160 external to the IC. The main memory 160 is composed of an SDRAM. The interface 164 controls a write / read operation of the main memory 160. The packing unit 107
a, video shuffling unit 107b, packing unit 10
7c, the packing and shuffling portion 107
Is configured.

FIG. 17 shows an example of the address configuration of the main memory 160. The main memory 160 is, for example, an SD
It is composed of RAM. The main memory 160 has a video area 250, an overflow area 251 and an audio area 252. The video area 250 includes four banks (vbank # 0, vbank # 1, and vbank # 2).
And vbank # 3). Each of the four banks can store digital video signals of one equal length unit. One equalization unit is a unit for controlling the amount of generated data to a substantially target value, for example, one picture (I
Picture). A part A in FIG. 17 shows a data part of one sync block of the video signal. Data of a different number of bytes is inserted into one sync block depending on the format (see FIG. 15A). In order to support a plurality of formats, the data size of one sync block is equal to or more than the maximum number of bytes and is a number of bytes convenient for processing, for example, 256 bytes.

Each bank in the video area is further divided into a packing area 250A and an area 250B for output to the inner encoding encoder. Overflow area 251
Consists of four banks corresponding to the above-mentioned video area. Further, the main memory 160 has an area 252 for audio data processing.

By referring to the data length indicator LT of each macroblock, the packing unit 107a separates the fixed frame length data and the overflow data that is beyond the fixed frame into separate areas 250 and 251 of the main memory 160. To remember. The fixed frame length data is data that is equal to or less than the length of the data area of the sync block.
This is called block length data. The area for storing the block length data is the packing processing area 250A of each bank. If the data length is shorter than the block length, an empty area is created in the corresponding area of the main memory 160. The video shuffling unit 107b performs shuffling by controlling the write address. Here, the video shuffling unit 107b shuffles only the block length data, and the overflow portion is written to the area assigned to the overflow data without shuffling.

Next, the packing section 107c performs processing of packing and reading the overflow portion into the memory for the outer code encoder 109. That is, 1 is prepared from the main memory 160 to the outer code encoder 109.
The data of the block length is read into the memory of the ECC block, and if there is a free area in the data of the block length, an overflow portion is read there to block the data to the block length. When the data for one ECC block is read, the reading process is temporarily suspended, and the outer code encoder 109 generates the parity of the outer code. The outer code parity is the outer code encoder 10
9 is stored in the memory. When the processing of the outer code encoder 109 is completed for one ECC block, the outer code encoder 1
From 09, the data and the outer code parity are rearranged in the order of performing the inner code, and are written back to the packing processing area 250A and another output area 250B of the main memory 160.
The video shuffling unit 110 performs shuffling on a sync block basis by controlling an address at the time of writing back the data on which the encoding of the outer code has been completed to the main memory 160.

As described above, the block length data and the overflow data are separated and the data is written into the first area 250A of the main memory 160 (first packing process), and the overflow data is packed into the memory of the outer code encoder 109. (The second packing process), the generation of the outer code parity, and the data and the outer code parity in the second area 250 of the main memory 160.
The process of writing back to B is performed in units of one ECC block.
Since the outer code encoder 109 includes the memory having the size of the ECC block, the frequency of access to the main memory 160 can be reduced.

Then, a predetermined number of Es included in one picture
When the processing of the CC block (for example, 32 ECC blocks) is completed, packing of one picture and encoding of the outer code are completed. The data read from the area 250B of the main memory 160 via the interface 164 is processed by the ID addition unit 118, the inner code encoder 119, and the synchronization addition unit 120, and the output data of the synchronization addition unit 120 is output by the parallel / serial conversion unit 124. Is converted to bit serial data. The output serial data is processed by the partial response class 4 precoder 125. This output is digitally modulated as necessary, and supplied to the rotary head via the recording amplifier 121.

It is to be noted that a sync block in which valid data called null sync is not arranged is introduced into the ECC block, and the ECC block is provided with an EC for the difference in the format of the recording video signal.
The flexibility of the configuration of the C block may be provided. The null sink is generated in the packing unit 107a of the packing and shuffling block 107,
Written to main memory 160. Therefore, since the null sync has a data recording area, it can be used as a recording sync for the overflow portion.

In the case of audio data, even-numbered samples and odd-numbered samples of one-field audio data constitute different ECC blocks. Since the ECC outer code sequence is composed of audio samples in the input order, the outer code encoder 116 generates an outer code parity each time an outer code sequence audio sample is input. The address control when writing the output of the outer code encoder 116 to the area 252 of the main memory 160 causes the shuffling unit 117 to perform shuffling (channel units and sync block units).

Further, a CPU interface indicated by 126 is provided, and C functions as a system controller.
It is possible to receive data from the PU 127. This data includes shuffling table data, parameters related to the format of the recording video signal, and the like. The shuffling table data is stored in a video shuffling table (RAM) 128v and an audio shuffling table (RAM) 128a. The shuffling table 128v performs an address conversion for shuffling the video shuffling units 107b and 110. Shuffling table 128a
Performs address conversion for audio shuffling 117.

The present invention relates to the main memory 160 described above.
Applies to access to Main memory 1
As 60, a 64 Mbit SDRAM is used. The specific specifications are as follows.

Total number of bits: 67108864 Bit width per word: 32 Number of banks: 4 Number of rows: 2048 Number of columns: 256 Burst (number of words): Select 8 out of 1, 4, 8 Total number of bits: It is the product of the number of banks, the number of rows, the number of columns, and the bit width.

The above specifications will be further described.
The fact that the bit width per word is 32 bits / word means that the size of data represented by one address is one word, that is, 32 bits (4 bytes).
Means that One row has 256 column addresses and 256 words, that is, 10
24 bytes can be stored. Further, the fact that the burst is 8 means that continuous data can be read / written in units of 8 words (= 32 bytes).

In the case of a recording device such as a digital VTR, the recording / reproducing operation is performed in units of sync blocks. In the recording / reproducing process, it is simplified to input / output video / audio data in sync block units. It is convenient for conversion. Digital VTR described above
Can cope with a plurality of formats, and the data of the sync block excluding the sync signal, ID, and inner code parity of the sync block does not exceed 256 bytes for both video data and audio data. In view of this, a configuration is adopted in which 256 bytes are used as logical breaks in the main memory 160 as well.

Although 256 bytes are treated as a logical unit (called a box) that can store one sync block, a new virtual address is introduced to improve the efficiency of access. The size of 256 bytes in one box is 64 words, which corresponds to 8 bursts. From such a relationship, as described below, the 256
Make up the bytes.

A burst (8 words / times) is performed in the column address (sdram col) direction. Since addressing of eight words in a burst is continuous, only the head address is specified.

If the burst continues a plurality of times, the bank (sdr
am bank). That is, when one burst is completed, the bank is switched.

When the four banks make one cycle, the column address is advanced. The above addressing is repeated.
When the column address is used up, the row address (sdram ro
w) Step forward one step.

FIG. 18 schematically shows data storage in the main memory 160 described above. FIG. 18A
, Each of the banks # 0 to # 3 has 256
Column addresses and 2048 row addresses. As shown in FIG. 18B, a number is assigned to a box on the main memory that stores the sync block, and the number is called an index (sdram index). In addition, it indicates the number of the burst in the index (sdram
burst) is introduced.

FIG. 18C shows the contents of an index, for example, # 0. 256 bytes of the box of one sync block (= 6
4 words) are eight bursts. First bank #
Eight words from head column address # 0 to # 7 are addressed by row # 0 of 0. Next, the bank is switched to # 1 in order to continuously address data in burst units. Similarly, data is stored in burst units. When the data storage up to bank # 3 is completed, the column address is advanced. That is, the head column address # 8 is designated, and similar data storage in burst units is performed. By eight burst units,
A box of one sink block is formed.

Regarding index 1, the head column address is set to # 16, and data is stored in the same manner as in FIG. 18C. Since the column addresses are # 0 to # 255, when a burst is performed with the column addresses # 248 to # 255, the process returns to # 0. At this time, the row address is advanced by one from # 0 to # 1.

The address (bank, row, column) described above, the index, and the physical quantity indicating the number of the burst within the index make it possible to address the main memory 160 based on the sync block number. The bank, row, and column addresses and indexes have the following relationship.

Sdram burst [2: 0] = ｛sdram col [3], sdra
m bank [1: 0]｝; sdram index [14: 0] = ｛sdram row [10: 0], sdram col [7:
4]｝; or conversely, sdram bank [1: 0] = sdram burst [1: 0],｝; sdram col [7: 0] = ｛sdram index [3: 0], sdram burst
[2], 3'b000｝; sdram row [10: 0] = sdram index [14: 4]; The lower 3 bits of sdram col are 3'b000 because the burst made in the column address direction is a word burst and the address is continuous.
This is because only the head address of the burst needs to be managed. The bank, row, and column addresses determined in this way are linked to form a virtual address (interface address) mprm adrs [20: 0] of the main memory 160.

Mprm adrs [20: 0] = ｛sdram bank [1: 0], sdra
m row [10: 0], sdram col [7: 0]}; FIG. 19 shows the correspondence between the bit numbers 0 to 20 of the linked virtual address and each address.

FIG. 18B shows the capacity of the main memory 160 as an index. The vertical axis represents the index, and the horizontal axis represents the burst direction for convenience. FIG. 18C shows the contents of one index with the burst direction as the vertical axis.

As shown in FIG. 17, both the audio data and the video data are roughly addressed by an index (sdram index) corresponding to a box of a sync block, and the data inside the data is a burst (sdram burst).
It is possible to indicate by using.

In the above-described digital VTR, the configuration related to the inter-block interface according to the present invention is the configuration on the recording side shown in FIG. Although not shown, the configuration on the reproduction side also employs the inter-block interface according to the present invention. The correspondence between FIG. 1 and FIG. 16 will be described. SDRAM 314 and main memory 16
0 corresponds, and the arbitration block 313
4. The internal block 311 includes a video shuffling unit 107b, a packing unit 107c, a video shuffling unit 110, an audio shuffling unit 117, and an I / O unit connected to the interface 164.
D adding circuit 118.

The interface 164 arbitrates requests for the main memory 160 from these internal blocks, and controls write and read operations on the main memory 160. That is, the video shuffling unit 107
b, The video shuffling unit 110 and the audio shuffling unit 117 output data to the interface 164, and the packing unit 107c and the ID adding circuit 118 read the data via the interface 164. Each of the internal blocks in the configuration shown in FIG. 16 has a RAM inside.

An arbitration block provided in the interface 164 arbitrates accesses from these internal blocks. As described with reference to FIG. 1 to FIG. Is controlled so that there is no empty space, and furthermore, even if the access time of the internal RAM is long, the frequency of the transfer clock of the inter-block interface can be prevented from being lowered.

The present invention is not limited to a digital VTR, but can be applied to a data processing device having a configuration in which an arbitration block is interposed between a plurality of internal blocks and a memory.

[0154]

According to the first and second aspects of the present invention, the arbitration block generates the start signal indicating the position of the write data and address before the busy signal becomes low level (accessible period). If the start signal is at a high level when the output busy signal is lowered to a low level, it is processed as if the start signal has arrived. Therefore, for the input and output of the busy signal,
It is possible to prevent the occurrence of empty data due to the interposition of the flip-flop. Thereby, access to the SDRAM can be performed continuously, and the access efficiency can be improved.

According to the third and fourth aspects of the present invention, the internal RA
When the access time of M is long, the RAM is read with the first clock clock2, and the read data is sampled by the flip-flop, so that the second clock clock1 having a frequency twice as high as that of the first clock is used. Synchronous transfer to the arbitration block. Thereby, a RAM with a long access time can be used. Usually, a RAM with a slow access speed consumes less power, and has the advantage of using such a RAM in reducing the power consumption of an IC. Stated another way, a clock faster than the operating speed of the RAM can be used for the interface.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first example of an inter-block interface according to the present invention.

FIG. 2 is a block diagram for explaining a second example of the inter-block interface according to the present invention;

FIG. 3 is a block diagram for explaining a second example of the inter-block interface according to the present invention;

FIG. 4 is a timing chart for explaining a first example of an inter-block interface according to the present invention;

FIG. 5 is a timing chart for explaining a second example of the inter-block interface according to the present invention;

FIG. 6 is a block diagram showing a configuration of a recording side of a digital VTR employing an inter-block interface according to the present invention.

FIG. 7 is a block diagram showing a configuration on a reproduction side of a digital VTR employing an inter-block interface according to the present invention.

FIG. 8 is a schematic diagram illustrating an example of a track format.

FIG. 9 is a schematic diagram illustrating another example of a track format.

FIG. 10 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 11 shows an ID and DI added to a sync block.
It is a schematic diagram which shows the content of D.

FIG. 12 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 13 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 14 is a schematic diagram for explaining a process of packing data whose order is rearranged into a sync block.

FIG. 15 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 16 is a more specific block diagram of a recording signal processing unit.

FIG. 17 is a schematic diagram illustrating a memory space of a memory to be used.

FIG. 18 is a schematic diagram for explaining addressing of a memory;

FIG. 19 is a schematic diagram for explaining a virtual address.

FIG. 20 is a timing chart for explaining one example and another example of a memory access.

FIG. 21 is a block diagram for explaining a conventional inter-block interface to which the present invention can be applied.

FIG. 22 is a block diagram for explaining a first problem of the conventional inter-block interface.

FIG. 23 is a block diagram for explaining a second problem of the conventional inter-block interface.

FIG. 24 is a timing chart for explaining a conventional inter-block interface.

FIG. 25 is a timing chart for explaining a first problem of the conventional inter-block interface.

FIG. 26 is a timing chart for explaining a second problem of the conventional inter-block interface.

[Explanation of symbols]

107 ... packing and shuffling part, 10
9, 116 ... outer code encoder, 110, 117
..Shuffling section, 118... ID adding section, 120
... Synchronization adding unit, 160 ... Main memory, 311
... Internal block, 313 ... Arbitration block, 31
4: SDRAM, 316: flip-flop

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (7)

[Claims] In a memory interface in which a signal processing block accesses a memory via an arbitration block, when a write operation is performed on the memory, a busy signal indicating a period during which the memory can be accessed and a period during which the memory cannot be accessed are provided. The arbitration block provides to the signal processing block, wherein the signal processing block generates a start signal indicating the start of address and data before indicating a period in which the busy signal can be accessed, and the arbitration block includes: A memory interface which performs processing in response to the start signal assuming that the start signal has arrived at a time when a busy signal can be accessed. 2. A memory, a plurality of signal processing blocks,
In a data processing device having an arbitration block for arbitrating access to a memory from each of a plurality of signal processing blocks, when performing a write operation on the memory, a busy signal indicating a period during which the memory can be accessed and a period during which the memory cannot be accessed is provided. The arbitration block provides to the signal processing block, wherein the signal processing block generates a start signal indicating the start of address and data before indicating a period in which the busy signal can be accessed, and the arbitration block includes: A data processing apparatus comprising: a memory interface configured to perform processing in response to the start signal when the start signal arrives when a busy signal can be accessed. 3. A memory interface in which a signal processing block accesses a memory via an arbitration block. When a write operation is performed on the memory, a busy signal indicating a period during which the memory can be accessed and a period during which the memory cannot be accessed are provided. An arbitration block provides the signal processing block with the signal processing block. The signal processing block reads data from an internal memory in synchronization with a first clock and converts the read data to a signal having a frequency that is an integral multiple of the first clock. A memory interface for supplying to the arbitration block in synchronization with a second clock. 4. A memory, a plurality of signal processing blocks,
In a data processing device having an arbitration block for arbitrating access to a memory from each of a plurality of signal processing blocks, when performing a write operation on the memory, a busy signal indicating a period during which the memory can be accessed and a period during which the memory cannot be accessed is provided. An arbitration block provides the signal processing block with the signal processing block. The signal processing block reads data from an internal memory in synchronization with a first clock and converts the read data to a signal having a frequency that is an integral multiple of the first clock. A data processing device comprising a memory interface adapted to supply the arbitration block in synchronization with a second clock. 5. The burst according to claim 1, wherein the memory has a plurality of banks, each of which is specified by a row and column address and accessed in units of a plurality of words. An apparatus, wherein digital information data is input or output in the unit described above. 6. The method according to claim 1, wherein the plurality of signal processing blocks and the arbitration block are I
C. wherein the memory is connected outside of the IC. 7. The device according to claim 3, wherein the memory inside the signal processing block is of a synchronous type in which data is read in synchronization with a clock.