JP2000134110A - Data transmitter and transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmitter that can prevent a defective image due to a header error without the need for multiple recording and to provide a data transmission method. SOLUTION: This data transmitter receives a recovered stream NXPB and an error flag ERR. A header detection circuit 12 detects a header in the received stream to generate a detection signal. A RAM 13 stores only the data with a header, having no error based on an output of an AND gate 15. A selector 11 is controlled by an output of an AND gate 14, and when there is an error in a header of the received stream, the erroneous part is replaced with header data without errors read from the RAM 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus and a data transmission method applied to, for example, recording compressed image data on a recording medium and reproducing the image data from the recording medium.

[0002]

2. Description of the Related Art Digital VCR (VIdeo Cassette Reco)
A data recording / reproducing apparatus which records a digital image signal on a recording medium and reproduces the digital image signal from the recording medium, as typified by rder), is known. In the case of a digital image signal, since the amount of information is large, the data amount is compressed.
As encoding for compressing the data amount of moving image data, for example, motion compensation prediction encoding between screens (frames) is well known. MPEG2 (Moving
Picture Experts Group Phsse 2) is well known.

When recording and reproducing picture data conforming to the MPEG2 standard, an elementary stream (E
S), packetized elementary stream (PE
S) and transport stream (TS) can be recorded and reproduced. The elementary stream is a bit stream output from the encoder, and includes an access unit corresponding to a video frame. The packetized elementary stream is a packetized elementary stream, and each packet has a PES
Contains the header. Further, the transport stream is divided into packets having a length of 188 bytes, and the data of the packetized elementary stream is divided into each packet. Each packet includes a transport stream header.

[0004] The data structure of MPEG has a hierarchical structure. The highest layer is the sequence layer.
Below the sequence layer, a GOP layer, a picture layer, a slice layer, a macroblock layer, and a block (DCT block) layer are defined, and data included in each layer is also defined. The lowest block layer is DCT (D
It includes DCT coefficient data generated by iscrete cosine transform. The macro block is composed of four luminance signal blocks and one or two color difference signal blocks. Therefore, one macroblock includes a total of 6 or 8 blocks of coefficient data. The coefficient data is variable-length coded. Macroblock information such as a macroblock type is added to the variable-length-coded macroblock data.

When recording and reproducing an elementary stream, it is necessary to record headers such as a picture header, a GOP header, and a sequence header in addition to the data of each macroblock of variable length. After all, when recording an elementary stream, a packetized elementary stream, and a transport stream, a header and variable-length encoded coefficient data are recorded. Data having image information, such as variable-length-coded coefficient data, is called picture data.

As described above, when recording and reproducing an MPEG2 stream, it is necessary to record both the header and the picture data. The header contains image frame information (horizontal / vertical size, aspect ratio), frame frequency information,
User data and the like are stored. Therefore, when an error occurs in the header in the process of recording and reproducing, the entire corresponding picture data cannot be correctly decoded, and the reproduced image is likely to be broken. On the other hand, picture data is
Since the image data is divided into information related to a part of the image (macroblock, 16 × 16 pixels), even if an error occurs in the picture data, the influence is small compared to the header.

Generally, when digital data is recorded on a tape and reproduced from the tape, it is assumed that an error occurs at a certain rate, and an error correction code having a performance sufficient to counter this error is assumed. Is used. That is, as shown in FIG. 15, the ECC encoder 201 on the recording side records data on the tape by adding information bits (redundant data necessary for correction) to the check bits (actual data) and records the data on the tape. The ECC decoder 202 detects the presence / absence of an error using both the check bit and the information bit, and corrects the error when there is an error.

[0008]

However, an error may occur at a rate higher than expected or the error may not be corrected by the error correction code depending on the position of the bit where the error occurred. This is a state called error omission or error correction impossible. When an error that cannot be corrected occurs in the header portion as described above, as described above,
There is a high possibility that the image will break down over the entire picture related to the header.

[0009] In order to solve this problem, a technique for reducing the probability of occurrence of error omission in the header as compared with the picture data has conventionally been adopted. For example, a method is employed in which only the header is double- and triple-recorded on the tape.

However, the method of multiplex-recording the header still has a problem that an error may still be lost and the recording capacity for picture data on the tape may be reduced.

It is therefore an object of the present invention to provide a data transmission apparatus and a data transmission method which can prevent an image from being broken by an error in a header without performing multiplex recording.

[0012]

According to a first aspect of the present invention, there is provided a data transmission apparatus for transmitting a header and picture data, comprising: an encoding means for encoding the header with an error correction code; and an output data of the encoding means. Sending means for sending to the transmission path; receiving means for receiving data encoded by the error correction code passing through the transmission path; and header and picture data by receiving the received data and decoding the error correction code. Error correcting means for correcting the error of the header, a header detecting means for detecting a header in the output data of the error correcting means, and a header detected by the header detecting means. A memory means that writes only the headers that are determined to be missing, and a header that has an error in the output data of the error correction means. To select the header stored in the memory means Te, a data transmission apparatus characterized by comprising a selection means controlled by the error flag.

According to an eighth aspect of the present invention, in a data transmission method for transmitting a header and picture data, a step of encoding the header with an error correction code, a step of transmitting the encoded data to a transmission path, Receiving data encoded by the error correction code passing through the path, receiving the received data, and decoding the error correction code to correct errors in the header and picture data; Only the header detection step of detecting a header in the data after error correction and the detected header, and only the header determined as having no error by the error flag generated in the error correction step are written to the memory means. Step and storing in the memory means in place of the header which is an error in the output data after error correction. To select a header that is a data transmission method characterized by comprising the steps that are controlled by the error flag.

The header is detected, and only the header that is not error-free is stored in the memory. If the header contains an error, the error-free header stored in memory replaces the error-containing header. Therefore, it is possible to prevent a received (reproduced) image from being broken due to an error in the header. Further, since the header is not multiplex-recorded or transmitted repeatedly, there is no problem that the recording capacity is reduced or the transmission data rate is increased due to the multiplex recording or repeated transmission.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described with reference to digital VC.
An embodiment applied to R will be described. This embodiment is suitable for use in a broadcast station environment,
Video signals of a plurality of different formats are handled in a unified manner. For example, a signal having 480 effective lines (480i signal) in the interlaced scanning based on the NTSC system and a signal having 576 effective lines (576i signal) in the interlaced scanning based on the PAL system are unified. Will be Furthermore, the number of lines is 1
080 signals (1080i signals) and 480 lines in progressive scanning (non-interlace)
, 720, 1080 signals (480p signal, 72
0p signal, 1080p signal) and the like are unified.
That is, video signals of different formats can be recorded and reproduced by almost common hardware.

In this embodiment, a video signal and an audio signal are compression-coded based on the MPEG2 system. As is well known, MPEG2 is a combination of motion compensated prediction coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer,
A slice layer, a picture layer, a GOP layer, and a sequence layer are provided.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I picture (Intra-coded picture) uses information that is closed only in one picture when it is encoded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as a macro block type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock that predicts the future from the past, and backward (Backward) interframe prediction macroblock that predicts the past from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of the sequence layer, GOP layer, picture layer, slice layer, and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

A macroblock is a screen (picture) of 1
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices.

In the MPEG2 system, decoding is not possible as image data unless data is arranged at least in macroblock units. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal degradation due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is made equal in length so that data generated in one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration of a recording / reproducing apparatus 100 according to this embodiment. First, this configuration will be schematically described. At the time of recording, a digital video signal is input from a terminal 101 via a predetermined interface, for example, an SDI (Serial Data Interface) receiving circuit. S
DI uses SMPTE to transmit (4: 2: 2) component video signals and digital audio signals.
The interface specified by. The input video signal is variable-length coded by the MPEG encoder 102 and output as variable-length coded (VLC) data. This data is an elementary stream conforming to MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, the terminal 104 is an ANSI / SMPTE 305M so that various formats can be included.
SDTI, the interface specified by
(Serial Data Transport Interface) format data is input. From the terminal 104, a signal including an MPEG2 elementary stream is input. This signal is synchronously detected by the SDTI receiving circuit 105. Then, the elementary stream is temporarily stored in the buffer, and the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. As described later, the stream converter 1
In step 06, the DCT coefficients arranged for each DCT block based on the rules of MPEG2 are grouped for each frequency component through a plurality of DCT blocks constituting one macroblock, and the grouped frequency components are rearranged. The rearranged converted elementary streams are stored in the packing circuit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing circuit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. The packed data is supplied to an ECC (Error Correcting Code) encoder 108.

The ECC encoder 108 is supplied with the packed video signal and, for example,
9 supplies a digital audio signal. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is input to the SDI
Receiving circuit (not shown) or SDTI receiving circuit 105
And compensates for the delay that occurs in the processing of the video signal.

In the ECC encoder 108, shuffling is performed for each sync block. By performing shuffling, data is uniformly arranged with respect to the pattern on the tape. By performing shuffling, it is possible to increase the resistance to burst errors that occur at continuous positions on the tape.

When shuffling is performed, an outer code parity and an inner code parity are added in a predetermined data unit (symbol), and error correction encoding using a product code is performed. First, an outer code parity is added through a predetermined number of blocks, and then, for each of the blocks including the outer code parity, an inner code parity is added in the block direction. The inner code parity is added in units of an inner code block composed of the same data sequence as the fixed frame used at the time of packing. SYNC for detecting synchronization with respect to the error-corrected encoded data
ID for identifying a pattern, sync block, and DID indicating information on the content of data to be recorded
Is added.

A data block completed by the inner code parity and the outer code parity is called an error correction block.

The error correction encoded data from the ECC encoder 108 is scrambled by a scramble circuit (not shown), and the frequency components are averaged. Then, it is supplied to the recording amplifier 110, recorded and encoded, and converted into a format suitable for recording on the magnetic tape 120. In this embodiment, a partial response precoder is used for recording and encoding. The recording-encoded data is recorded on the magnetic tape 120 by the recording head 111.

At the time of reproduction, the signal recorded on the magnetic tape 120 is reproduced by the reproduction head 130 and the reproduction amplifier 13
1 is supplied. The reproduction signal is subjected to equalization, waveform shaping, and the like by a reproduction amplifier 131, and is converted into a digital signal by a channel coding decoding circuit (not shown). The reproduction digital signal output from the reproduction amplifier 131 is
Decoding of the partial response is performed. It is supplied to the ECC decoder 132.

In the ECC decoder 132, first, synchronization detection is performed based on the SYNC pattern added at the time of recording, and a sync block is cut out. Then, error correction is performed based on the error correction code added at the time of recording. When an error exists that exceeds the error correction capability of the error correction code, an error flag indicating a data block containing the error is set. And
Deshuffling is performed, and the data shuffled at the time of recording is rearranged in the original order.

The video data output from the ECC decoder 132 is supplied to a depacking circuit 133. The depacking circuit 133 disassembles the packing performed during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. here,
If the error flag is set by the ECC decoder 132, the concealing circuit (not shown) corrects the error data. Modification, for example, all data

[0]
This is done by filling in with the bits of, or replacing the data of the previous frame.

The output of the depacking circuit 133 is supplied to a header reproducing circuit 140. Header reproduction circuit 140
Is a circuit for reconstructing the header by using information taken immediately before when there is an uncorrectable error in the header. The header reproducing circuit 140 is a feature of the present invention, and will be described later in more detail.

The output data of the header reproducing circuit 140 is supplied to the stream converter 134. In the stream converter 134, the above-described stream converter 106
The reverse process is performed. That is, the DCT coefficients arranged for each frequency component through the DCT block are converted into DCT coefficients.
Rearrange every T blocks. As a result, the reproduced signal becomes M
It is converted into an elementary stream conforming to PEG2.

In the stream conversion processing on the reproduction side, it is necessary to perform error processing based on an error flag by outer code correction obtained by the ECC decoder 132 before conversion. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore,
For example, the data at the error location is replaced with a block end code (EO).
B), and the DCT coefficients of the frequency components thereafter are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data.

Through the DCT block, the DCT coefficient is D
Since the C component and the low frequency component are arranged from the high frequency component to the high frequency component, even if the DCT coefficients are ignored from a certain point onward, the DC and DC components of the DCT blocks constituting the macroblock are uniformly distributed. DCT coefficients from the low-frequency component can be distributed.

As for the input / output of the stream converter 134, a sufficient transfer rate (bandwidth) is secured in accordance with the maximum length of the macroblock, as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The ECC decoder 132 also performs audio data error correction. The audio data is taken out to the terminal 139 and supplied to the SDTI transmission circuit 135 or the SDI transmission circuit via a delay circuit (not shown) for adjusting the time with the processing of the video signal.

From the SDTI transmission circuit 135, the SDTI
Format data is output and taken out to the terminal 136. Also, by being supplied to the MPEG decoder 137, decoding based on the MPEG2 specification is performed, decoded into a digital video signal, and taken out to the output terminal 138. An SDI transmission circuit (not shown) is connected to the output terminal 138, and a digital audio signal is multiplexed with a digital video signal.

Although not shown in FIG. 1, a timing generating circuit for generating a timing signal synchronized with the input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. .

In this embodiment, recording of a signal on a magnetic tape is performed by a helical scan method in which an oblique track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 2 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and the audio signal can also be recorded in the same tape format as in FIG.

One segment is composed of two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 2, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged on both ends, and an audio sector in which audio data is recorded is arranged between the video sectors. FIG. 2 and FIG. 3, which will be described later, show the arrangement of sectors on the tape.

In this example, eight channels of audio data can be handled. A1 to A8
Indicates audio data channels 1 to 8 respectively. The audio data is recorded with its arrangement changed in segment units. In this example, in this example, data of four error correction blocks is interleaved for one track, and Upper Side and Low
It is divided into sectors of r Side and recorded. Lowe
In the video sector of r Side, a system area is provided at a predetermined position.

In FIG. 2, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 2 shows an example in which data per frame is recorded on eight tracks. Depending on the format of data to be recorded / reproduced, data per frame is recorded in four tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 3A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 3B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 3C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 3B) to form, for example, a video sector (FIG. 3A).

FIG. 4 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this embodiment, one or two macroblocks of data are stored for one sync block, and the length is changed according to the format of the video signal handled by the size of one sync block. . FIG.
As shown in A, one sync block starts from the beginning.
It consists of a 2-byte SYNC pattern, a 2-byte ID, and a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). The data area is
Also called payload.

The first two bytes of the SYNC pattern are for synchronization detection, and consist of a predetermined pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

The ID has important information inherent to the sync block, and two bytes (ID0 and ID1) are assigned to each ID. FIG. 5A shows an example of the bit assignment of ID0 and ID1. ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Indicates which of the video data and the audio data the sync block is.

The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. FIG. 5B
Shows an example of bit assignment of DID in the case of video. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 5C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 4, FIGS. 4B to 4E
Shows an example of the above-mentioned payload. 4B and 4C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 4B where one macroblock is stored, the first three bytes are provided with length information LT indicating the length of the following macroblock.
The length information LT may or may not include its own length. 4C shown in FIG. 4C.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.

FIG. 4D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT includes a video AU not including itself.
The length of the X data is described. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining part of the payload length is reserved.
It is said.

FIG. 4E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM (Pulse Code Modulation) format.
The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, since the length of the payload, which is the data storage area of each sync block, is optimally set for the video sync block and the audio sync block, they are not equal to each other. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

Next, each section of the recording / reproducing apparatus 100 will be described in more detail. FIG. 6 shows an example of the configuration of the MPEG encoder 102. MPEG encoder 1
The input component 150 of 02 receives a 4: 2: 2 digital component video signal. This signal is supplied to the MPEG encoder 102. When the input component signal is converted into a block
It is divided into macroblocks of pixels × 16 lines. This macro block is supplied to one input terminal of the subtractor 154 and is also supplied to the motion detection circuit 160. Further, the input signal is also supplied to the statistical processing circuit 152. The statistical processing circuit 152 calculates the complexity of the input image data by predetermined statistical processing. The calculation result is supplied to the bit rate control circuit 153.

In the motion detection circuit 160, the input image data supplied from the blocking circuit 151 and the image data of one frame before supplied through an inverse quantization circuit 163 and an inverse DCT circuit 162, which will be described later. In comparison, for example, motion information (motion vector) is obtained by block matching. The motion compensation circuit 161 performs motion compensation based on the motion information, and supplies the result of the motion compensation to the other input terminal of the subtractor 154.

The difference between the input image data and the motion compensation result is obtained by the subtractor 154 and supplied to the DCT circuit 155. The DCT circuit 155 further calculates the difference data by 8
The image is divided into DCT blocks each consisting of pixels × 8 lines, and DCT is performed on each DCT block. DCT
The DCT coefficient output from the circuit 155 is
It is quantized at 56. At the time of quantization, the quantization scale is controlled based on control information from the bit rate control circuit 153, thereby controlling the bit rate. The quantized DCT coefficient is supplied to the inverse quantization circuit 163 and the zigzag scan circuit 157.

From the zigzag scan circuit 157, the DC
The T coefficient is output by zigzag scan. That is, D
Each of the CT blocks is arranged in order from the DC component and the low frequency component to the high frequency component. This DCT coefficient is
The data is variable-length coded by the VLC circuit 158 and is extracted to an output terminal 159 as an elementary stream compliant with MPEG2.

FIG. 7 schematically shows processing in zigzag scan circuit 157 and VLC circuit 158. As shown in FIG. 7A, in the DCT block, the horizontal spatial frequency and the vertical spatial frequency are increased in the rightward and downward directions, for example, with the upper left as the DC component. In the zigzag scan circuit 157, starting from the upper left DC component,
In the direction where the horizontal and vertical spatial frequencies increase, DCT
Each DCT coefficient of the block is scanned zigzag.

As a result, as shown in an example in FIG. 7B, a total of 64 (8 pixels × 8 lines) DCT coefficients are obtained in the order of frequency components. This DCT coefficient is supplied to the VLC circuit 158, where it is subjected to variable length coding. That is, each coefficient is such that the first coefficient is fixed as a DC component, and from the next component (AC component), the coefficient is grouped by a zero run and a subsequent level, and one code is assigned. , Variable-length coding is performed. The variable-length coded output for the coefficient data of the AC component is represented by A (high-order) coefficient from a low (low-order) coefficient of the frequency component.
_{C 1, AC 2, AC 3} , in which aligned with ....

The information on the amount of generated data obtained at the time of variable length coding in the VLC circuit 158 is stored in the bit rate control circuit 1.
53. In the bit rate control circuit 153,
Bit rate control information is supplied to the quantization circuit 156 such that an appropriate bit rate is obtained at the output based on the encoded information and the calculation result of the complexity of the macroblock by the statistical processing circuit 152 described above. With this bit rate control information, the amount of data generated in a GOP (one frame) is fixed.

On the other hand, D supplied to the inverse quantization circuit 163
The CT coefficients are inversely quantized, decoded into image data by an inverse DCT circuit 162, and supplied to a motion detection circuit 160 and a motion compensation circuit 161.

In this embodiment, only I pictures are used, and P and B pictures are not used. Therefore, in the above-described configuration of the MPEG encoder 102, a configuration for performing motion compensation prediction between frames or fields, that is, a subtractor 154, an inverse quantization circuit 163, an inverse DCT circuit 162, a motion compensation circuit 161, and a motion detection circuit 160 can be omitted.

In the stream converter 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the MPEG encoder 10
In 2, the zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, the DCT coefficients are arranged in order of frequency components from DC components and low-frequency components to high-frequency components for each DCT block. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. And, as mentioned above,
A set of consecutive runs and subsequent levels has [D
C, AC ₁ , AC ₂ , AC ₃ ,...
Variable length coding is performed so that two codes are assigned.

In the stream converter 106, the variable-length coded and arranged DCT coefficients are once decoded by the variable-length code to detect the break of each coefficient, and the frequency is spread over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. Also, M
In the PEG encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing circuit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows a packing process of a macroblock in the packing circuit 107. Macroblocks are applied to fixed frames with a given data length,
Will be packed. If the data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data at the time of recording and reproduction, it is convenient for the subsequent ECC encoder 108 to perform shuffling and error correction coding. good. For simplicity, assume that one frame contains eight macroblocks.

As shown in an example in FIG. 9A, eight macroblocks have different lengths due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, the macroblock is poured into a fixed-length frame having a length of one sync block, and the entire data generated in one frame period is fixed-length. FIG.
As shown in an example in B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks,
The portion (overflow portion) that extends beyond the sync block length is packed into an area that is vacant in order from the beginning, that is, after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing circuit 107 can know the end of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing circuit 107. For each row of VLC data, SYNC pattern, ID, DID
Are added, and the parity of the inner code is added, thereby forming one SYNC block.

That is, a 10-byte outer code parity is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID and VLC data (or external data) are aligned in the horizontal direction. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the difference between the lengths of VLC data in one SYNC block is 59.94 Hz, 25 Hz, and 23.97.
This is because the frame frequency of video data is different, such as 6 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz, and one sample is quantized to 24 bits. One sample may be converted to another number of bits, for example, 16 bits. Therefore, according to the difference in the frame frequency described above,
The amount of audio data in one SYNC block is different.

An example of the header reproducing circuit 140 will be described with reference to the block diagram of FIG. 11 and the timing chart of FIG. The stream NXPB of the reproduction data from the depacking circuit 133 is supplied to the selector 11, the header detection circuit 12, and the RAM 13 via an 8-bit width bus. As shown in FIG. 12A, the stream NXPB includes a header section and a picture data section. For example, in MPEG, a header portion includes a sequence header, a GOP header, a picture header, and user data. In the header section, each data field is delimited in byte units.

The header detection circuit 12 outputs the stream NXP
A header portion in B is detected, and a header detection signal is generated.
For example, in the case of MPEG, a header start code (Sequence start code) is (00
Four bytes of 0001B3hex) (hex indicates a hexadecimal code) are arranged, and (0000010) is set as a picture data start code (Slice start code).
1hex) to (000001AFhex). By detecting the header start code and the picture data start code, the header detection circuit 12 generates a header detection signal that becomes “1” (logical 1) in the section of the header section as shown in FIG. 12B. I do.

The error flag ERR generated by the ECC decoder 132 is supplied to AND gates 14 and 15. The error flag ERR is a signal that becomes “1” at the position of an error that cannot be corrected. FIG. 12C shows an example of the error flag ERR. The error flag ERR is inverted and input to the AND gate 15.
As another input of each of the AND gates 14 and 15, a header detection signal is supplied.

The output herr of the AND gate 14 is shown in FIG.
As shown in (1), this signal is set to "1" when the data included in the header is an error. The presence or absence of an error is indicated in byte units. The output capt of AND gate 15 is shown in FIG.
As shown in FIG. 2E, this signal is "1" when the header is not in error. The selector 11 is controlled by the output herr of the AND gate 14. The output capt of AND gate 15 is supplied to we (Wite enable) of RAM 13,
The operation of fetching data from the RAM 13 is controlled. RA
The data nxram read from M13 is supplied to the selector 11.

In the case shown in FIG.
When the output capt is "1", the data, that is, the data of the header portion without error is written into the RAM 13. The written data of the header portion is read from the RAM 13. The selector 11 sets the output herr of the AND gate 14 to "
0 "(logical 0), the playback stream NXPB
Is selectively output as output data NX2, which is "1".
In this case, the information of the header portion having no error stored in the RAM 13 is selectively output as the output data NX2. Accordingly, the output data NX2 is obtained by replacing the error data with the error-free data from the RAM 13 as shown in FIG. 12F.

In this embodiment, the error flag ERR
Indicates the presence or absence of an error in byte units, and the data in the header portion is written to the RAM 13 at different addresses in byte units. Further, even when a byte having an error in the header portion is replaced with a byte stored in the RAM 13, the corresponding byte is replaced in byte units. In this case, the error may be replaced in units of one or more bytes of the header part, and
The entire header may be replaced. It should be noted that, in the picture data section, the picture data indicating the error by the error flag ERR is modified by a separate circuit (not shown) by a separate circuit.

In the embodiment shown in FIG. 11, the contents of the RAM 13 are constantly updated with error-free header data. Therefore, it is possible to recover the error data in the header portion by the data immediately before the error. Normally, the data (information) in the header portion does not frequently change, so that it is possible to output the output stream NX2 including the effective header portion from which the error has been removed.

Referring to FIGS. 13 and 14, another embodiment of the header reproducing circuit 140 will be described. In another embodiment, header types (sequence header, GOP header, picture header) are distinguished, and header information is recovered for each header type. Header detection circuits 12a, 12b, and 12c for detecting each type of header are provided. As shown in FIG. 14A, in the case of MPEG,
Header start code (S
(equence start code) as (000001B3hex)
(Hex indicates that it is a hexadecimal code.) 4 bytes are arranged, and (00000) is used as a header start code (Sequence start code) indicating the start of the GOP header.
1B8 hex), and a header start code (Sequence start code) indicating the start of a picture header
And 4 bytes of (00000100 hex) are arranged. Further, the picture data start code (Sl
(ice startcode) as (000001)
01hex) to (000001AFhex).

As shown in FIG. 14B, the header detection circuit 12a detects the detection signal which becomes "1" in the section of the sequence header.
seq, and the header detection circuit 12b outputs the detection signal go which becomes “1” in the section of the GOP header as shown in FIG. 14C.
p, and as shown in FIG. 14C, the header detection circuit 12c outputs the detection signal pi which becomes "1" in the picture header section.
Output c. These header detection signals are OR gate 1
The logical sum is obtained at 6, and the output of the OR gate 16 is supplied to the AND gate 14. The selector 11a is controlled by the output herr of the AND gate 14.

In order to store error-free data in the header of the playback stream NXPB, the RAM 13a,
13b and 13c are provided. RAM13a we
The output seqc of the AND gate 15a is supplied as (Wite enable), and the AND gate 15a is used as the we of the RAM 13b.
The output gopc of b is supplied, and the output picc of the AND gate 15c is supplied as the we of the RAM 13c. The header detection signal seq and the inverted error flag ERR (FIG. 14E) are supplied to the AND gate 15a.
The header detection signal gop and the inverted error flag ERR are supplied to 5b, and the AND gate 15c is supplied with the header detection signal pic and the inverted error flag ERR. Therefore, the content of the RAM 13a is updated by an error-free sequence header, the content of the RAM 13b is updated by an error-free GOP header,
The content of M13c is updated with an error-free picture header.

An error-free sequence header seqr, an error-free GOP header gopr, and an error-free picture header picr read from each of the RAMs 13a, 13b, and 13c are input to the selector 11b. Selector 11
b is controlled by the header detection signals seq, gop, and pic, and selectively outputs the corresponding header data as output data nxram in a section where these header detection signals are "1". The output data nxram of the selection 11b is supplied as another input of the selector 11a. As described above, the selector 11a is controlled by the output herr of the AND gate 14, and replaces the erroneous header data with the erroneous header data from the RAM.

FIGS. 14F, 14G and 14H show examples of the recovery of the data in the sequence header. FIG.
In the case of 4, the output seqc of the AND gate 15a is as shown in FIG.
As shown in (1), the value of the sequence header becomes "1" in the section of data having no error, and the data of the sequence header having no error is taken into the RAM 13a. The selector 11a outputs the output herr of the AND gate 14 (FIG. 14).
When G) is "1", the output data nxra of the selector 11b
Since m is selected, the error data in the sequence header is replaced with error-free data stored in the RAM 13a, as shown in FIG. 14H. Similarly, errors in other GOP headers and picture headers are stored in the RAM 13.
Replaced with error-free data stored in b and 13c. In this way, the header information can be recovered.

The present invention can be applied to a case where data is recorded on a recording medium other than a tape, for example, a disc-shaped recording medium. The present invention is also applicable to a case where data is transmitted via a wired or wireless transmission path.

[0103]

According to the present invention, only the header determined to have no error is stored in the memory, and when the reproduced (received) header has an error, the header having the error is replaced by the header stored in the memory. Therefore, there is an advantage that it is not necessary to repeatedly transmit the header or to perform multiplex recording on the medium, and there is no problem that the transmission data rate is increased or the recording capacity is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an example of a track format.

FIG. 3 is a schematic diagram illustrating another example of a track format.

FIG. 4 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 5 shows an ID and a DID added to a sync block.
FIG.

FIG. 6 is a block diagram illustrating an example of an MPEG encoder.

FIG. 7 is a schematic diagram for explaining an output method of an MPEG encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of an MPEG encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a block diagram of an example of a header reproducing circuit according to the present invention.

FIG. 12 is a timing chart showing an operation of an example of the header reproducing circuit.

FIG. 13 is a block diagram of another example of the header reproducing circuit according to the present invention.

FIG. 14 is a timing chart showing the operation of another example of the header reproduction circuit.

FIG. 15 is a schematic diagram for explaining a problem of a conventional data recording / reproducing device.

[Explanation of symbols]

12, 12a, 12b, 12c ... header detection circuit,
13, 13a, 13b, 13c: RAM for storing only error-free headers, 102: MPEG encoder, 106: stream converter, 107
.Packing circuit, 108 ECC encoder, 1
20: magnetic tape, 131: ECC decoder,
133: depacking circuit, 134: stream converter, 140: header reproducing circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/92 H04N 5/92 H 7/30 7/133 A F term (Reference) 5C053 FA22 FA23 GB14 GB15 GB38 GB40 JA07 JA21 5C059 KK01 MA00 MA05 MA23 ME01 RF09 RF11 SS06 SS11 TA76 TB00 TC22 TD00 5J065 AA05 AB02 AC03 AD16 AE02 AE08 AF02 5K014 AA01 BA05 EA01 FA06 HA05 5K030 GA12 HA08 HB02 JA05 KA13 KA19 LA07 LA07

Claims (8)

[Claims] 1. A data transmission apparatus for transmitting a header and picture data, comprising: encoding means for encoding a header with an error correction code; transmitting means for transmitting output data of the encoding means to a transmission path; Receiving means for receiving data encoded by an error correction code passing through a transmission path; and error correction for receiving the received data and decoding the error correction code to correct errors in the header and picture data. Means, a header detection means for detecting a header in the output data of the error correction means, and a header detected by the header detection means,
A memory means for writing only a header determined to be free of an error by the error flag from the error correction means; and a header stored in the memory means in place of the header which is an error in the output data of the error correction means. And a selecting means controlled by the error flag so as to select the data transmission apparatus. 2. The data transmission apparatus according to claim 1, wherein the encoding unit encodes the header and the picture data using a common error correction code. 3. The data transmission apparatus according to claim 1, wherein the picture data is data compressed by coding that combines inter-picture prediction coding and DCT. 4. The data transmission device according to claim 1, wherein the header has information necessary for restoring an image from the picture data. 5. The data transmission device according to claim 4, wherein the information of the header is information on a vertical size and a horizontal size of a screen. 6. The data transmission apparatus according to claim 1, wherein the header includes information necessary for restoring an image from the picture data, and user data. 7. The data transmission device according to claim 1, wherein the header detecting means detects the header by detecting a specific start code of the header. 8. A data transmission method for transmitting a header and picture data, comprising: a step of encoding the header with an error correction code; a step of transmitting the encoded data to a transmission path; Receiving data encoded by an error correction code; receiving the received data and decoding the error correction code to correct an error in the header and picture data; A header detection step of detecting a header in the subsequent data; and a step of writing only the detected header, which is determined to be error-free by the error flag generated in the error correction step, to the memory means. The memory is replaced with a header which is an error in the output data after the error correction. To select the header stored in the stage, the data transmission method characterized by comprising the steps being controlled by said error flag.