JP2000152175A - Synchronization detector, its method and reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically detect respective data blocks of different length intermingled in a data stream. SOLUTION: Input data are fed to shift registers 10, 11 respectively corresponding to data lengths L, K where L>K and 2K>L hold. Based on a synchronization pattern in input data detected by a circuit 14, the synchronization pattern is detected in inputs and outputs of the shift registers 10, 11. A data length of signals from the circuits 10, 11 from which the synchronization pattern is detected is used for a SYNC block length. The detected SYNC information is stored in a RAM 17 from the head of the information when the length of the information is K and stored in the RAM 17 from a bit of the information by (L-K) bits from the least significant bit when the length is L. The information is fed to an inertia circuit 18 from the (2L-K)th bit from the head of the information stored in the RAM 17. When the length is K, the circuit 18 delays the information by (L-K) and outputs a resulting synchronization pulse. A delay line 19 outputs a SYNC block synchronously with the synchronization pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detecting apparatus and method for detecting a synchronization pattern from data blocks of at least two different data lengths reproduced from a recording medium, and a reproducing apparatus.

[0002]

2. Description of the Related Art In recent years, digital video tape recorders, which use a magnetic tape as a recording medium and record and reproduce digital video signals and digital audio signals, are becoming widespread.

In such an apparatus, digital video data and digital audio data are stored in units of packets of a predetermined length, and each packet has a synchronization pattern for detecting synchronization, a block ID for identifying each packet, and a data. The sync block is configured by adding an ID representing the contents of the above and a parity for error correction.
Then, the sync blocks are grouped into sectors according to the type of data, and are recorded on the magnetic tape as serial data in sector units. Recording is performed by a helical scan method in which tracks are formed diagonally on a magnetic tape by a rotating head.

At the time of recording, the length of each sync block in the same sector is made the same, and
IDs in which D is continuous and represent data contents have the same value.

FIG. 23 schematically shows an example of the arrangement of each sector on a track. The rotating head traces from the left side to the right side of the figure to form a track. As described above, the track is actually formed obliquely with respect to the magnetic tape, and one frame of video data is recorded using a plurality of, for example, four tracks. A plurality of audio sectors for recording audio data are arranged between video sectors for recording video data. In this example, C
Since audio signals for eight channels from h1 to Ch8 can be handled, eight audio sectors A1 to A8 are arranged.

[0006] Between each sector, an edit gap (E) in which audio data is not recorded is inserted so that, for example, insert editing can be performed in sector units of an audio signal.
G) is arranged. A preamble is provided at the beginning of the track. In the preamble, a signal that makes it easy for the PLL for the reproduction clock to lock during reproduction, for example, data of “FF (hexadecimal notation)” is repeatedly recorded. Further, the shortest recording wavelength on the recording medium depends on the data amount for one track.

At the time of reproduction, tracks on the magnetic tape are traced by the rotating head, and a reproduction signal is obtained.
The edge of the signal in the preamble portion of the reproduced signal is detected, and the PLL for the reproduced clock is locked using the edge interval. Then, from the reproduced signal, a sync pattern is detected from the reproduced bit string synchronized with the reproduced clock by the sync detection circuit, and the head position of each sync block is detected. Then, the packets in the detected sync block are rearranged according to the block ID number and the data content ID, and the original data sequence is decoded. That is, by utilizing the fact that the bit sequence and appearance period of the synchronization pattern at the head of the sync block and that the block ID number is continuous and the ID indicating the data content is the same within the same sector, the phase of the sync block is changed. Specified.

For example, the same pattern is detected at a position where the bit string of the synchronization pattern matches the unique pattern and is delayed by the sync block length.
If the number is correct, the phase of the sync block is specified.

Here, consider a case where an error has occurred in the data string when decoding the data string. Here, it is assumed that the bit intervals of the data string are always the same, and only a random error is added. In this case, the bit interval between the synchronization patterns is always the same within the same sector. Therefore, if the synchronization can be detected at the beginning of the sector, the flywheel processing is performed based on the block length, and then the beginning of the subsequent synchronization block is obtained. The phase can be specified. Therefore, in this case, it is sufficient that the synchronization detection probability at the head position of the sector is sufficiently ensured.

[0010] The flywheel process is a process for generating a synchronization signal following the previously detected synchronization.
It is realized by an inertia circuit.

[0011]

In an actual digital video tape recorder, two types of data, video and audio, are handled. For example, in order to store two types of data having different data amounts per video editing unit in one type of sync block and handle them, a redundant portion is inserted into either data length to reduce the length. Will be aligned.

For example, P used in European countries and the like
Considering the format of the AL / SECAM system, the number of samples of audio data in one field having a cycle of 50 Hz is 910 when the sampling frequency is 48 KHz (one sample is 24 bits + control bits). If this is to be accommodated in a sync block having a block length L corresponding to the number of video data, 9
10 samples × (24 bits + control bits) = L × n
... (1) Here, n is an integer. Therefore, if the number of bytes of the audio data is set to an integral multiple of L, there is no useless recording area and the efficiency is high.

On the other hand, the optimum sync block length of video data is determined by the total amount of data, the minimum singular image block as a unit of processing, the number of tracks per editing unit, and the like. In other words, the optimum value of the sync block length differs depending on the type of data to be stored, and if there is no optimum combination of the sync block lengths for both the audio data and the video data, the sync block length is determined for either of the sync blocks. Since the same length cannot be obtained unless redundant data is inserted, the efficiency is reduced.

Therefore, if the length of the sync block for storing the audio data and the video data is set to a recording format that selects the optimum length, the recording efficiency can be improved. That is, sync blocks having different lengths are mixed in one recording format.

As described above, at the time of reproduction, it is necessary to detect a synchronization pattern by a sync detection circuit and cut out a sync block. FIG. 24 shows an example of the configuration of a sync detection circuit according to the related art. This circuit corresponds to a sync block whose data length is L. The input data supplied from the terminal 300 is supplied to the delay 301 corresponding to the data length L and to one input terminal of the comparison circuit 304. The other input terminal of the comparison circuit 304 is supplied with the input data delayed by the delay 301.

The data string output from the delay 301 is delayed by 2 L via the delay line 303 and supplied to the variable shifter 305.

The input data is supplied to the sink comparison circuit 30.
2 and latched internally. Then, the latched input data is compared with a synchronization pattern consisting of 8 bits at each bit position. As a result of the comparison, the detection result of the synchronization pattern and the bit shift amount indicating at which bit position the pattern matches are used as the comparison circuit 3
04. The comparison circuit 304 detects a sync block from the data string supplied to one and the other input terminals based on the detection result, and based on the block ID number and the data content ID stored in the sync block, as described above. , Judge the validity of the sync block, and specify the phase of the sync block.

A sync position correction circuit 306 generates sync position correction information based on the sync block phase information obtained by the comparison circuit 304. This sync position correction information is supplied to the variable shifter 305 and the inertia circuit 307. In the inertia circuit 307, a synchronization pulse corresponding to the sync block length is generated based on the sync position correction information and the sync block length L given in advance. On the other hand, the variable shifter 3
The data sequence supplied to 05 is bit-shifted by a predetermined amount based on the sync position correction information. Then, based on the synchronization pulse supplied from the inertia circuit 307, it is output to the output terminal 308 as output data. The synchronization pulse generated by the inertia circuit 307 is supplied to the terminal 309
Is also derived.

As described above, the sync detection circuit according to the prior art has only one set of circuits for detecting a synchronization pattern, and cannot cope with a case where data blocks of different lengths exist in a series of input data. . In addition, the inertia circuit 307 that generates a synchronization pulse, which is a synchronization signal, has a problem that the pulse generation cycle is fixed, and the inertia circuit 307 cannot cope with a data string having a plurality of data lengths.

As a method of processing a data string having a plurality of sync block lengths by a sync detection circuit which can handle only one type of synchronization pattern interval, a control for switching a sync block length to be detected corresponding to an input data string is used. It is conceivable to use a signal. For example, it is possible to generate a switching timing for the position of the audio and video sectors on the track from the position information of the reproducing head.

However, this method has a problem that, for example, in a reproducing system requiring a high data rate and a large number of reproducing heads, it is necessary to generate a control signal corresponding to each reproducing head.

Further, in a system in which reproduction is performed at a tape speed different from that at the time of recording and in which the number of rotations of a rotary head is controlled during variable speed reproduction, the switching timing dynamically changes, and a control signal is generated. There was a problem that it was like this.

Further, as in the configuration according to the prior art shown in FIG. 24, in a circuit whose processing is delayed by 3L as a whole, the detection block length is changed from L to K shorter than L by using a control signal in this state. If the switching is performed instantaneously, there is a problem that data of (3L-K) length on the circuit that delays data is lost. This is because control is performed so that data is output at the timing of the data length K even though data of 3L exists on all delays.

Accordingly, an object of the present invention is to provide a synchronization detecting apparatus and method, and a reproducing apparatus, which are capable of automatically detecting data blocks of different lengths mixed in a data string. is there.

[0025]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a synchronization detecting apparatus for detecting the synchronization of at least two different data lengths of a data block having a synchronization pattern for detecting synchronization. At
A first synchronization pattern detecting means for detecting a synchronization pattern for input data; a first storage unit for storing the input data in order of a predetermined unit length and outputting the stored data in an order of a predetermined unit length from the oldest order; Based on the detection result of the first memory means having a length corresponding to the data length L, and the pattern detection means, the data input to the first memory means and the data output from the first memory means are both synchronized. First comparison means for detecting whether or not the pattern matches a pattern, input data is input simultaneously with the first memory means, and the input data is sequentially stored in predetermined length units, and the stored data is stored in predetermined units. A second memory means which is shorter than the first data length L and has a length corresponding to the second data length K which is not an integral multiple of the first data length L, which is output from the oldest one for each length And puta A second comparing means for detecting whether or not the data input to the second memory means and the data output from the second memory means coincide with the synchronization pattern based on the detection result of the second detecting means; A synchronization detection device that, when the synchronization pattern is detected by one of the first comparison unit and the second comparison unit, the synchronization detection is performed.

According to the present invention, there is provided a reproducing apparatus for reproducing data blocks of at least two different data lengths having a synchronization pattern for detecting synchronization recorded on a recording medium. A synchronization pattern detecting means for detecting a synchronization pattern with respect to the data, and a first data for storing the reproduced data in order of a predetermined unit length and outputting the stored data in an order of oldness for the predetermined unit length. First of length corresponding to length L
And a first means for detecting whether both the data inputted to the first memory means and the data outputted from the first memory means coincide with the synchronization pattern based on the detection result of the pattern detecting means. The reproduction data is input simultaneously with the comparison means and the first memory means, and the reproduction data is sequentially stored in units of a predetermined length, and the stored data is output from the oldest unit in the predetermined unit length. And a second memory unit having a length corresponding to a second data length K that is shorter than the data length L of the first data length L and is not an integral multiple of the first data length L, and a detection result of the pattern detection unit. Second
Comparing means for detecting whether both the data inputted to the memory means and the data outputted from the second memory means coincide with the synchronization pattern, the first comparing means and the second comparing means If a synchronization pattern match is detected in one of the first and second comparison means, it is determined that synchronization has been detected. And output means for outputting in data block units each having a data length.

According to the present invention, there is provided a synchronization detecting method for detecting synchronization of data blocks having at least two different data lengths having a synchronization pattern for detecting synchronization, the length corresponding to the first data length L Storing the input data in units of a predetermined unit length in order in the first memory, and outputting the data stored in the first memory in units of the predetermined unit length in chronological order; Input data is input simultaneously with the first memory to the second memory having a length shorter than the length L and corresponding to the second data length K which is not an integral multiple of the first data length L. Storing the input data in units of a predetermined length, outputting the data stored in the second memory in units of a predetermined length in chronological order, and detecting a synchronization pattern with respect to the input data. Detecting whether the data input to the first memory and the data output from the first memory coincide with the synchronization pattern based on the detection result of the synchronization pattern detection step and the pattern detection step. Detecting whether the data input to the second memory and the data output from the second memory coincide with the synchronization pattern based on the detection results of the first comparison step and the pattern detection step. A second comparison step of performing synchronization detection if a synchronization pattern match is detected in one of the first comparison step and the second comparison step. This is a synchronization detection method.

As described above, according to the present invention, the first and second data lengths L and K corresponding to the first and second data lengths L and K, respectively, are used.
Data is input to the first and second memory means, and the input data and the output data are compared in each of the first and second memory means. Since it is determined that the synchronization has been detected when the synchronization pattern is detected in both outputs, the synchronization can be automatically detected for at least two different data lengths.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital video tape recorder will be described below. This embodiment is suitable for use in the environment of a broadcasting station, and enables recording and reproduction of video signals of a plurality of different formats. For example,
Both a signal having 480 effective lines in the interlaced scanning based on the NTSC system (480i signal) and a signal having 576 effective lines in the interlaced scanning based on the PAL system (576i signal) are hardly used. Recording and reproduction can be performed without any change. further,
A signal with 1080 lines (10
80i signal), progressive scanning (non-interlace), the number of lines is 480 lines, 720 lines, and 108 lines, respectively.
0 signals (480p signal, 720p signal, 1080p signal
Signal) and the like.

In this embodiment, a video signal signal is compression-encoded based on the MPEG2 system, and an audio signal is handled uncompressed. As is well known, MPEG2
Is a combination of motion-compensated predictive coding and compression coding by DCT. The data structure of MPEG2 has a hierarchical structure, and includes a block layer, a macroblock layer, a slice layer, a picture layer, a GOP layer, and a sequence layer from the lowest level.

The block layer is a unit for performing DCT, D
It consists of a CT block. The macroblock layer includes a plurality of D
It is composed of CT blocks. The slice layer is composed of a header section and any number of macroblocks that do not extend between rows. The picture layer includes a header section and a plurality of slices. A picture corresponds to one screen. G
The OP (Group Of Picture) layer includes a header portion, an I picture that is a picture based on intra-frame coding, and P and B pictures that are pictures based on predictive coding.

An I picture (Intra-coded picture) uses information that is closed only in one picture when it is coded. Therefore, at the time of decoding, decoding can be performed using only the information of the I picture itself. A P-picture (Predictive-coded picture: a forward predictive coded picture) uses a previously decoded I-picture or P-picture which is temporally previous as a predicted picture (a reference picture for taking a difference). . Whether to encode the difference from the motion-compensated predicted image, to encode without taking the difference,
The more efficient one is selected for each macroblock. A B picture (Bidirectionally predictive-coded picture) is a temporally previous I-picture or P-picture which is temporally preceding, and a temporally backward I-picture, We use three types of I-pictures or P-pictures already decoded, as well as interpolated pictures made from both. Among the three types of difference coding after motion compensation and intra coding, the most efficient one is selected for each macroblock.

Therefore, as the macroblock type,
Intra-frame coding (Intra) macroblock, forward (Fward) inter-frame prediction macroblock predicting the future from the past, and backward (Backward) interframe prediction macroblock predicting the future from the future, There is a bidirectional macroblock to be predicted. All macroblocks in an I picture are intra-coded macroblocks. The P picture includes an intra-frame coded macro block and a forward inter-frame predicted macro block. The B picture includes all four types of macroblocks described above.

A GOP includes at least one I picture, and P and B pictures are allowed even if they do not exist. The top sequence layer is composed of a header section and multiple GOPs.
It is composed of

In the MPEG format, a slice is one variable-length code sequence. A variable-length code sequence is a sequence in which a data boundary cannot be detected unless a variable-length code is decoded.

At the head of each of the sequence layer, GOP layer, picture layer, slice layer and macroblock layer, an identification code (referred to as a start code) having a predetermined bit pattern arranged in byte units is provided. Be placed. Note that the header section of each layer described above collectively describes a header, extension data, or user data. In the header of the sequence layer, the size of the image (picture) (the number of vertical and horizontal pixels) and the like are described. The time code, the number of pictures constituting the GOP, and the like are described in the header of the GOP layer.

The macro blocks included in the slice layer are:
It is a set of a plurality of DCT blocks, and the encoded sequence of the DCT block is a variable of a sequence of quantized DCT coefficients, with the number of consecutive 0 coefficients (run) and a non-zero sequence (level) immediately after it as one unit. It is a long code. The macroblock and the DCT block in the macroblock are not added with the identification codes arranged in byte units.
That is, they are not one variable-length code sequence.

The macro block is composed of one screen (picture).
It is divided into a grid of 6 pixels × 16 lines. A slice is formed by connecting these macroblocks in the horizontal direction, for example. The last macroblock of the previous slice of a continuous slice and the first macroblock of the next slice are continuous, and it is not allowed to form a macroblock overlap between slices. When the size of the screen is determined, the number of macroblocks per screen is uniquely determined.

On the other hand, in order to avoid signal deterioration due to decoding and encoding, it is desirable to edit the encoded data. At this time, the P picture and the B picture require a temporally preceding picture or a preceding and succeeding picture for decoding. Therefore, the editing unit cannot be set to one frame unit. In consideration of this point, in this embodiment, one GOP is made up of one I picture.

For example, a recording area in which recording data for one frame is recorded is a predetermined area. MPEG2
Since the variable length coding is used, the amount of generated data for one frame is controlled so that data generated during one frame period can be recorded in a predetermined recording area. Further, in this embodiment, one slice is composed of one macroblock so as to be suitable for recording on a magnetic tape, and one macroblock is applied to a fixed frame having a predetermined length.

FIG. 1 shows an example of the configuration on the recording side of the recording / reproducing apparatus according to this embodiment. At the time of recording, a predetermined interface, for example, SDI (Serial Data Interface)
The digital video signal is input from the terminal 101 via the receiving unit of the above. SDI is an interface defined by SMPTE for transmitting (4: 2: 2) component video signals, digital audio signals, and additional data. An input video signal is converted by a video encoder 102 into a DCT (Discrete Cosine Transform).
form), is converted into coefficient data, and the coefficient data is subjected to variable length coding. The variable length coded (VLC) data from the video encoder 102 is an elementary stream compliant with MPEG2. This output is supplied to one input terminal of the selector 103.

On the other hand, through the input terminal 104, the ANSI
SDTI (Serial Data Transport Inter), which is an interface defined by / SMPTE 305M
face) format data is input. This signal is synchronously detected by SDTI receiving section 105. And
Once stored in the buffer, the elementary stream is extracted. The extracted elementary stream is supplied to the other input terminal of the selector 103.

The elementary stream selected and output by the selector 103 is supplied to a stream converter 106. In the stream converter 106, the MPE
The DCT coefficients arranged for each DCT block based on the G2 rule are replaced with a plurality of DCTs constituting one macroblock.
Through the T block, frequency components are grouped, and the grouped frequency components are rearranged. The rearranged converted elementary stream is stored in the packing and shuffling unit 1.
07.

Since the video data of the elementary stream is variable-length coded, the data length of each macroblock is not uniform. In the packing and shuffling unit 107, macro blocks are packed in a fixed frame. At this time, the portion that protrudes from the fixed frame is sequentially packed into a surplus portion with respect to the size of the fixed frame. Also, system data such as time code is input to the input terminal 108.
Is supplied to the packing and shuffling unit 107, and the system data is subjected to a recording process similarly to the picture data. Also, shuffling is performed in which the macroblocks of one frame generated in the scanning order are rearranged and the recording positions of the macroblocks on the tape are dispersed. Shuffling can improve the image update rate even when data is reproduced in pieces during variable speed reproduction.

The video data and system data from the packing and shuffling section 107 (hereinafter, also referred to as video data even when system data is included unless otherwise required) are supplied to the outer code encoder 109. A product code is used as an error correction code for video data and audio data. The product code encodes an outer code in a vertical direction of a two-dimensional array of video data or audio data, encodes an inner code in a horizontal direction thereof, and encodes data symbols doubly. As the outer code and the inner code, a Reed-Solomon code can be used.

The output of the outer code encoder 109 is supplied to the shuffling unit 110 and a plurality of ECCs (Error Correction
ig Code) blocks are shuffled to change the order in sync block units. The shuffling in sync block units prevents errors from concentrating on a specific ECC block. Shuffling part 1
Shuffling performed at 10 may be referred to as interleaving. The output of the shuffling unit 110 is
1 and mixed with audio data. In addition,
The mixing unit 111 includes a main memory, as described later.

Audio data is supplied from an input terminal denoted by reference numeral 112. In this embodiment, an uncompressed digital audio signal is handled. The digital audio signal is supplied to an input SDI receiver (not shown)
These are separated by the DTI receiving unit 105 or input through an audio interface. The input digital audio signal is supplied to A
It is supplied to the UX adding unit 114. The delay unit 113 is for time alignment of the audio signal and the video signal.
The audio AUX supplied from the input terminal 115 is auxiliary data, and is data having information related to audio data such as the sampling frequency of audio data. The audio AUX is added to the audio data by the AUX adding unit 114, and is treated the same as the audio data.

The audio data and AUX from the AUX adding unit 114 (hereinafter, AUX except when necessary)
Is also simply referred to as audio data. ) Is supplied to the outer code encoder 116. Outer code encoder 11
No. 6 encodes an outer code for audio data. The output of the outer code encoder 116 is the shuffling unit 1
17 and undergoes a shuffling process. As audio shuffling, shuffling in sync block units and shuffling in channel units are performed.

The output of the shuffling unit 117 is
1 and the video data and the audio data are converted into data of one channel. The output of the mixing unit 111 is ID
The adding unit 118 is supplied, and the ID adding unit 118 adds an ID including information indicating a sync block number. The output of the ID addition unit 118 is the inner code encoder 119
, And the inner code is encoded. Further, the output of the inner code encoder 119 is supplied to the synchronization adding section 120, and a synchronization signal for each sync block is added. By adding the synchronization signal, recording data in which the sync blocks are continuous is configured. This recording data is supplied to the rotary head 122 via the recording amplifier 121, and is recorded on the magnetic tape 123. In practice, the rotary head 122 is configured such that a plurality of magnetic heads having different azimuths of heads forming adjacent tracks are attached to the rotary drum.

The recording data may be scrambled as required. Further, digital modulation may be performed at the time of recording, and a partial response class 4 and Viterbi code may be used.

FIG. 2 shows an example of the configuration on the reproducing side according to an embodiment of the present invention. Rotating head 1 from magnetic tape 123
The reproduction signal reproduced at 22 is supplied to the synchronization detection unit 132 via the reproduction amplifier 131. Equalization and waveform shaping are performed on the reproduced signal. Further, demodulation of digital modulation, Viterbi decoding, and the like are performed as necessary. The synchronization detection unit 132 detects a synchronization signal added to the head of the sync block. The sync block is cut out by the synchronization detection.

The output of the synchronization detecting circuit 132 is supplied to the inner code encoder 133, and the error of the inner code is corrected. The output of the inner code encoder 133 is the ID interpolation unit 134
And the ID of the sync block in which the error occurred due to the inner code, for example, the sync block number is interpolated. ID
The output of the interpolation unit 134 is supplied to a separation unit 135, where the video data and the audio data are separated. As described above, video data means DCT coefficient data and system data generated by MPEG intra coding, and audio data is PCM (Pulse Code Modulati
on) means data and AUX.

The video data from the separation unit 135 is subjected to a process reverse to shuffling in the deshuffling unit 136. The deshuffling unit 136 performs a process of restoring the shuffling in sync block units performed by the shuffling unit 110 on the recording side. Deshuffling part 136
Is supplied to the outer code decoder 137, and error correction by the outer code is performed. When an error that cannot be corrected occurs, an error flag indicating the presence or absence of the error is set to indicate the presence of the error.

The output of the outer code decoder 137 is supplied to a deshuffling and depacking unit 138. The deshuffling and depacking unit 138 performs processing for restoring shuffling in macroblock units performed by the packing and shuffling unit 107 on the recording side. In the deshuffling and depacking unit 138,
Disassemble the packing applied during recording. That is, the length of the data is returned in units of macroblocks, and the original variable length code is restored. Further, in the deshuffling and depacking unit 138, the system data is separated,
It is taken out to the output terminal 139.

Deshuffling and depacking unit 13
The output of No. 8 is supplied to the interpolation unit 140, and the data for which the error flag is set (that is, there is an error) is corrected. That is, if it is determined that there is an error in the macroblock data before the conversion, the DCT coefficients of the frequency components after the error location cannot be restored. Therefore, for example, the data at the error location is replaced with a block end code (EOB), and the DCT coefficients of the subsequent frequency components are set to zero. Similarly, at the time of high-speed reproduction, only DCT coefficients up to the length corresponding to the sync block length are restored, and the coefficients thereafter are replaced with zero data. Further, the interpolation unit 1
In 40, when the header added to the head of the video data is an error, the header (sequence header, GOP
Header, picture header, user data, etc.) are also recovered.

Since the DCT coefficients are arranged from the DC component and the low-frequency component to the high-frequency component across the DCT block, even if the DCT coefficients are ignored from a certain position onward, the macro block , DCT coefficients from DC and low-frequency components can be distributed evenly to each of the DCT blocks constituting.

The output of the interpolation section 140 is supplied to the stream converter 141. In the stream converter 141, the reverse process to that of the stream converter 106 on the recording side is performed. That is, the DCT coefficients arranged for each frequency component across the DCT blocks are rearranged for each DCT block. Thereby, the reproduced signal is converted into an elementary stream conforming to MPEG2.

As for the input / output of the stream converter 141, a sufficient transfer rate (bandwidth) is secured in accordance with the maximum length of the macroblock, as in the recording side. When the length of the macroblock is not limited, it is preferable to secure a bandwidth three times the pixel rate.

The output of the stream converter 141 is supplied to the video decoder 142. Video decoder 142
Decodes the elementary stream and outputs video data. That is, the video decoder 142 performs an inverse quantization process and an inverse DCT process. The decoded video data is taken out to the output terminal 143. For the interface with the outside, for example, SDI is used. In addition, the elementary stream from the stream converter 141 is supplied to the SDTI transmitting unit 144. Although illustration of the path is omitted, the SDTI transmission unit 144 is also supplied with system data, reproduced audio data, and AUX, and
It is converted into a stream having a data structure of the TI format. The stream from the SDTI transmission unit 144 is output to the outside through the output terminal 145.

The audio data separated by the separation unit 135 is supplied to the deshuffling unit 151. The deshuffling unit 151 performs a process opposite to the shuffling performed by the shuffling unit 117 on the recording side. The output of the deshuffling unit 117 is supplied to the outer code decoder 152, and error correction by the outer code is performed. Outer code decoder 152
Output the error-corrected audio data. An error flag is set for data having an uncorrectable error.

The output of the outer code decoder 152 is supplied to an AUX separation section 153, where the audio AUX is separated.
The separated audio AUX is taken out to the output terminal 154. The audio data is supplied to the interpolation unit 155. The interpolating unit 155 interpolates a sample having an error. As the interpolation method, it is possible to use an average value interpolation for interpolating with the average value of correct data before and after in time, a previous value hold for holding a previous correct sample value, and the like. The output of the interpolation unit 155 is supplied to the output unit 156. The output unit 156 performs a mute process for inhibiting the output of an audio signal that is in error and cannot be interpolated, and performs a delay amount adjustment process for time alignment with a video signal. The reproduced audio signal is extracted from the output unit 156 to the output terminal 157.

Although not shown in FIGS. 1 and 2, a timing generator for generating a timing signal synchronized with the input data, a system controller (microcomputer) for controlling the entire operation of the recording / reproducing apparatus, and the like are provided. Have been.

In this embodiment, signal recording on a magnetic tape is performed by a helical scan method in which a diagonal track is formed by a magnetic head provided on a rotating rotary head. A plurality of magnetic heads are provided on the rotating drum at positions facing each other. That is, when the magnetic tape is wound around the rotary head at a winding angle of about 180 °, a plurality of tracks can be simultaneously formed by rotating the rotary head by 180 °. The magnetic heads are formed as a set of two magnetic heads having different azimuths. The plurality of magnetic heads are arranged such that azimuths of adjacent tracks are different from each other.

FIG. 3 shows an example of a track format formed on a magnetic tape by the rotary head described above. This is an example in which video and audio data per frame are recorded on eight tracks. For example, the frame frequency is 29.97 Hz, and the rate is 50 Mbp
s, the number of effective lines is 480, and the number of effective horizontal pixels is 720
A pixel interlace signal (480i signal) and an audio signal are recorded. When the frame frequency is 25H
z, the rate is 50 Mbps, the number of effective lines is 576, and the number of effective horizontal pixels is 720.
6i signal) and audio signal can also be recorded in the same tape format as in FIG.

One segment is composed of two tracks having different azimuths. That is, eight tracks are composed of four segments. Track number corresponding to azimuth for a set of tracks constituting a segment

[0] and a track number [1] are assigned. In the example shown in FIG. 3, track numbers are exchanged between the first eight tracks and the second eight tracks, and different track sequences are assigned to each frame. Thus, even if one of the set of magnetic heads having different azimuths becomes unreadable due to clogging or the like, the influence of an error can be reduced by using the data of the previous frame.

In each of the tracks, a video sector in which video data is recorded is arranged at both ends, and an audio sector in which audio data is recorded is interposed between the video sectors. 3 and FIG. 4, which will be described later, show the arrangement of audio sectors on the tape.

In the track format shown in FIG. 3, eight channels of audio data can be handled. A1 to A8 indicate sectors of channels 1 to 8 of the audio data, respectively. The audio data is recorded with its arrangement changed in segment units. For audio data, audio samples generated in one field period (for example, when the field frequency is 29.97 Hz and the sampling frequency is 48 kHz, 800 or 801 samples) are divided into even-numbered samples and odd-numbered samples. Each sample group and AUX form one ECC block of a product code.

In FIG. 3, since data for one field is recorded on four tracks, two ECC blocks per channel of audio data are recorded on four tracks. The data of two ECC blocks (including the outer code parity) is divided into four sectors, and as shown in FIG. 3, the data is dispersedly recorded on four tracks. Two ECCs
A plurality of sync blocks included in the block are shuffled. For example, two ECC blocks of channel 1 are constituted by four sectors to which reference numbers A1 are assigned.

In this example, the video data is shuffled (interleaved) for four ECC blocks for one track, divided into upper sectors and lower sides, and recorded. In the lower sector video sector, a system area is provided at a predetermined position.

In FIG. 3, SAT1 (Tr) and SAT2 (Tm) are areas where servo lock signals are recorded. In addition, a gap of a predetermined size (Vg1, Sg1, Ag, Sg) is provided between the recording areas.
2, Sg3 and Vg2).

FIG. 3 shows an example in which data per frame is recorded on eight tracks.
Recording can be performed on tracks, six tracks, and the like.
FIG. 4A shows a format in which one frame has six tracks. In this example, the track sequence is

Only [0] is set.

As shown in FIG. 4B, the data recorded on the tape is composed of a plurality of equally-spaced blocks called sync blocks. FIG. 4C schematically shows a configuration of the sync block. As will be described later in detail, the sync block is composed of a SYNC pattern for detecting synchronization, an ID for identifying each sync block, a DID indicating the content of subsequent data, a data packet, and an inner code parity for error correction. Is done. Data is,
It is treated as a packet in sync block units. That is, the smallest data unit to be recorded or reproduced is one sync block. A number of sync blocks are arranged (FIG. 4B) to form, for example, a video sector (FIG. 4A).

FIG. 5 more specifically shows the data structure of a sync block of video data, which is the minimum unit of recording / reproduction. In this embodiment, one or two macroblocks of data (VLC data) are stored for one sync block according to the format of video data to be recorded, and the size of one sync block is reduced. The length is changed according to the format of the video signal to be handled. As shown in FIG. 5A, one sync block is
From the beginning, a 2-byte SYNC pattern, a 2-byte I
D, a 1-byte DID, for example, a data area variably defined between 112 bytes and 206 bytes, and a 12-byte parity (inner code parity). Note that the data area is also called a payload.

The first two bytes of the SYNC pattern are for synchronization detection and have a predetermined bit pattern. Synchronization detection is performed by detecting a SYNC pattern that matches the unique pattern.

FIG. 6A shows an example of the bit assignment of ID0 and ID1. The ID has important information inherent to the sync block, and each ID has 2 bytes (ID
0 and ID1). ID0 is 1
The identification information (SYNC ID) for identifying each of the sync blocks in the track is stored. SYNC
The ID is, for example, a serial number assigned to a sync block in each sector. The SYNC ID is represented by 8 bits. SYNC IDs are separately assigned to video sync blocks and audio sync blocks.

ID1 stores information on the track of the sync block. When the MSB side is bit 7 and the LSB side is bit 0, with respect to this sync block,
Bit 7 indicates whether the track is above (upper) or below (Lo)
wer), and bits 5 to 2 indicate the segment of the track. Bit 1 indicates the track number corresponding to the azimuth of the track.
Are bits for distinguishing video data and audio data by this sync block.

FIG. 6B shows an example of DID bit assignment in the case of video. The DID stores information related to the payload. The content of DID differs between video and audio based on the value of bit 0 of ID1 described above. Bits 7 to 4 are undefined (Reserve
d). Bits 3 and 2 are the mode of the payload, for example, indicating the type of the payload.
Bits 3 and 2 are auxiliary. Bit 1 indicates that one or two macroblocks are stored in the payload. Bit 0 indicates whether the video data stored in the payload is an outer code parity.

FIG. 6C shows an example of bit assignment of DID in the case of audio. Bits 7-4 are R
Eserved. Bit 3 indicates whether the data stored in the payload is audio data or general data. If compression-encoded audio data is stored in the payload, bit 3 is a value indicating the data.
Bit 2 to bit 0 store information of a 5-field sequence in the NTSC system. That is, NT
In the SC system, the sampling frequency of an audio signal for one field of a video signal is 48 kHz.
Is either 800 samples or 801 samples, and this sequence is aligned every five fields. Bit 2 to bit 0 indicate where in the sequence it is located.

Referring back to FIG. 5, FIGS. 5B to 5E
Shows an example of the above-mentioned payload. 5B and 5C
Shows an example in which video data (variable-length coded data) of 1 and 2 macroblocks is stored for the payload, respectively. In the example shown in FIG. 5B in which one macroblock is stored, length information LT indicating the length of the following macroblock is arranged in the first three bytes.
The length information LT may or may not include its own length. 5C shown in FIG.
In an example in which a macroblock is stored, the length information LT of the first macroblock is arranged at the head, and the first macroblock is arranged subsequently. Then, length information L indicating the length of the second macroblock following the first macroblock
T is arranged, followed by a second macroblock.
The length information LT is information necessary for depacking.

FIG. 5D shows video A for the payload.
An example in which UX (auxiliary) data is stored will be described. The head length information LT describes the length of the video AUX data. Subsequent to the length information LT, 5-byte system information, 12-byte PICT information, and 92-byte user information are stored. The remaining portion of the payload length is reserved.

FIG. 5E shows an example in which audio data is stored in the payload. Audio data can be packed over the entire length of the payload. The audio signal is not subjected to compression processing or the like, and is handled in, for example, a PCM format. The present invention is not limited to this, and audio data compressed and encoded by a predetermined method can be handled.

In this embodiment, the length of the payload, which is the data storage area of each sync block, is set optimally for the video sync block and the audio sync block, and is therefore not equal to each other. . In addition, the length of a sync block for recording video data and the length of a sync block for recording audio data are set to optimal lengths according to the signal format. Thereby, a plurality of different signal formats can be handled uniformly.

FIG. 7A shows the order of DCT coefficients in video data output from the DCT circuit of the MPEG encoder. Starting from the DC component at the upper left in the DCT block, in the direction where the horizontal and vertical spatial frequencies increase,
DCT coefficients are output by zigzag scan. As a result, as shown in an example in FIG. 7B, a total of 64 (8
DCT coefficients of (pixel × 8 lines) are obtained by being arranged in the order of frequency components.

This DCT coefficient is equal to V of the MPEG encoder.
Variable length coding is performed by the LC unit. That is, the first coefficient is fixed as a DC component, and the next component (AC
From the component), codes are assigned corresponding to the run of zero and the subsequent level. Therefore, the variable-length coded output for the coefficient data of the AC component is converted from the low (low-order) coefficient of the frequency component to the high (high-order) coefficient of AC ₁ ,
AC ₂ , AC ₃ ,... The elementary stream includes DCT coefficients subjected to variable length coding.

In the stream converter 106, the DCT coefficients of the supplied signal are rearranged. That is, in each macroblock, DCT coefficients arranged in order of frequency components for each DCT block by zigzag scan are rearranged in order of frequency components over each DCT block constituting the macroblock.

FIG. 8 shows this stream converter 106.
2 schematically shows the rearrangement of the DCT coefficients in. (4:
2: 2) In the case of a component signal, one macroblock is composed of four DCT blocks (Y ₁ ,
Y _2, and Y ₃ and Y _4), chroma signal Cb, DCT blocks (Cb ₁ of every two according to each of Cr, C
b ₂ , Cr ₁ and Cr ₂ ).

As described above, the video encoder 102
Then, a zigzag scan is performed in accordance with the rules of MPEG2, and as shown in FIG. 8A, for each DCT block,
DCT coefficient is changed from DC component and low frequency component to high frequency component,
The frequency components are arranged in order. When scanning of one DCT block is completed, scanning of the next DCT block is performed, and similarly, DCT coefficients are arranged.

That is, in the macro block, DCT blocks Y ₁ , Y ₂ , Y ₃ and Y ₄ , DCT block C
For each of b ₁ , Cb ₂ , Cr ₁ and Cr ₂ , the DCT coefficients are arranged in order of frequency from the DC component and the low-frequency component to the high-frequency component. Then, [DC, AC ₁ , AC
_2, AC _3, and..], So that codes are assigned, it is variable length coded.

The stream converter 106 decodes the variable-length coded and arranged DCT coefficients once by decoding the variable-length code to detect a break of each coefficient, and extends the frequency over each DCT block constituting the macro block. Summarize by component. This is shown in FIG. 8B. First, the DC components of the eight DCT blocks in the macroblock are summarized, the AC coefficient components of the eight DCT blocks having the lowest frequency components are summarized, and the AC coefficients of the same order are grouped in order. The coefficient data is rearranged across the DCT blocks.

The rearranged coefficient data is DC
(Y ₁ ), DC (Y ₂ ), DC (Y ₃ ), DC
(Y ₄ ), DC (Cb ₁ ), DC (Cb ₂ ), DC (C
r ₁ ), DC (Cr ₂ ), AC ₁ (Y ₁ ), AC ₁ (Y
₂ ), AC ₁ (Y ₃ ), AC ₁ (Y ₄ ), AC ₁ (Cb
₁ ), AC ₁ (Cb ₂ ), AC ₁ (Cr ₁ ), AC
₁ (Cr ₂ ),. Where DC, AC ₁ ,
AC ₂ ,... Are, as described with reference to FIG. 7, each of the variable-length codes assigned to the set consisting of the run and the subsequent level.

The converted elementary stream in which the order of the coefficient data is rearranged by the stream converter 106 is supplied to the packing and shuffling unit 107. The data length of the macroblock is the same for the converted elementary stream and the elementary stream before conversion. In the video encoder 102, even if the length is fixed in GOP (one frame) units by bit rate control, the length varies in macroblock units. The packing and shuffling unit 107 applies the data of the macroblock to the fixed frame.

FIG. 9 schematically shows the processing of packing macroblocks in packing and shuffling section 107. The macro block is applied to a fixed frame having a predetermined data length and is packed. The data length of the fixed frame used at this time is matched with the sync block length, which is the minimum unit of data during recording and reproduction. This is to simplify the processing of shuffling and error correction coding. In FIG. 9, for simplicity, it is assumed that one frame includes eight macroblocks.

As shown in an example in FIG. 9A, the lengths of eight macroblocks are different from each other due to the variable length coding. In this example, as compared with the length of one sync block, which is a fixed frame, the data of macro block # 1, the data of # 3 and the data of # 6 are each longer, and the data of macro block # 2, the data of # 5, # 7 data and # 8
The data of each is short. The data of the macro block # 4 has a length substantially equal to one sync block.

By the packing process, macro blocks are packed into a fixed-length frame having a length of one sync block. Data can be packed without excess or shortage because the amount of data generated in one frame period is controlled to a fixed amount. As shown in an example in FIG. 9B, a macroblock longer than one sync block is divided at a position corresponding to the sync block length. Of the divided macroblocks, the part (overflow part) that protrudes from the sync block length is placed in an area that is vacant in order from the top,
That is, it is packed after a macroblock whose length is less than the sync block length.

In the example of FIG. 9B, the macro block # 1
The portion that exceeds the sync block length is first packed after the macro block # 2, and when it reaches the length of the sync block, it is packed after the macro block # 5. Next, the portion of the macro block # 3 that is outside the sync block length is packed behind the macro block # 7. Further, the part of the macro block # 6 that protrudes from the sync block length is packed after the macro block # 7, and the part that protrudes further is packed after the macro block # 8. Thus, each macroblock is packed in a fixed frame of the sync block length.

The length of each macroblock can be checked in advance by the stream converter 106.
As a result, the packing unit 107 can know the end of the data of the macro block without decoding the VLC data and checking the contents.

FIG. 10 shows an example of an error correction code used in one embodiment. FIG. 10A shows one ECC block of an error correction code for video data.
B is 1E of an error correction code for audio data.
Indicates a CC block. In FIG. 10A, VLC data is data from the packing and shuffling unit 107. A SYNC pattern, ID, and DID are added to each row of the VLC data, and a parity of an inner code is added to form one SYNC block.

That is, a 10-byte outer code parity is generated from a predetermined number of symbols (bytes) aligned in the vertical direction of the array of VLC data, and the ID, DID, and VLC data (or outer) are aligned in the horizontal direction. Parity of the inner code is generated from a predetermined number of symbols (bytes) of the code parity. In the example of FIG. 10A, 10 outer code parity symbols and 12 inner code parity symbols are added. As a specific error correction code, a Reed-Solomon code is used. FIG.
At 0A, the lengths of VLC data in one SYNC block are different at 59.94 Hz, 25 Hz, 23.
This is because the frame frequency of video data is different, such as 976 Hz.

As shown in FIG. 10B, the product code for audio data is the same as that for video data.
The parity of the 10-symbol outer code and the parity of the 12-symbol inner code are generated. In the case of audio data, the sampling frequency is, for example, 48 kHz.
And one sample is quantized to 16 bits. One sample may be converted into another bit number, for example, 24 bits. According to the difference in the frame frequency described above, 1SYN
The amount of audio data in the C block is different.
As described above, one field of audio data /
One channel forms two ECC blocks.
One ECC block includes one of even-numbered and odd-numbered audio samples and audio AUX as data.

Next, the synchronization detection circuit 132 described above with reference to FIG. 2 will be described in more detail. FIG.
1 shows an example of the configuration of a synchronization detection circuit 132 according to the present invention. The synchronization detecting circuit 132 is adapted to automatically detect sync blocks having different data lengths, and forms the gist of the present invention.

In the following, this synchronization detection circuit 132
Then, 2 such that [L> K] and [2K> L]
It is assumed that sync blocks having different data lengths L and K are detected. The data lengths L and K correspond to L and K clocks of a clock of a predetermined frequency.

When the bit serial input data is input to terminal 1
Is entered for This input data is supplied to a shift register L10, a shift register K11, a comparison (L) circuit 12
, One input terminal of a comparison (K) 13 circuit, and a sink comparison circuit 14.

Shift register L10 and shift register K11 have bit lengths corresponding to data lengths L and K, respectively. The output of the shift register L10 is 2L
A delay line 19 having a delay of one minute and the other input terminal of the comparison (L) circuit 12 corresponding to the synchronization pattern of length L are supplied. The output of the shift register K11 is the length K
Is supplied to the other input terminal of the comparison (K) circuit 13 corresponding to the synchronization pattern of The synchronization pattern detection result by the sync comparison circuit 14 and bit shift amount information indicating at which bit position the synchronization pattern matches are supplied to the comparison (L) circuit 12 and the comparison (K) circuit 13, respectively.

The detection result and the shift amount in the comparison (L) circuit 12 are supplied to the sync detection circuit 15 as a signal CL. Similarly, the detection result and shift amount in the comparison (K) circuit 13 are supplied to the sync detection circuit 15 as a signal CK. In the sync detection circuit 15, the signal CL or the signal C
Based on K, detection and hold of the sync information are performed. The held sync information is phase-controlled by the phase control circuit 16 and written to the sync RAM 17. The sync information is read from a position corresponding to the length (2L−K) from the top in the sync RAM 17 and supplied to the inertia circuit 18.

On the other hand, the output control circuit 20
From M17, the sync information delayed by (3L-K) is supplied, and the synchronization pulse generated by the inertia circuit 18 is supplied. Input data stored in the delay line 19 is read out based on the supplied sync information and synchronization pulse, and is derived to the output terminal 21 as a sync block. Further, the synchronization pulse generated by the inertia circuit 18 is also output to the output terminal 22.

Next, the processing in the synchronization detecting circuit 132 will be described in more detail. As mentioned above,
In the sync block, a synchronization pattern is provided in the first two bytes, an ID number (ID0) is provided in the third byte, and additional information (ID1) is provided in the fourth byte. The type of data stored in the sync block is described in the additional information.

In practice, the sync block simply handles serial data reproduced from the recording medium in units of one byte, which is serial-parallel converted for every 8 bits. Are input in a bit-shifted state. This is shown in FIG. The input data is simply 8 as shown in FIG.
Bits (1 octet) are treated as a unit. FIG.
B, as shown in an example, the delimiter of the input data does not always correspond to the delimiter of the original (recording) data, and the data of each byte is, for example, as shown in FIG. In this example, the input data is shifted by 3 bits with respect to the division of the input data.

The bit shift amount between the input data and the original data is determined based on how much the data is shifted to obtain a unique synchronization pattern when the synchronization pattern is detected. Here, a description will be given assuming that the bit shift amount of the input data string is 0 and matches the original data. In this example, reference is made to input data and data delayed by L and K clocks with respect to the input. Then, the data is verified whether the bit-shifted value matches the unique synchronization pattern, the continuity of the ID number and the identity of the ID information, and if all the data are correct, the synchronization pattern is detected. It is judged that it was done.

FIG. 13A shows an example of input data input from the input terminal 1. The length of each sync block starting from the sync pattern is indicated by L. This input data is supplied to the input terminal 1 and sequentially supplied to the shift register L10 and the shift register K11. When data is continuously input, the register in the shift register L10 enters a state as shown in FIG. 14A. In FIG. 14A,
SYNC (L) indicates the first eight bits of the synchronization pattern, and SYNC (H) indicates the second eight bits.

The input data directly from the input terminal 1 and the output of the shift register L 10 are supplied to one and the other input terminals of the comparison (L) circuit 12. For example, data supplied to one input terminal of the comparison (L) circuit 12 is:
The data at the position “A” in FIG. 14A and the data supplied to the other input terminal are the data at the position “B”.

The comparison (L) circuit 12 has a configuration as shown in FIG. 15, for example. The comparison (K) circuit 13 has the same configuration. Shift register L10
Is input from a terminal 30, and 8 bits are stored in 8-bit parallel registers 31 and 32, respectively. Similarly, input data from the input terminal 1 is input from a terminal 34, and 8-bit parallel registers 35 and 36 store 8 bits each. The EXOR circuits 33, 37 and NO determine whether the data stored in the registers 31, 32 and the data stored in the registers 35, 36 match.
A check is made using the R circuit 38. This is shown in FIG. 14B. The comparison result is output to the output terminal 39.

It is to be noted that the input data is checked in advance by the sync comparison circuit 14 as to whether it matches the synchronization pattern, and the result is compared with the comparison (L) circuit 12 and the comparison (K) circuit 13.
Respectively. In the sink comparison circuit 14, FIG.
As shown in an example in FIG. 6, input data latched internally is compared with an 8-bit synchronization pattern at each bit position. From the sync comparison circuit 14, the comparison (L) circuit 12 and the comparison (K) circuit 13 provide a detection result indicating whether a synchronization pattern has been detected and, if a synchronization pattern has been detected, which bit A bit shift amount indicating whether the positions match is supplied.

By performing such processing, when a synchronization pattern is input at intervals of the data length L, the comparison (L) circuit 12 synchronizes at the same bit position detected by the sync comparison circuit 14. It can be detected that the patterns match. Then, the detection result and the bit shift amount are output as the signal CL. As a result, FIG.
The position of each sync block shown in FIG. 3A can be confirmed.

On the other hand, in the shift register K11,
Since the bit length of the register is shorter than the number of bytes of the input sync block, the state shown in FIG. 14A is not obtained. This detection circuit does not detect the synchronization pattern.

Similarly, when sync blocks having a data length of K are successively input, at this time, the shift register K11 and the comparison (K) circuit 13 operate as shown in FIG.
Since the state shown in FIG. 4A and the state shown in FIG. 14B are obtained, it is possible to detect the coincidence of the synchronization patterns. In this case, the shift register L10 and the comparison (L) circuit 12
14B, the synchronization pattern is not detected on the detection circuit side.

As described above, a plurality of sync blocks can be detected by using the circuit of FIG. 11 without specially providing data length information on input data. In principle, by providing a shift register and a comparison circuit for each data length to be detected, the types of data lengths that can be detected simultaneously can be increased.

Next, a method for generating a synchronization pulse indicating the head position of a sync block when outputting input data will be described. Originally, the synchronization detection circuit 132
The data handled in step (1) is data to which sync blocks are continuously input as shown in FIG. 13A. However, there is a possibility that only a part of data or a certain continuous section has been lost due to an error or the like generated in the process of recording and transmission. Since the data portion of the sync block, that is, the data packet, forms an error correction code, even if a part of the data including the synchronization pattern is lost, there is a possibility that the error can be corrected. However, in order to execute the error correction process, the head of the error correction code, that is, the position of the head of the sync block needs to be correctly detected.

Considering that sync blocks of the same length are continuously recorded in the same sector, once a synchronization pattern is detected with a specific data length, the data length at that time is detected. It is highly probable that the sync blocks are arranged at intervals of. Therefore, even if the synchronization pattern cannot be detected, there is a possibility that data can be reproduced based on the synchronization pulse by continuing to output the previously detected synchronization pulse until the next synchronization pattern is detected. For example, as shown in FIG. 13C, the sync block can be correctly reproduced based on the synchronization pulse corresponding to the sync block length as shown in FIG. 13B.

As means for this purpose, a circuit is used which outputs a pulse at regular intervals in synchronism with the start of output data once a synchronization pattern has been detected. The above-mentioned inertia circuit 18 corresponds to this circuit.

FIG. 17 shows an example of the configuration of the inertia circuit 18 described above. This circuit 18 has data lengths L and K
This corresponds to the two types of data length. An identification signal L / K for determining the data length to be either L or K is supplied to the terminal 50. Identification signal L / K
For example, the detection of the synchronization pattern
This is an identification signal indicating whether the operation was performed using L or the shift register K11. Further, a signal (start pulse) corresponding to the timing of detecting the synchronization pattern is supplied to the terminal 51.

The start pulse is supplied to the start terminal ST of the L / K counter 52 and also to one input terminal of the OR circuit 58 via the switch circuit 54 whose terminal 51 is initially selected. The output of the OR circuit 58 is supplied to a load input terminal of a counter 59 described later.

The identification signal L / K input to the terminal 50 is
It is supplied to the enable terminal EN of the L / K counter 52 and is used as a selection control signal of the switch circuit 53. Switch circuit 53 selects input terminals 53A and 53B according to the content of identification signal L / K. In response to the selection of the input terminals 53A and 53B, initial values corresponding to the data lengths L and K are supplied and loaded from, for example, a system controller (not shown) to the load data terminal of the counter 59.

The counter 59 counts down from the loaded initial value based on a predetermined clock. And the count value is

When [0] is reached, a synchronization pulse is output for one clock. The output sync pulse is
The signal is output to the output terminal 60 and supplied to the other input terminal of the OR circuit 58. When the synchronization pulse is output, the initial value is loaded again via the switch circuit 53, and the countdown is restarted.

The count by the counter 59 is determined by the OR circuit 5
The process is started with the pulse output from 8 as a starting point. That is, the start point is either the start pulse supplied from the terminal 51 or the synchronization pulse output from the counter 59. And even during the counting,
When the pulse is supplied from the OR circuit 58, the initial value is loaded from the load data terminal, and the countdown from the initial value is started. Therefore, even if the detection position of the synchronization pattern of the input data changes, the initial value is loaded during the counting, so that the synchronization pulse following the input data can be output. The switch circuit 54 is appropriately selected according to the operation of the circuit 18. Depending on the selection of the switch circuit 54, L /
The output from the K counter 52 is the starting point.

FIG. 18 shows an example of operation timing in the inertia circuit 18 when the data length is L. The counter 59 counts down based on the clock of FIG. 18A. For example, a start pulse and an identification signal L / K are input at timing A (FIGS. 18B and 18C). Then, at the next clock, the initial value corresponding to the data length L is input from the load data terminal, and the countdown from the initial value is performed (FIG. 18D). And the count value is

When it reaches [0] (timing B), a synchronization pulse is output as shown in FIG. 18E even if no start pulse is input. Thus, once started, a synchronization pulse can be output at regular intervals.

As shown at timing C, the counter 5
If a start pulse is input during the countdown by 9, the initial value is loaded at that time. further,
Like timing D, the count value

Even when the input of [0] and the input of the start pulse are performed at the same time, the initial value is loaded at that time in the same manner as at the timing B described above.

As described above, the synchronization pulse is output L clocks after the start pulse is input. on the other hand,
Even when the data length is K, (L
-K) The delay for the clock is adjusted (described later),
Thereafter, the countdown by the counter 59 is started. Therefore, when outputting the output data (sync block), it is necessary to delay by L clocks. This delay of the output data is performed using the delay 19B in the delay line 19 in FIG.

Next, a method of transmitting the detection result of the synchronization pattern to the inertia circuit 18 will be described with reference to FIGS. First, referring to FIG.
The case will be described. FIG. 19 shows the synchronization pattern input at the latest timing A, and shows that the synchronization pattern is input to the input terminal 1 in the order of D, C, B, and A. The sync blocks corresponding to the synchronization patterns input at the respective timings of A, B, C, and D are respectively referred to as sync blocks A,
Called B, C and D.

When a synchronous pattern is detected at the timings A and B in FIG. 19, each data is stored in the shift register L10 and the delay line 19 as shown in FIG. 20, respectively. That is, the sync block C is stored in the delay 19B in the delay line 19, and the sync block B is stored in the delay 19A.
On the other hand, the sync block A is stored in the shift register L10.

The inertia circuit 18 must be started for the sync block B. The storage position on the sync RAM 17 corresponding to the head of the sync block B is a position advanced by (LK) from the head of the sync RAM 17, that is, (a position that is 2 L ahead of the final output position of the sync RAM 17. In the sync RAM 17, the sync pattern detection information, the sync block length, and the bit shift amount of the sync block are stored at the position corresponding to each sync block, and the inertia is calculated from the storage position L clocks before the final output position. Synchronization pattern detection information is output to the circuit 18. The synchronization pattern detection information is, for example, an identification signal L / K.

FIG. 21 shows an example in which the data length is K. Also in this case, the operation is performed in the same manner as when the data length is L. When the data length is K, the sync pattern detection information for the sync block B is read from the top of the sync RAM 17, that is, from the last output position by (3L).
−K). Therefore, the timing of the sync block B in the delay line 19 and the timing of the corresponding data in the sync RAM 17 are the same.

Here, the data output position from the sync RAM 17 to the inertia circuit 18 is read at a position L clocks before the final output position of the sync RAM 17 regardless of whether the sync block length is L or K. On the other hand, when the sync block length is K, the inertia circuit 18 also outputs a sync pulse with a K clock cycle. In this state, the output phase of the sync pulse and the output phase of the sync block data in the delay line 19 become ( LK) clocks.

Therefore, L / K in the inertia circuit 18
A counter 52 is used (FIG. 17). The L / K counter 52 is a counter that counts only the difference between the data lengths L and K. The L / K counter 52 performs a count operation based on the identification signal L / K supplied from the terminal 50 to the enable terminal EN only when the sync block length is K. By a system controller not shown,
Data lengths L and K are supplied as initial values. L / K
The counter 52 receives a signal from the terminal 51 and receives a start signal S
Triggered by a start pulse supplied to T.
When activated, the countdown starts from (LK) and the count value becomes

When it becomes [0], a pulse for one clock is output.

The switch circuit 54 is switched so as to select the output of the L / K counter 52 when the output of the sink RAM 17 to the inertia circuit 18 is the sync block length K. The output pulse is supplied to the switch circuit 5
4 and to the load terminal of the counter 59 via the OR circuit 58. Thus, the counter 59 reads the initial value from the load data terminal, and restarts the countdown. As described above, by delaying the re-counting by the counter 59 by the L / K counter 52, the synchronization pulse output of the inertia circuit 18 and the output timing of the delay line 19 and the sync RAM 17 are adjusted so as to match.

The writing to the sink RAM 17 is controlled by the phase control circuit 16. When the detection result of the synchronization pattern is supplied from the comparison (L) circuit 12 or the comparison (K) circuit 13 to the sync detection circuit 15 and a detection report is issued, the sync detection circuit 15 performs the synchronization To the phase control circuit 16, that is, information on which of the comparison (L) circuit 12 and the comparison (K) circuit 13 has received the detection report.

The phase control circuit 16 obtains a write address to the sink RAM 17 based on this information and creates data to be written to the sink RAM 17. As described above, the sync detection flag block length information (L / K) and the bit shift amount are written to the sync RAM 17. They are created by the phase control circuit 16. The write address for the sink RAM 17 is, as described with reference to FIGS.
When the data length is K, the sync block B for starting the process by the inertia circuit 18 is written from the top of the sync RAM 17, and when the data length is L, the data is (LK) clocks from the top of the sync RAM 17. Written from the delayed position.

Note that when recording a data string on a recording medium,
The data length and the identification information for identifying the sync block can be stored in advance in the data of the sync block. By doing so, it is possible to check the validity of the detected data length and the sync block type at the time of reproduction, and prevent erroneous processing by application software at the subsequent stage.

In this application example, the sync block length of video data and audio data is determined in advance, and
Only when the relationship between the flag indicating audio / video in the D information (ID1) and the data length of the detected sync block matches, it is possible to consider that a correct synchronization pattern has been detected.

As such identification information, for example, ID1, DID and length information LT in the sync block can be used.

In this embodiment, the sync detection circuit 15
In, this check is performed. That is, if it is determined by this check that the pattern is invalid, it is determined that the synchronization pattern has not been detected, and the above-described report to the phase control circuit 16 is not performed.

The sync detection information is reflected on the output data. That is, the output control circuit 20, which is the final output stage, outputs the output data from the delay line 19 based on the output of the inertia circuit 18 and the synchronization pattern detection information.
The data is shifted by the bit shift amount and restored to the original data in 1-byte units.

FIG. 22 shows an example of data output from the output control circuit 20. In this example, the data length L is [6]
It has been. The overall operation is performed based on the clock of FIG. 22A. The input data from the terminal 1 follows the sync block A having the data length of [6], followed by the data length of [4].
Is the data gap corresponding to. Subsequently, a sync block C whose data length is (6) is input. in this way,
A synchronization pattern is detected from the input data and a counter 59
Thus, the countdown is performed from the data length L. The count value is

At [0], a synchronization pulse is generated and data is output. Even if a data gap having a different data length (L>) is input while the data length remains [6], when the next normal sync block C is input, the count value is increased.

Before reaching [0], the countdown is started from the value corresponding to the data length L. As a result, the sync block is output normally.

In the above description, the synchronization pattern is referred to at intervals of data lengths L and K, but this is not limited to this example. That is, in the same processing, L,
, NL, K, 2K, 3K, ..., mK
It is also possible to refer to the synchronization pattern at intervals of.

Further, in the above description, a magnetic tape is used as the recording medium, but this is not limited to this example. The present invention can be applied to a disk-shaped recording medium such as a hard disk and a magneto-optical disk. Further, the present invention can be applied not only to a recording medium but also to data transmitted via communication such as a network.

[0145]

As described above, according to the present invention, when the phase of each sync block is detected from a digital data string composed of sync blocks of a plurality of lengths, the block length to be detected is switched. Since there is no need to input a signal or the like from the outside, there is an effect that the system configuration of the reproducing apparatus can be simplified.

Further, according to this embodiment, since the data output is controlled based on the difference between the input different sync block lengths, processing is performed so that the data is not lost at the point where the sync block length is switched. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration on a recording side according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a reproducing side according to an embodiment of the present invention.

FIG. 3 is a schematic diagram illustrating an example of a track format.

FIG. 4 is a schematic diagram illustrating another example of a track format.

FIG. 5 is a schematic diagram illustrating a plurality of examples of a configuration of a sync block.

FIG. 6 shows an ID and a DID added to a sync block.
FIG.

FIG. 7 is a schematic diagram for explaining an output method of a video encoder and variable-length encoding.

FIG. 8 is a schematic diagram for explaining rearrangement of an output order of a video encoder.

FIG. 9 is a schematic diagram for explaining a process of packing data rearranged in order into a sync block.

FIG. 10 is a schematic diagram for explaining an error correction code for video data and audio data.

FIG. 11 is a block diagram showing an example of a configuration of a synchronization detection circuit according to the present invention.

FIG. 12 is a schematic diagram for explaining bit shift of input data.

FIG. 13 is a schematic diagram for explaining input data and a synchronization pulse.

FIG. 14 is a schematic diagram for explaining sync detection using a shift register.

FIG. 15 is a block diagram illustrating an example of a configuration of a comparison (L) circuit and a comparison (K) circuit.

FIG. 16 is a schematic diagram for explaining synchronization pattern detection in the sync comparison circuit.

FIG. 17 is a block diagram showing an example of a configuration of an inertia circuit according to the present invention.

FIG. 18 is a timing chart showing an example of operation timing in the inertia circuit.

FIG. 19 is a schematic diagram for explaining a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 20 is a schematic diagram illustrating a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 21 is a schematic diagram illustrating a method of transmitting a detection result of a synchronization pattern to an inertia circuit.

FIG. 22 is a timing chart showing an example of data output from the output control circuit.

FIG. 23 is a schematic diagram schematically showing an example of the arrangement of each sector on a track.

FIG. 24 is a block diagram illustrating an example of a configuration of a sync detection circuit according to the related art.

[Explanation of symbols]

10 shift register L, 11 shift register K, 12 ... comparison (L) circuit, 13 ... comparison (K) circuit, 14 ... sync comparison circuit, 15 ... sync detection Circuit, 16 ... Phase control circuit, 17 ... Sink RAM, 18 ... Inertia circuit, 19 ... Delay line, 20 ... Output control circuit, 52 ... L
/ K counter, 59 counter, 100 recording / reproducing device, 114 AUX addition circuit, 116
Outer code encoder, 117... Shuffling, 118
... ID addition circuit, 119 ... inner encoder
120: synchronous addition circuit, 123: magnetic tape,
132: synchronization detection circuit, 133: inner code decoder, 134: ID interpolation circuit, 151: deshuffling circuit, 152: outer code decoder, 153 ...
.AUX separation circuit, 155... Interpolation circuit, 156.
・ Output section

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C053 FA21 FA22 GB01 GB05 GB10 GB15 GB18 GB21 GB37 HA01 HA04 JA01 JA07 JA21 JA24 KA01 KA09 LA06 5D044 AB05 AB07 BC01 CC03 DE03 DE32 GM26

Claims (9)

[Claims] 1. A synchronization detection device for detecting synchronization of data blocks having at least two different data lengths having a synchronization pattern for detecting synchronization, wherein a synchronization pattern is detected for input data. And storing the input data in order for each predetermined unit length,
A first memory unit having a length corresponding to a first data length L for outputting stored data from the oldest unit for each of the predetermined unit lengths; First comparing means for detecting whether both data input to the memory means and data output from the first memory means coincide with the synchronization pattern; and Input data is input, the input data is stored in order for each of the predetermined length units, and the stored data is output from the oldest order for each of the predetermined unit lengths, shorter than the first data length L, and A second memory unit having a length corresponding to a second data length K which is not an integral multiple of the first data length L; and a second memory unit based on a detection result of the pattern detection unit. Enter in And second comparing means for detecting whether both the data to be output and the data output from the second memory means coincide with the synchronization pattern. The first comparing means and the second comparing means A synchronization detecting device, wherein when one of the means detects the coincidence of the synchronization pattern, the synchronization is detected. 2. The synchronization detection device according to claim 1, wherein the first data length L and the second data length K are:
A synchronization detection device characterized by a relationship of (L> K) and (2K> L). 3. The synchronization detecting device according to claim 1, wherein: a delay unit for delaying the input data; and, when the synchronization is detected, outputting a synchronization signal at an interval corresponding to a data length in which the synchronization is detected. A synchronization signal generation unit; and an output control unit that outputs data from the delay unit in synchronization with the synchronization signal generated by the synchronization signal generation unit, wherein the synchronization signal generation unit includes: If the comparison means detects the coincidence of the synchronization pattern, the first
Wherein the synchronization signal is output after being delayed by a time corresponding to the difference between the data length of the second data length and the second data length. 4. The synchronization detection device according to claim 1, wherein the first and second data lengths stored for each of the data blocks having the first and second data lengths correspond to the first and second data lengths. A synchronization detection device, wherein the identification information is compared with a result of the synchronization detection. 5. At least two different recording mediums each having a synchronization pattern for detecting synchronization recorded on a recording medium.
A reproducing apparatus for reproducing a data block having two data lengths, a synchronous pattern detecting means for detecting a synchronous pattern for the reproduced data reproduced from the recording medium, and storing the reproduced data in order for each predetermined unit length,
A first memory unit having a length corresponding to a first data length L for outputting stored data from the oldest unit for each of the predetermined unit lengths; First comparing means for detecting whether both data input to the memory means and data output from the first memory means coincide with the synchronization pattern; and Playback data is input, the playback data is stored in order for each of the predetermined length units, and the stored data is output from the oldest order for each of the predetermined unit lengths, shorter than the first data length L, and A second memory unit having a length corresponding to a second data length K which is not an integral multiple of the first data length L; and a second memory unit based on a detection result of the pattern detection unit. Enter in Second comparing means for detecting whether both the data to be output and the data output from the second memory means coincide with the synchronization pattern, and among the first comparing means and the second comparing means If the coincidence of the synchronization pattern is detected in any one of them, it is determined that the synchronization has been detected, and the reproduced data is detected by the first comparison means and the second comparison means. Output means for outputting in units of data blocks each having a data length corresponding to the reproduced data. 6. The reproducing apparatus according to claim 5, wherein the first data length L and the second data length K are:
A playback device characterized by the relationship of (L> K) and (2K> L). 7. The reproducing apparatus according to claim 5, wherein: a delay means for delaying the reproduced data; and a synchronizing signal for outputting a synchronizing signal at an interval corresponding to a data length in which the synchronism is detected when the synchronism is detected. Signal generating means; and output control means for outputting data from the delay means in synchronization with the synchronizing signal generated by the synchronizing signal generating means, wherein the synchronizing signal generating means comprises: Means for detecting the match of the synchronization pattern,
Wherein the synchronization signal is output after being delayed by a time corresponding to the difference between the data length of the second data length and the second data length. 8. The reproduction apparatus according to claim 5, wherein the first and second data blocks output from the output unit and having the first and second data lengths are stored. A reproducing apparatus characterized by comparing identification information corresponding to a second data length with a result of the synchronization detection. 9. A synchronization detection method for detecting synchronization of data blocks having at least two different data lengths having a synchronization pattern for detecting synchronization, wherein the first data length L corresponds to the first data length L. In the memory, the input data is sequentially stored for each predetermined unit length, and
Outputting the data stored from the first memory for each of the predetermined unit lengths, starting from the oldest one; and a relationship between the first data length L and an integral multiple of the first data length L. The input data is input simultaneously with the first memory to a second memory having a length corresponding to a second data length K that does not exist, and the input data is sequentially stored in units of the predetermined length. Outputting the data stored in the second memory from the oldest unit for each of the predetermined unit lengths; detecting a synchronous pattern with respect to the input data; Based on the detection result of the step,
A first comparing step of detecting whether both the data input to the first memory and the data output from the first memory coincide with the synchronization pattern, and detecting the pattern detecting step Based on the result, a second comparing step of detecting whether both the data input to the second memory and the data output from the second memory match the synchronization pattern, A synchronization detection method, wherein if one of the first comparison step and the second comparison step detects the coincidence of the synchronization patterns, the synchronization is detected.