JP2000151393A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a digital PLL circuit which can generate a clock signal, whose phase and frequency are stable and suppress generation of jitters. SOLUTION: This PLL circuit divides the frequency of a reference clock RFCK and inputs the frequency-divided signal ck0 to a phase comparator 10a and its inverted signal ck to a frequency multiplier 30a, the phase comparator 10a outputs an up signal Sup or down signal Sdw according to the phase difference between the signal ck0 and frequency-divided signal DCK, and a counter 20a outputs a count value M corresponding to the phase difference signal, and the frequency multiplier 30a outputs a multiplied clock signal PLCK of frequency set with the count value M and when a mask signal mk is inputted from the frequency divider 40, the phase of the multiplied clock PLCK is corrected corresponding to the clock signal ck. A frequency divider 40a divides the frequency of the multiplied clock PLCK at a preset frequency division ratio N, outputs the frequency-divided signal DCK, and further generates a mask signal mk at a prescribed ratio with respect to the frequency-divided signal DCK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL circuit capable of suppressing generation of jitter and generating a clock signal having a stable phase and frequency.

[0002]

2. Description of the Related Art In a digital PLL circuit composed of a phase comparator, a counter and a frequency multiplier, a clock signal is generated by a frequency multiplier at a frequency controlled by the count value of the counter. Therefore, a clock signal having a predetermined frequency or phase can be generated by following the phase of the reference signal _Sref input to the phase comparator.

FIG. 13 shows a general digital P described above.
1 shows an example of an LL circuit. As shown, the digital PLL circuit includes a phase comparator 10, a counter 20, a frequency multiplier 30, and a frequency divider 40.
The phase comparator 10 compares the phases of the reference clock RFCK of the frequency f _{0 and} the frequency-divided signal S40 from the frequency divider 40, and outputs up / down signals S _up and S _dw to the counter 20 according to the comparison result. . For example, when the frequency of the frequency-divided signal S40 from the frequency divider 40 is lower than the reference clock RFCK, an up signal S _up is generated and output to the counter 20,
Conversely, when the frequency of the frequency-divided signal S40 from the frequency divider 40 is higher than the reference clock RFCK, the down signal _Sdw is generated and output to the counter 20.

The counter 20 sets the count value S20 of m (m = 1, 2, 3,...) Bits according to the up / down signal from the phase comparator 10, and sets the count value S20.
Is output to the frequency multiplier 30. The frequency multiplier 30 has almost the same function as a voltage controlled oscillator (VCO) in an analog PLL circuit, and controls the frequency of an oscillation signal to be output according to an input control signal. Here, the frequency multiplier 30 is a so-called digitally controlled oscillation circuit that controls the frequency of the oscillation signal S30 according to the input count value S20. The frequency divider 40 has a preset frequency division ratio N
(N = 1, 2, 3,...), The frequency of the oscillation signal S30 from the frequency multiplier 30 is divided, and the frequency-divided signal S40 is
Output to

In the PLL circuit thus configured, when the phase comparator 10 obtains a comparison result indicating that the phase of the divided signal S40 matches the phase of the reference clock RFCK, the PLL circuit reaches a locked state. At this time, the frequency f ₁ of the output signal S30 of the frequency multiplier 30 is the frequency divider 4
It is determined by the division ratio N of 0 and the frequency f ₀ of the reference clock RFCK, and f ₁ = Nf ₀ .

The output signal S30 of the frequency multiplier 30 is supplied to the outside as a clock signal PLCK. Divider 4
By setting the frequency division ratio N to 0, a clock signal PLCK having a desired frequency can be obtained.

[0007]

In the above-described conventional PLL circuit, the oscillation frequency of the frequency multiplier 30 is controlled in accordance with the count value which is a digital signal. The division ratio cannot be divided by N. Further, since the change in the count value of the counter is a fixed value (± 1 in most cases), there is a disadvantage that the phase shift cannot be corrected at high speed.

Here, assuming that the value of the count value S20 is larger, the frequency of the multiplied clock signal P generated by the frequency multiplier is increased.
Assuming that the frequency of the LCK becomes lower, as shown in FIG. 14, the phase comparison is affected by the phase comparison and the phase shift cannot be corrected, so that the period of the generated clock signal PLCK is slower than the target. Nevertheless, the result of the phase comparison may be counted up or vice versa. Therefore, the period of the generated signal is tl to tf
~ Ts, and the phase is not determined. As a result, not only the phase jitter with the reference clock PFCK but also the period jitter of the generated clock signal PLCK increases.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a digital PLL circuit capable of generating a clock signal having a stable phase and frequency and suppressing generation of jitter. .

[0010]

To achieve the above object, a digital PLL circuit according to the present invention compares the phase of a reference signal with the phase of a signal to be compared, and calculates the phase difference between the reference signal and the signal to be compared. A phase comparison circuit that outputs a phase difference signal in response to the phase difference signal, a counter that counts according to the phase difference signal, and outputs a count value corresponding to a phase difference between the reference signal and the comparison target signal; An oscillation circuit that generates a clock signal at a frequency set according to the above, and when a correction control signal is input from outside, an oscillation circuit that corrects the phase of the clock signal based on the reference signal; A frequency dividing circuit that divides the frequency by a frequency ratio, supplies the frequency-divided signal as the comparison target signal to the phase comparison circuit, and generates the correction control signal at a predetermined ratio with respect to the frequency-divided signal.

Further, the digital PLL circuit of the present invention comprises:
A phase comparison circuit that compares the phases of the reference signal and the signal to be compared and outputs a phase difference signal according to the phase difference between the reference signal and the signal to be compared, and counts according to the phase difference signal, A counter that outputs a count value corresponding to the phase difference between the reference signal and the comparison target signal, and a clock signal having a frequency set according to the count value, a correction control signal is input from the outside, An oscillation circuit that corrects the phase of the clock signal based on the reference signal when the phase of the reference signal and the signal to be compared that are input to the phase comparison circuit are not the same; A frequency dividing circuit that divides the frequency by a frequency ratio, supplies the frequency-divided signal to the phase comparison circuit as the comparison target signal, and generates the correction control signal at a predetermined ratio with respect to the frequency-divided signal. .

In the present invention, preferably, the oscillation circuit has a loop circuit including a delay circuit whose delay time is controlled by the count value from the counter. Specifically, for example, the oscillation circuit is set by a first input signal, a first output signal is set to a high level, a second output signal is set to a low level, and reset by a second input signal. A flip-flop circuit in which the first output signal is set to a low level and the second output signal is set to a high level; and a falling edge of the first output signal is detected. A first edge detection circuit that outputs a pulse signal, a second edge detection circuit that detects a falling edge of the second output signal, and outputs a second pulse signal according to a detection result; A first delay circuit that delays one pulse signal by a delay time set according to the count value and outputs a first delay signal; and sets the second pulse signal according to the count value. Time delay A second delay circuit that outputs a second delay signal with only a delay, a signal holding circuit that holds the phase difference signal from the phase comparison circuit according to the timing of the reference signal, and a holding signal of the signal holding circuit. A logic gate circuit that outputs a logical product of the reference signal and the correction control signal, and a logical sum of the first delay signal and the output signal of the logical gate as the first input signal, which is supplied to the flip-flop. A first gate circuit for inputting the signal; and a second gate circuit for inputting the second delay signal as the second input signal to the flip-flop.

Further, in the present invention, preferably, when the correction control signal is input, the first delay signal from the first delay circuit is held at a low level, and the flip-flop is accordingly The first output signal is held at a low level and the second output signal is held at a high level. When the holding signal of the signal holding circuit is at a high level, the first output signal corresponds to a rising edge of the reference signal. The flip-flop is set and the first
Is set to a high level, and the second output signal is set to a low level.

According to the present invention, a clock signal is generated by an oscillating circuit, for example, a frequency multiplying circuit that can be controlled by data (count value) to which an oscillating frequency is input, and the clock signal is set to a predetermined dividing ratio. And a divided signal is output. The phase comparison circuit compares the phases of the frequency-divided signal and a reference signal input from the outside, and outputs a phase difference signal corresponding to the phase difference between these signals. A counter outputs a count value corresponding to the phase difference signal, and the counter value is supplied to the frequency multiplier, and the oscillation frequency of the frequency multiplier is controlled accordingly. In the digital PLL circuit thus configured, the frequency of the clock signal output from the frequency multiplier is determined by the frequency of the reference signal and the frequency division ratio of the frequency divider. Further, the frequency divider circuit outputs a correction control signal at a predetermined ratio with respect to the frequency-divided signal, and the frequency multiplier circuit corrects the phase of the clock signal in accordance with the correction control signal in accordance with the reference signal. ,
The phase and frequency jitters of the reference signal are suppressed, and a stable clock signal is generated.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a digital PLL circuit according to the present invention. As shown, the digital PLL circuit according to the present embodiment includes a phase comparator 10a, a counter 20a, a frequency multiplier 30a, a frequency divider 40a, and a frequency divider 50.

The frequency divider 50 divides the frequency of the reference clock RFCK input at a preset frequency division ratio R, and outputs a frequency-divided clock signal ck0 to the phase comparator 10a.
An inverted signal ck of the frequency-divided signal is output to the frequency multiplier 30a. Here, assuming that the frequency of the reference clock RFCK is f ₀ , the frequency-divided clock signal c output by the frequency divider 50
The frequency of k0 or its inverted signal is (f ₀ / R).

The phase comparator 10a receives a frequency-divided clock signal ck0 from the frequency divider 50 and a frequency-divided signal DCK from the frequency divider 40a.
And outputs the up / down signals S _up and S _dw to the counter 20a according to the comparison result. For example, when the frequency of the frequency-divided signal DCK from the frequency divider 40a is lower than that of the clock signal ck0, the up signal S _up is generated and output to the counter 20a. If the frequency is high, a down signal S _dw is generated and output to the counter 20a.

The counter 20a counts up or down according to an up / down signal from the phase comparator 10a, sets an m-bit count value M, and outputs the count value M to the frequency multiplier 30a. Frequency multiplier 30a is a digital control oscillator for controlling the frequency f ₁ of the multiplied clock signal PLCK in accordance with the count value M is inputted. The frequency divider 40a divides the frequency of the frequency-multiplied clock signal PLCK from the frequency multiplier 30a by a preset frequency division ratio N (N = 1, 2, 3,...), And
Is output to the phase comparator 10a.

In the PLL circuit thus configured, the phase comparator 10a obtains a comparison result in which the phase of the frequency-divided clock signal ck0 from the frequency divider 50 matches the phase of the frequency-divided signal DCK from the frequency divider 40a. At this time, the PLL circuit reaches a locked state. At this time, the frequency f ₁ of the output signal PLCK of the frequency multiplier 30a is determined by the frequency dividing ratios N and R of the frequency divider 40a and the frequency divider 50 and the frequency f ₀ of the reference clock RFCK, and (f ₁ = Nf _0). / R).

The multiplied clock signal PLCK generated by the frequency multiplier 30a is supplied to the outside. Frequency divider 40
a, by appropriately setting the frequency division ratios N and R of frequency divider 50, clock signal PLC having desired frequency f ₁
K is obtained.

FIG. 2 is a circuit diagram showing an example of the configuration of the frequency multiplier 30a. As shown, the frequency multiplier 30-
1 is a rising edge detection circuit (rise edge detection circuit)
Detection circuit) 308, falling edge detection circuit (fal
l edge detection circuit) 302, 304, delay circuit 30
1 (delay circuit L), 303 (delay circuit H), RS flip-flop 313, and other gate circuits.

The frequency multiplier 30-1 includes a frequency divider 40a.
Mk, the divided clock signal ck generated by the frequency divider 50, and the reset signal re
sest is input. Reset signal rese
t is formed, for example, by a system reset signal that controls reset of the entire PLL circuit. Reset signal r
When the eset and the mask signal mk become high level,
The output signal S _out goes low, and the inverted output signal / S
_out goes high. Note that the output signal S _out is the same signal as the multiplied clock signal PLCK shown in FIG.

As shown, the mask signal mk is AND
Input to gates 307, 309 and 310, respectively. The clock signal ck is inverted by the inverter 305, and the inverted clock signal is output to the AND gates 309 and 31.
0 and the inverter 306. The output signal of inverter 306 is input to AND gate 307.

The output signal of the AND gate 307 is input to the rising edge detection circuit 308. By the rising edge detection circuit 308, the rising edge of the output signal of the AND gate 307 is detected, the detection signal is input to the OR gate 311 with the output signal S _L of the delay circuit 301. A reset signal rese is supplied to the OR gate 312.
Output signal S _H of t and the delay circuit 303 is input. OR
Output signals of the gates 311 and 312 are input to the set terminal S and the reset terminal R of the RS flip-flop 313, respectively. The falling edge of the output signal of the output terminal Q of the RS flip-flop 313 is detected by the falling edge detection circuit 302, and the falling edge detection signal is input to the delay circuit 301. On the other hand, the falling edge of the output signal of the inverted output terminal / Q of the RS flip-flop 313 is detected by the falling edge detection circuit 302, and the falling edge detection signal is input to the delay circuit 303.

The delay circuit 301 or 303 outputs to the output terminal out a delayed signal obtained by delaying the input signal from the input terminal in by a predetermined time according to the count value M from the counter 20a shown in FIG. Delay signals S _L and S _H delayed by delay circuits 301 and 303 are input to OR gates 311 and 312, respectively.
The output signal of the gate is input to the set terminal S and the reset terminal R of the RS flip-flop 313, respectively.

For example, the falling edge of the output signal S _out from the output terminal Q of the RS flip-flop 313 is delayed by the delay circuit 301 and fed back to the set terminal S of the RS flip-flop 313 via the OR gate 311. , RS flip-flop 313 output signal S
_out is the delay time t _{L of the} delay circuit 301 after falling.
After that, get up again. The falling edge of the output signal / S _out of the inverted output terminal / Q of the RS flip-flop is delayed by the delay circuit 303, and the OR gate 3
12, the feedback signal is fed back to the reset terminal R of the RS flip-flop 313, so that the output signal / S _out of the inverted output terminal / Q of the RS flip-flop 313 has passed the delay time t _H of the delay circuit 303 after falling. And get up again. That is, during the high level period of the output signal S _out of the RS flip-flop 313, the delay circuit 30
3 is set by the delay time t _H , and the low level period is set by the delay time t _L of the delay circuit 301.
The period T of the signal S _out or / S _out is determined by the delay circuit 303
And 301 are equal to the sum of the delay times t _H and t _L. That is, a multiplied clock signal PL generated by the frequency multiplier
The period T of CK is (t _H + t _L ), and its frequency f
₁ is 1 / (t _H + t _L ).

For this reason, the delay circuits 301, 303, OR
Gates 311 and 312, RS flip-flop 313 and falling edge detection circuits 302 and 304
A feedback loop having a delay time controlled by the count value M is configured. The feedback loop forms an oscillation circuit,
The oscillation signal S _out at the frequency set by the count value M
And its inverted signal / S _out .

FIG. 3 shows an example of the configuration of the delay circuit 301 or 303. As shown, the delay circuit includes a decoder 320, an OR gate 321 and a plurality of delay elements DL ₀ , DL ₁ ,..., DL _j-1 connected in series.

The decoder 320 decodes the input m-bit count value M to generate a j-bit signal.
Delay element DL _0, DL _1, ..., are output to the DL _j-1. Each delay element is connected to a selection circuit S ₀ ,
S _1, ..., it is constituted by a buffer circuit connected to the output terminal of the S _j-1 and the respective selection circuits.
The selection circuit constituting each delay element outputs an input signal to either the buffer or the output terminal out according to the output signal from the decoder 320. Therefore, the decoder 320
, The signal path from the input terminal in to the output terminal out of the delay circuit differs, and the input signal is output to the output terminal out after a delay time set by the count value M.

The mask signal mk is supplied to the OR gate 321.
And a reset signal reset are input. When one or both of these input signals go high, the output signal of the OR gate 321 goes high,
In response to this, the delay element _{DL 0, DL 1, ...,} DL j-1
Are fixed at, for example, a low level.

FIG. 4 shows the frequency multiplier 30-1 shown in FIG.
FIG. 6 is a waveform chart showing the operation of FIG. Hereinafter, the operation of the frequency multiplier 30-1 will be described with reference to FIGS. In the frequency multiplier shown in FIG. 2, when the mask signal mk is at a high level, phase correction is performed. At this time, the clock signal ck is input to the rising edge detection circuit 308 via the inverters 305 and 306 and the AND gate 307. The rising edge of the clock signal ck is detected by the rising edge detection circuit, and the detection signal is input to the OR gate 311. OR gate 311
The RS flip-flop 313 is set according to the output signal of. For this reason, the phase of the output signal S _out of the frequency multiplier is corrected by the clock signal ck.

As shown in FIG. 4, the reset signal rese
When t is at the high level, the output signal S _out of the RS flip-flop 313 is held at the low level, and the inverted output signal / S _out is held at the high level. Reset signal r
When eset switches from high level to low level,
The frequency multiplier starts operating. The output signal of the AND gate 307 rises in response to the rising edge of the clock signal ck. The rising edge is detected by the rising edge detection circuit 308, and the detection signal is input to the OR gate 311. Therefore, the output signal of the OR gate 311 rises, whereby the RS flip-flop 313 is set, and the output signal S _out rises. Also, the inverted output signal / S _out falls.

The falling edge of the inverted output signal / S _out of the RS flip-flop 313 is detected by the falling edge detection circuit 304, and a detection signal, for example, a pulse signal having a narrow width is detected by the delay circuit 303 at time t _H.
The delayed signal S _H delayed by only this amount is input to the OR gate 312. In response, the output signal of the OR gate 312 rises, and the RS flip-flop 313 is reset. That is, the output signal S of the RS flip-flop 313
_out is switched to low level, and the inverted output signal / S
_out is switched to high level.

The output signal S of the RS flip-flop 313
The falling edge of _out is detected by a falling edge detection circuit 302, and the detection signal is a delay signal S _L delayed by a time t _L by a delay circuit 301 to an OR gate 31.
1 is input. In response, the output signal of the OR gate 311 rises, and the RS flip-flop 313 is set. That is, the output signal S _out of the RS flip-flop 313 is switched to the high level, and the inverted output signal /
S _out is switched to low level.

As described above, the frequency multiplier shown in FIG. 2 generates an oscillation signal having a period (t _L + t _H ) as S _out or its inverted signal / S _out . In addition, the phases of these oscillation signals are corrected by the clock signal ck.
Note that the delay times t _L and t of the delay circuits 301 and 303 are
_{Since H} is set by the count value M of the counter 20a, the oscillation frequency of the frequency multiplier is controlled by the count value M of the counter 20a. When the mask signal mk is at the low level, the phase correction by the clock signal ck is not performed, the frequency multiplier oscillates at the frequency set by the count value M, and the signal _Sout and its inverted signal / _Sout are output.

FIG. 5 shows another example of the configuration of the frequency multiplier 30a constituting the digital PLL circuit shown in FIG. As shown in the figure, the frequency multiplier 30-2 of the present example has an OR gate 3 compared to the frequency multiplier 30-1 shown in FIG.
11 and 312 and the RS flip-flop 313 are replaced with NOR gates 315 and 316 and an inverter 3
17, 318 are used. The other parts are almost the same as the corresponding parts of the frequency multiplier 30-1 shown in FIG. 2, and therefore, in FIG. 5, the same circuit elements are denoted by the same reference numerals.

The NOR gates 315 and 316 each have 3
Input NOR gate. In the NOR gate 315,
The output signal S _L of the delay circuit 301, the detection signal of the rising edge detection circuit 308, and the output signal of the NOR gate 316 are input. The output signal of the NOR gate 315 is input to the falling edge detection circuit 304, and is output as a signal S _out via the inverter 317.
The output signal S of the delay circuit 303 is supplied to the NOR gate 316.
_H , reset signal reset and NOR gate 315
Is output. The output signal of the NOR gate 316 is input to the falling edge detection circuit 302, and is output as an inverted signal / S _out via the inverter 318.

In the initial state, the output terminal of the NOR gate 315 is held at a high level, and the output terminal of the NOR gate 316 is held at a low level. At this time, the output signal S _out of the frequency multiplier 30-2 is held at a low level, and the inverted output signal S / _out is held at a high level.

When the reset signal reset switches from a high level to a low level, the frequency multiplier 30-2 enters an operating state. First, the output signal of the AND gate 307 rises in response to the rising edge of the clock signal ck, the rising edge is detected by the rising edge detection circuit 308, and the detection signal is output to the NOR gate 315.
Is input to In response, the output signal S _O of the NOR gate 315 switches from high level to low level. Accordingly, the output signal / S _O of the NOR gate 316 switches from the low level to the high level.

The falling edge of the signal S _O is detected by the falling edge detection circuit 304. The signal S _H delayed by the time t _H by the detection signal delay circuit 303.
Is input to the NOR gate 316. Accordingly, the inverted signal of signal S _O , that is, the output signal of NOR gate 316 /
S _O switches from a high level to a low level. The falling edge of the inverted signal / S _o is detected by the falling edge detection circuit 302. The detection signal is supplied to the delay circuit 30
The delay signal S _L delayed by the time t _L by 1 is input to the NOR gate 315. In response, NOR gate 3
The output signal 15 switches from high level to low level.

As described above, the NOR gates 315, 3
The 16 output signals S _O and / S _O have a period (t _H +
t _L ). That is, the output signal S _out of the frequency multiplier shown in FIG.
_out is a clock signal having a period (t _H + t _L ). As described above, the frequency multiplier 30-2 of the present example is configured as shown in FIG.
The clock signal _Sout having the frequency set by the count value M from the counter 20a and its inverted signal / _Sout are generated in substantially the same manner as the frequency multiplier 30-1 shown in FIG. And when the mask signal mk is at a high level,
The phase of the signal S _out and its inverted signal / S _out are corrected by the clock signal ck.

FIG. 6 is a circuit diagram showing an example of the frequency divider 40a constituting the digital PLL circuit shown in FIG. As shown, the frequency divider 40a subtracts n-bit data input from the outside to set the frequency division ratio N (-1).
Subtractor 401, a counter 402 for counting an input clock signal, an output of the subtractor 401 and a counter 4
It is composed of a comparison circuit for comparing with the count value of 02, a falling edge detection circuit 409, a frequency divider 407, RS flip-flop circuits 410, 412, 414 and other gate circuits.

The subtractor 401 subtracts 1 from the n-bit data indicating the frequency division ratio N, and outputs n-bit data. The counter counts up according to the input clock signal and outputs an n-bit count value. The comparison circuit includes n exclusive NOR gates EOR.
, EORn-1 and an n-input AND gate 403. When the output data of the subtractor 401 matches the count value of the counter 402,
The output signal mk 'of the AND gate 403 becomes high level, otherwise, the output signal m of the AND gate 403 becomes
k 'goes low.

The output signal mk 'of the AND gate 403 is A
The signals are input to the set terminal S of the ND gate 404 and the RS flip-flop 410, respectively. The output signal of the OR gate 411 is input to the reset terminal R of the RS flip-flop 410. The signal mask output from the RS flip-flop 410 is input to the AND gate 408 together with the output signal of the AND gate 415. AND
The output signal out ′ of the gate 408 is
6, are input to the AND gate 405 and the falling edge detection circuit 409, respectively.

The frequency divider 407 divides the output signal of the inverter 416 by two, inputs the obtained frequency-divided signal wd to the AND gate 405, and further converts the frequency-divided signal inverted by the inverter 406 into the AND gate 404. Is input to
The falling edge detection circuit 409 is connected to the AND gate 40
The falling edge of the output signal out ′ is detected and the detection signal is input to the AND gate 405 and the OR gate 411, respectively.

FIG. 7 is a waveform chart showing the operation of frequency divider 40a shown in FIG. Hereinafter, the operation of the frequency divider 40a will be described with reference to FIGS. When the reset signal reset is at a high level, the AND gate 415
Is held at a low level, no clock signal is input to the counter 402, and the counter 402 stops. When the reset signal reset switches from the high level to the low level, the clock signal ck
, The counter 402 counts the clock signal ck, and the count value gradually increases.

The count value of the counter 402 is calculated by the subtractor 40.
1, that is, at the (N−1) th pulse of the clock signal ck, as shown in FIG.
A pulse signal mk ′ having a width corresponding to one cycle of the clock signal ck is output from the D gate 403. RS accordingly
The flip-flop 410 is set and its output signal m
Ask goes high. The AND operation of the signal mask and the AND gate 415 is performed by the AND gate 408.
t ′ is output. That is, as shown in FIG. 7, the output signal out ′ of the AND gate 415 is the N
It is almost in phase with the first pulse.

The falling edge of the signal out 'is detected by the falling edge detection circuit 409, and the detection signal is output to the AND gate 411. AND gate 411
, The RS flip-flop 410 is reset, and the output signal mask changes to low level.

In the initial state, the output signal wd of the frequency divider 407 is held at a high level. At this time, AND
The gate 405 outputs a signal out that is substantially synchronized with the signal out ′. The out signal is output from the frequency divider 40a.
, Ie, a divided signal obtained by dividing the input clock signal ck by N. On the other hand, an inverted signal of the output signal out 'of the AND gate 408 is input to the frequency divider 407, and the frequency divider 407 divides the frequency by 2 to obtain a frequency divided signal wd. Since the output signal of the inverter 416, that is, the inverted signal of the signal out 'is input to the frequency divider 407, the signal ou
Each time t 'is input, the output of the frequency divider 407 is inverted. For this reason, the frequency divider 4 according to the first signal out '
07 switches from the high level to the low level.

The counter 402 is reset by the output signal of the OR gate 411 and restarts the counter. When the count value reaches N-1, the output signal mk 'of the AND gate 403 rises again. At this time, the frequency divider 40
7 is at the low level, the output signal of the inverter 406 is at the high level, and the AND gate 4
03 is the same as the mask signal mk in phase with the output signal mk ′.
Output from the ND gate 404.

The RS flip-flop 410 is set by the output signal mk 'of the AND gate 403, and the output signal mask goes high. AND accordingly
The gate 408 outputs a second pulse signal out ′. At this time, since the output signal wd of the frequency divider 407 is at the low level, the output signal ou of the AND gate 405 is output.
t is held at a low level. The frequency divider 407 operates according to the inverted signal of the signal out ′, and the output signal wd switches from the low level to the high level.

The falling edge of the output out ′ of the AND gate 408 is detected by the falling edge detection circuit 409, and the detection signal is input to the OR gate 411. The counters 401 are both reset. After being reset, the counter 401 restarts the counting operation in response to the input of the next clock signal ck.

As described above, the frequency divider 40a shown in FIG.
As a result, the clock signal ck is frequency-divided at the frequency division ratio N set externally. The frequency-divided signal out and the mask signal mk are output alternately every n cycles of the clock signal ck. The frequency-divided signal out is input to the phase comparator 10a as the frequency-divided signal DCK shown in FIG. 1, and the mask signal mk is input to the frequency multiplier 30a.

The reference clock R is output by the phase comparator 10a.
A frequency-divided clock signal ck0 obtained by dividing FCK and a frequency divider 40
The phase with the frequency-divided signal DCK from a is compared, and an up signal S _up or a down signal S _dw is output according to the result of the comparison. In the frequency multiplier 30a, when the mask signal mk is at a high level, the input clock signal ck
As a result, the phase of the frequency-multiplied clock signal PLCK generated by the frequency multiplier 30a is corrected.

FIG. 8 is a waveform diagram showing the entire operation of the digital PLL circuit shown in FIG. FIG. 8 shows the operation when the frequency division ratio R of the frequency divider 50 is set to 2. In the drawing, (mk: L) indicates a signal input to the input terminal mk of the delay circuit 301, and (mk: H) indicates a signal input to the input terminal mk of the delay circuit 303. As shown in the figure, the phase of the frequency-divided signal obtained by dividing the reference clock RFCK by R (here, frequency-divided by 2) is compared with the phase of the frequency-divided signal DCK from the frequency divider 40a, and according to the phase difference error between these signals. Signal S by the phase comparator 10a.
Either the _up signal or the down signal S _dw is output.

As described above, the divided clock signal PLCK from the frequency multiplier 30a is divided by N by the divider 40a, and the divided signal DCK and the mask signal mk are output alternately. In response, the phase comparison and the phase correction are performed alternately as shown in FIG. For example, the reference clock RFC
In the first cycle of K, the phase comparator 10a compares the phase of the frequency-divided clock signal from the frequency divider 50 with the phase of the frequency-divided signal DCK from the frequency divider 40a, and outputs an up signal in accordance with the phase difference between these signals. The S _up or down signal S _dw is output, and the count value M of the counter 20a is controlled accordingly. The frequency of the output signal PLCK of the frequency multiplier 30a is controlled according to the count value M.

In the next cycle of the reference clock RFCK, phase correction is performed. At this time, since the high-level mask signal mk is output from the frequency divider 40a, the clock signal ck is input to the rising edge detection circuit 308 in the frequency multiplier shown in FIG. 2, and the rising edge is detected. R according to the rising edge
The S flip-flop 313 is set. That is, the phase of the multiplied clock signal PLCK generated by the frequency multiplier is adjusted to the clock signal ck. Therefore, the phase jitter between the multiplied clock signal PLCK and the reference clock RFCK is reduced, and the period jitter is also reduced.

Before performing phase correction, delay circuits 301 and 3
03 are sequentially reset. For example, in the frequency multiplier 30-1 shown in FIG.
Is input, the output of the AND gate 309 becomes high level while the clock signal ck is low level, and the delay circuit 301 is reset. When the clock signal ck switches to low level, the output signal of the AND gate 309 becomes low level, and the reset of the delay circuit 301 is released. On the other hand, the delay circuit 303 is reset after the inverted output signal / S _out of the RS flip-flop 313 switches from low level to high level, and is released when the clock signal ck becomes high level. In this case, assuming that the cycle of the multiplied clock signal PLCK is T and the minimum step amount of the cycle of the clock signal PLCK generated by the frequency multiplier 30a with respect to a change of 1 bit of the count value M of the counter 20a is Δd, ck
Is obtained by the following equation.

[0059]

Δt = ± N · Δd (1)

The cycle t 'immediately before performing the phase correction is expressed by the following equation.

[0061]

Δt ′ = T / N ± (2N−1) · Δd (2)

Therefore, when .DELTA.d and the frequency division ratio N of the frequency divider 40a are set to appropriate values, the phase jitter with the clock signal ck and the period jitter of the multiplied clock signal PLCK can be reduced.

As described above, according to the present embodiment, the frequency of the reference clock RFCK is divided by the frequency divider 50,
The frequency-divided signal ck0 is input to the phase comparator 10a, and the inverted signal ck is input to the frequency multiplier 30a. The phase comparator 10a receives the signal ck0 and the frequency-divided signal DC from the frequency divider 40a.
K, and outputs either the up signal S _up or the down signal S _dw according to the phase difference between these signals,
The counter 20a outputs a count value M according to the phase difference signal, the frequency multiplier 30a outputs a multiplied clock signal PLCK at a frequency set by the count value M, and further receives a mask signal mk from the frequency divider 40a. Then, the phase of the multiplied clock signal PLCK is corrected by the clock signal ck. The frequency divider 40a outputs the multiplied clock signal PLCK
Is divided by a preset dividing ratio N, and a mask signal mk is generated at a predetermined ratio with respect to the divided signal DCK. As a result, the phase error of the multiplied clock signal PLCK can be quickly corrected, the phase and frequency are stabilized, the phase jitter with the reference clock can be reduced, and the period jitter can be suppressed.

Second Embodiment FIG. 9 is a circuit diagram showing a second embodiment of the digital PLL circuit according to the present invention. As shown, the digital PLL circuit according to the present embodiment has a phase comparator 1 similar to the digital PLL circuit according to the first embodiment shown in FIG.
0a, counter 20a, frequency multiplier 30b, frequency divider 4
0a and the frequency divider 50. However,
In the digital PLL circuit of the present embodiment, the frequency multiplier 30b does not perform the phase correction when there is no phase difference between the signals input to the phase comparator 10a, and the frequency set according to the count value M from the counter 20a. Generates a multiplied clock signal PLCK.

The configuration and operation of each of the phase comparator 10a, counter 20a, frequency divider 40a and frequency divider 50 are substantially the same as those of the respective partial circuits constituting the digital PLL circuit of the first embodiment shown in FIG. Since they are the same,
In FIG. 9, the same components of the circuit are denoted by the same symbols. Hereinafter, the digital PLL circuit of the present embodiment will be described focusing on the configuration and operation of the frequency multiplier 30b in the digital PLL circuit of the present embodiment.

FIG. 10 shows an example of the configuration of the frequency multiplier 30b constituting the digital PLL circuit of FIG.
As shown, the frequency multiplier 30-3 of the present example has substantially the same configuration as the frequency multiplier 30-1 shown in FIG. However, the frequency multiplier 30-3 of the present example is different from the phase comparator 10-3.
In response to the up signal S _up and the down signal S _dw from a, phase correction is performed on these signals, the multiplied clock signal S _out (PLCK) generated in response to the clock signal ck, and its inverted signal / S _out . .

As shown, both the up signal S _up and the down signal S _dw from the phase comparator 10a are input to the OR gate 320. The output signal of the OR gate 320 is input to a latch circuit (LT) 321, the signal held by the latch circuit 321 is input to the latch circuit 322, and the output signal of the latch circuit 322 is input to the AND gate 3.
07a. Here, the AND gate 307a
Is a 3-input AND gate. AND gate 307
The output signal of the inverter 306, that is, the in-phase signal of the clock signal ck, the mask signal mk, and the output signal of the latch circuit 322 are input to a.

The latch circuit 321 holds an output signal of the inverter 323, that is, an input signal according to an inverted signal of the clock signal ck. For example, when the clock signal ck is at the low level, that is, when the output signal of the inverter 323 is at the high level, the latch circuit 321 outputs the input signal to the output terminal, and when the clock signal ck is at the high level,
That is, when the output signal of the inverter 323 is at a low level, the latch circuit 321 holds the output signal. The latch circuit 322 holds an input signal according to the clock signal ck. When the clock signal ck is at a high level, the latch circuit 322 outputs an input signal to an output terminal. When the clock signal ck is at a low level, the latch circuit 321 holds the output signal.

In the frequency multiplier 30-3 shown in FIG. 10, the logical sum of the up signal S _up and the down signal S _dw is O
Output from the R gate 320. At the rising edge of the clock signal ck, the output signal of the OR gate 320 is sampled and held until the next rising edge.
Therefore, when there is a phase difference between the signals input to the phase comparator 10a, either the up signal S _up signal or the down signal S _dw is held at a high level. At this time,
The output signal of the R gate 320 goes high. At the rising edge of the clock signal ck, the OR gate 3
20 output signals are sampled, and the output signal of the latch circuit 322 is at a high level.

On the other hand, when there is no phase difference between the input signals of the phase comparator 10a, the up signal S _up and the down signal S _dw
Are both held at the low level. At this time, the output signal of the OR gate 320 also becomes low level, so that the output signal of the latch circuit 322 is held at low level.

When the output signal of latch circuit 322 is held at a low level, the output signal of AND gate 307a is also held at a low level regardless of mask signal mk or clock signal ck, as shown in FIG. . That is, at this time, the phase of the multiplied clock signal S _out (PLCK) generated by the frequency multiplier 30-3 is not corrected, and the frequency of the multiplied clock signal is determined only by the count value M input from the counter 20a. Controlled.

In the frequency multiplier 30-3, the multiplied clock signal PLCK is output only when either the up signal S _up or the down signal S _dw is input from the phase comparator 10a.
Is performed. At other times, the frequency and phase of the multiplied clock signal PLCK are controlled by the count value M from the counter 20a.

FIG. 11 shows another configuration example 30-4 of the frequency multiplier constituting the digital PLL circuit of FIG. As shown, the frequency multiplier 30-4 is configured as shown in FIG.
The OR gate 31 is different from the frequency multiplier 30-3 shown in FIG.
1, 312 and RS flip-flop 313, OR gates 315, 316 and inverter 31
7,318. The other parts have the same configuration. The frequency multiplier 30-4 shown in FIG.
Although the number of elements constituting the circuit is smaller than that of the frequency multiplier 30-3 indicated by 0, the same function can be achieved.

FIG. 12 is a waveform diagram during the operation of the digital PLL circuit shown in FIG. Hereinafter, the operation of the digital PLL circuit according to the present embodiment will be described with reference to FIGS.

In the digital PLL circuit of FIG. 9, the frequency divider 40a divides the frequency of the multiplied clock signal PLCK from the frequency multiplier 30b by N, and alternately outputs the frequency-divided signal DCK and the mask signal mk. In response, FIG.
As shown in (2), the phase comparison and the phase correction are performed alternately. For example, in the first cycle of the reference clock RFCK, the phase comparator 10a compares the phase of the frequency-divided clock signal of the frequency divider 50 with the phase of the frequency-divided signal DCK from the frequency divider 40a. Either the up signal S _up or the down signal S _dw is output in accordance with the phase difference of

In the counter 20a, the phase comparator 10a
Count-up or count-down according to the up signal S _up or the down signal S _dw from the controller, and the value of the count value M is set. In the frequency multiplier 30b, a multiplied clock signal P according to the count value M from the counter 20a.
The frequency of LCK is controlled. Further, the phase comparator 10a
When either the up signal S _up or the down signal S _dw is output from the clock signal CK and the mask signal mk from the frequency divider 40a is at a high level, the phase of the multiplied clock signal PLCK is held by the clock signal ck. When there is no phase difference between the input signals of the phase comparator 10a and neither the up signal S _up nor the down signal S _dw is output, the frequency multiplier 3
0b, no phase correction is performed and the multiplied clock signal P
The frequency and phase of LCK are controlled by the count value M from the counter 20a.

As shown in FIG. 12, the reference clock RFC
Phase correction is performed in the second cycle of K. And
In the third cycle of the reference clock RFCK, the phase of the input signal is compared by the phase comparator 10a. If it is determined that there is no phase difference between the input signals, neither the up signal S _up nor the down signal S _dw is output. Therefore, no phase correction is performed in the next cycle of the reference clock RFCK. Thus, the digital P of the present embodiment is
In the LL circuit, when there is no phase difference between signals input to the phase comparator 10a, the phase correction in the frequency multiplier 30b is not performed, and the stop of the operation of the frequency multiplier 30b due to the phase correction is avoided, so that the LL circuit is more stable. Multiplied clock signal P
LCK can be generated.

As described above, according to the present embodiment, the frequency multiplier 30b performs the phase correction according to the comparison result of the phase comparator 10a, and when the phase comparator 10a has a phase difference between the input signals, , Frequency multiplier 30
b performs phase correction. Conversely, when there is no phase difference between the input signals of the phase comparator 10a, the frequency multiplier 30b stops the phase correction. Therefore, only when there is a phase error, the phase is corrected by the frequency multiplier 30b. At other times, the frequency multiplier 30b controls the frequency and phase of the multiplied clock signal PLCK according to the count value M from the counter 20a. In addition, it is possible to avoid stopping the operation of the frequency multiplier due to the phase correction, and to generate a stable multiplied clock signal PLCK.

[0079]

As described above, according to the digital PLL circuit of the present invention, the phase and frequency of the generated multiplied clock signal are stabilized, and not only the phase jitter with the reference clock but also the period jitter of the multiplied clock signal are obtained. Can be prevented from increasing. Further, according to the present invention, there is an advantage that a circuit can be constituted by a general logic circuit, and a stable multiplied clock signal can be generated without requiring a complicated special circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a digital PLL circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a frequency multiplier included in the digital PLL circuit of FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a delay circuit constituting the frequency multiplier.

FIG. 4 is a waveform chart showing an operation of the frequency multiplier.

FIG. 5 is a circuit diagram showing another configuration example of the frequency multiplier constituting the digital PLL circuit of FIG. 1;

FIG. 6 is a circuit diagram showing a configuration of a frequency divider constituting the digital PLL circuit of FIG. 1;

FIG. 7 is a waveform chart showing an operation of the frequency divider of FIG.

FIG. 8 is a waveform chart showing an overall operation of the digital PLL circuit shown in FIG.

FIG. 9 is a circuit diagram showing a second embodiment of a digital PLL circuit according to the present invention.

FIG. 10 is a circuit diagram showing a configuration example of a frequency multiplier constituting the digital PLL circuit shown in FIG. 9;

11 is a circuit diagram illustrating another configuration example of the frequency multiplier included in the digital PLL circuit illustrated in FIG. 9;

FIG. 12 is a waveform chart showing an operation of the digital PLL circuit shown in FIG.

FIG. 13 is a circuit diagram showing a configuration of a conventional digital PLL circuit.

FIG. 14 is a waveform chart showing an operation of a conventional digital PLL circuit.

[Explanation of symbols]

10, 10a ... phase comparator, 20, 20a ... counter,
30, 30a, 30b ... frequency multipliers, 40, 40a,
50: frequency divider, 301, 303 ... delay circuit, 302, 3
04 falling edge detection circuit, 308 rising edge detection circuit, 313 RS flip-flop, 40
DESCRIPTION OF SYMBOLS 1 ... Subtractor, 402 ... Counter, 407 ... Divider (divide | divide by 2), 409 ... Falling edge detection circuit, 410 ... R
S flip-flop.

Claims (10)

[Claims] A phase comparison circuit that compares a phase of a reference signal with a signal to be compared and outputs a phase difference signal in accordance with a phase difference between the reference signal and the signal to be compared; A counter that outputs a count value in accordance with the phase difference between the reference signal and the comparison target signal, and a clock signal generated at a frequency set in accordance with the count value, and a correction control signal from the outside. Is entered,
An oscillation circuit that corrects the phase of the clock signal based on the reference signal; and divides the clock signal by a predetermined division ratio, and supplies the frequency-divided signal to the phase comparison circuit as the comparison target signal. A frequency divider circuit for generating the correction control signal at a predetermined ratio with respect to the frequency-divided signal. 2. The digital P circuit according to claim 1, wherein said frequency dividing circuit alternately outputs said frequency dividing signal and said correction control signal.
LL circuit. 3. The digital PLL circuit according to claim 1, wherein said oscillation circuit has a loop circuit including a delay circuit whose delay time is controlled by said count value from said counter. 4. The oscillating circuit is set by a first input signal, a first output signal is set to a high level, a second output signal is set to a low level, and reset by a second input signal. When the first output signal is at a low level,
A flip-flop circuit whose output signal is set to a high level, a first edge detection circuit that detects a falling edge of the first output signal, and outputs a first pulse signal according to a detection result; A second edge detection circuit that detects a falling edge of the second output signal and outputs a second pulse signal according to a detection result; and the first pulse signal is set according to the count value. A first delay circuit that outputs a first delay signal by delaying the second delay signal by a predetermined delay time, and a second delay signal that delays the second pulse signal by a delay time set according to the count value. A second delay circuit for outputting, a first gate circuit for inputting the logical sum of the first delay signal and the reference signal as the first input signal to the flip-flop, and a second delay circuit Signal above As second input signal, a digital PLL circuit according to claim 1, further comprising a second gate circuit for inputting to the flip-flop. 5. When the correction control signal is input, the first delay signal from the first delay circuit is held at a low level, and the flip-flop is reset in response to the low delay signal. Output signal is low level, the second
Are held at a high level, and the flip-flop is set according to a rising edge of the reference signal, and the first output signal is set to a high level and the second output signal is set to a low level. 5. The digital PLL circuit according to claim 4, wherein: 6. A phase comparison circuit for comparing the phases of a reference signal and a signal to be compared, and outputting a phase difference signal in accordance with the phase difference between the reference signal and the signal to be compared; A counter that outputs a count value corresponding to the phase difference between the reference signal and the comparison target signal, and a clock signal having a frequency set according to the count value, and performs correction control from outside. Signal is input,
An oscillation circuit that corrects the phase of the clock signal based on the reference signal when the phase of the reference signal and the signal to be compared that are input to the phase comparison circuit are not the same phase; A digital PLL circuit having a frequency dividing circuit that divides the frequency by a frequency ratio, supplies the frequency-divided signal as the signal to be compared to the phase comparison circuit, and generates the correction control signal at a predetermined ratio with respect to the frequency-divided signal. . 7. The digital P circuit according to claim 6, wherein said frequency dividing circuit alternately outputs said frequency dividing signal and said correction control signal.
LL circuit. 8. The digital PLL circuit according to claim 6, wherein said oscillation circuit has a loop circuit including a delay circuit whose delay time is controlled by said count value from said counter. 9. The oscillating circuit is set by a first input signal, a first output signal is set to a high level, a second output signal is set to a low level, and reset by a second input signal. When the first output signal is at a low level,
A flip-flop circuit whose output signal is set to a high level, a first edge detection circuit that detects a falling edge of the first output signal, and outputs a first pulse signal according to a detection result; A second edge detection circuit that detects a falling edge of the second output signal and outputs a second pulse signal according to a detection result; and the first pulse signal is set according to the count value. A first delay circuit that outputs a first delay signal by delaying the second delay signal by a predetermined delay time, and a second delay signal that delays the second pulse signal by a delay time set according to the count value. A second delay circuit for outputting, a signal holding circuit for holding the phase difference signal from the phase comparison circuit in accordance with the timing of the reference signal, a holding signal of the signal holding circuit, the reference signal, and the A logic gate circuit that outputs a logical product of a positive control signal; and a first gate that inputs a logical sum of the first delay signal and an output signal of the logic gate as the first input signal to the flip-flop. 7. The digital PLL circuit according to claim 6, further comprising: a circuit; and a second gate circuit that inputs the second delay signal as the second input signal to the flip-flop. 10. When the correction control signal is input, the first delay signal from the first delay circuit is held at a low level, and the flip-flop is reset in response to the low delay signal. Is held at a low level and the second output signal is held at a high level. When the holding signal of the signal holding circuit is at a high level, the flip-flop is set according to a rising edge of the reference signal. 10. The digital PLL circuit according to claim 9, wherein the first output signal is set to a high level and the second output signal is set to a low level.