JP2000151380A - Semiconductor integrated logic circuit provided with mode switch means with response function for power interrupt and power supply method for semiconductor integrated logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restore all logic circuits to a state where power can completely be supplied and to avoid malfunctions by inputting the signal of effect for indicating the supply of power and sequentially supplying power to plural logic circuits in terms of a chain at switching of a sleep mode to an active mode. SOLUTION: Mode switch means PSW1-PSW6 are installed in circuit groups LGC1A-LGC6A, incorporating NAND gates 1a and 2a, INV circuits 3c and 3a-6a and an arbitrary transistor logic circuit FNC1. When sleep mode switch signals SIN are inputted, the mode switching means PSW1-PSW6 supply/ interrupt power to the respective circuits. The supply/interrupt of power to the respective circuits in a semiconductor integrated logic circuit is executed chain-like in the order LGC2A → LGC1A → LGC3A → LGC4A → LGC5A →LGC6A, while the sleeve mode switch signal SIN flows into the semiconductor integrated logic circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated logic circuit provided with a mode switching means having a power cutoff function.
The present invention relates to a semiconductor integrated logic circuit provided with means for observing a mode transition between the active mode and the sleep mode when the sleep mode is intermittently executed, and particularly for preventing a malfunction during the mode transition from the sleep mode to the active mode mode.

[0002]

2. Description of the Related Art Conventionally, a semiconductor integrated logic circuit having a mode switching means with a power cutoff function has been used in a semiconductor integrated logic circuit in order to achieve both high speed in an active mode and low power consumption in a sleep mode. I was

For example, Japanese Patent Application Laid-Open No. 06-29834 discloses that a semiconductor integrated logic circuit is constituted by low-threshold transistors so that, when active under a low power supply voltage, the logic circuit operates at a high speed and a high-threshold transistor is used. Method for reducing power consumption by cutting off the high threshold transistor in sleep mode to cut off power supply and also cut off sub-threshold leakage current (standby current) during sleep Is described.

FIG. 20 is a system diagram of a semiconductor integrated logic circuit 100 including a mode switching means with a power cutoff function according to the prior art. The semiconductor integrated logic circuit 100 includes NAND logic circuits NAND1 and NAND2 and an inverter circuit IN
V1 to INV4 and NAND logic circuits NAND1, NAND
2. It is composed of inverter circuits INV1 to INV3, control transistors TSP1 to TSP6 for supplying and cutting off power to the transistor logic circuit FNC1, and an arbitrary transistor logic circuit FNC1.

[0005] NAND7 has data signals IN1, IN
2 is input to NAND2, and data signals IN3 and IN
4 is input. Also, the control transistors TSP2, TSP
The sleep mode switching signal SL is input to SP3, and the control transistors TSN1, TSN4, TSN5, TSN6
Is supplied with a sleep mode switching signal SLB.

In FIG. 20, a p-channel type MOS transistor and an n-channel type MOS transistor having a high threshold value are indicated by a thick gate electrode output, and a low threshold value is indicated by a thin gate electrode output. The power supply on the high potential side is indicated by VDD, and the power supply on the low potential side is indicated by ground GND.

A conventional semiconductor integrated logic circuit 1 will be described below.
Each circuit constituting 00 will be described.

First, the NAND logic circuit NAND1 is composed of CMOS transistors having a low threshold value. The p-channel MOS transistors TDP1 and TDP2 connected in parallel, and these p-channel MOS transistors connected in parallel are connected in series. It comprises an n-channel MOS transistor TDN1 and a transistor TDN2. Transistor TDP1 and transistor T
The gate electrodes of DN1 are commonly connected to each other to generate a data signal IN1.
And the gate electrodes of the transistor TDP2 and the transistor TDN2 are connected in common, and the data signal I
N2 is input. Further, the commonly connected transistors TDP1, TDP2, and TDN
One drain electrode becomes an output signal terminal of the NAND logic circuit NAND1. Further, the commonly connected transistors T
The source electrodes of the transistor DP1 and the transistor TDP2 are a high-potential power supply terminal at one end of the NAND logic circuit NAND1, and the source electrodes of the transistor TDN2 are a NAND logic circuit NA.
The other end of ND1 is a low-potential-side power supply terminal.

The NAND logic circuit NAND1 receiving the two data signals IN1 and IN2 has a low threshold CMO.
Since it is constituted by the S transistor, high-speed operation can be performed in the active mode.

In the NAND logic circuit NAND1, a high-potential power supply terminal at one end is connected to the power supply VDD, and a low-potential power supply terminal at the other end is connected to a control transistor TSN1 via a control transistor TSN1.
ND, and these circuits constitute a NAND logic circuit LGC1 having a power cutoff function.

The control transistor TSN1 for performing conduction and cutoff control in response to the sleep mode switching inversion signal SLB is formed of a high threshold n-channel transistor.
B changes from High level to Low level. In the sleep mode (SLB = 0), the transistor TSN1 is cut off to cut off the power supply to the NAND logic circuit NAND1 and also cut off the sub-threshold leakage current. Sleep mode switching inversion signal SL
B changes from a low level to a high level. In the active mode (SLB = 1), the transistor TSN
1 turns on to supply power to the NAND logic circuit NAND1.

The NAND logic circuit NAND2 is composed of low threshold CMOS transistors like the NAND logic circuit NAND1, has the same circuit connection configuration, and uses the data signals IN3 and IN4 as input signals.

Here, since the NAND logic circuit NAND2 is formed of a low threshold CMOS transistor, it can operate at a high speed in the active mode.

The NAND logic circuit NAND2 has a low-potential power supply terminal at one end connected to GND and a high-potential power supply terminal at the other end connected to a power supply VDD via a control transistor TSP2. Constitutes a NAND logic circuit LGC2 having a power cutoff function.

Here, since the control transistor TSP2, which performs conduction and cutoff control in response to the sleep mode switching signal SL, is formed of a p-channel transistor having a high threshold value, the sleep mode switching signal SL changes from the low level to the low level. It changes to High level. In the sleep mode (SL = 1), the transistor TSP2 is cut off to cut off the power supply to the NAND logic circuit NAND2 and also cut off the sub-threshold leakage current. When the sleep mode switching signal SL is High
The level changes from the level to the low level. In the active mode (SL = 0), the transistor TSP2 is turned on to supply power to the NAND logic circuit NAND2.

Next, the inverter circuit INV1 is composed of a low threshold CMOS transistor, and is composed of a p-channel MOS transistor TIP1 and an n-channel MOS transistor TIN1 connected in series. The gate electrodes are connected in common, and the preceding NAND logic circuit NAN
The output signal of D1 is input, and the drain electrodes of the commonly connected transistor TIP1 and transistor TIN1 serve as the output signal terminal of the inverter circuit INV1. Further, the source electrode of the transistor TIP1 is a high potential side power supply terminal at one end of the inverter circuit INV1, and the source electrode of the transistor TIN1 is the inverter circuit INV1.
It becomes the low potential side power supply terminal at the other end of V1.

Here, since the inverter circuit INV1 is composed of a low threshold CMOS transistor, it can operate at a high speed in the active mode.

The inverter circuit INV2 is composed of low-threshold CMOS transistors similarly to the inverter circuit INV1 and has the same circuit connection configuration, and uses the output signal of the preceding NAND logic circuit NAND2 as an input signal. .

The inverter circuit INV2 has a low threshold CM.
Since it is constituted by the OS transistor, high-speed operation can be performed in the active mode.

Here, the inverter circuits INV1 and INV2
The low-potential-side power supply terminal at one end of each is connected to GND,
The other high-potential power supply terminal at the other end is connected to a control transistor TS.
The power supply VDD is commonly connected via P3, and these circuits constitute a two-parallel inverter circuit LGC3 having a power cutoff function.

Here, since the control transistor TSP3, which performs conduction and cutoff control in response to the sleep mode switching signal SL, is constituted by a p-channel type transistor having a high threshold value, the transistor TSP3 in the sleep mode (SL = 1) The TSP3 is cut off to cut off the supply of power to the inverter circuits INV1 and INV2 and also cut off the sub-threshold leakage current. In the active mode (SL = 0), the transistor TSP3 turns on to connect the inverter circuit INV1 with the inverter circuit INV1. INV
2 can be powered.

The transistor logic circuit FNC1 is composed of a low threshold CMOS transistor, receives each output signal of the preceding inverter circuits INV1 and INV2, outputs two signals, and outputs a high-potential power supply terminal and a low-potential side. It has one set of power supply terminals.

Here, the transistor logic circuit FNC1 is
Since the low-threshold CMOS transistor is used, high-speed operation can be performed in the active mode.

The transistor logic circuit FNC1 has a high-potential power supply terminal at one end connected to the power supply VDD, and a low-potential power supply terminal at the other end connected to the ground GND via the control transistor TSN4. Constitutes a transistor logic circuit LGC4 having a power cutoff function.

Here, the sleep mode switching inversion signal SLB
, The control transistor TSN4, which performs the conduction and cutoff control in response to the sleep mode (SLB), is composed of a high threshold n-channel transistor.
= 0), the transistor TSN4 is cut off, so that the supply of power to the transistor logic circuit FNC1 can be cut off and the sub-threshold leakage current can also be cut off. In the active mode (SLB = 1), the transistor TSN4 turns on. Transistor logic circuit FN
Power can be supplied to C1.

The inverter circuit INV3 has a low threshold CM.
OS transistors, and p connected in series
The transistor TIP2 includes a channel type MOS transistor TIP2 and an n-channel type MOS transistor TIN2. The gate electrodes of the transistor TIP2 and the transistor TIN2 are connected in common, and the transistor logic circuit FNC of the preceding stage is formed.
1 and the drain electrode of the commonly connected transistor TIP2 and the transistor TIN2 becomes the output signal terminal of the inverter circuit INV3 to output the data signal OUT1, and the source electrode of the transistor TIP2 is One end of the inverter circuit INV3 is a high-potential power supply terminal, and the source electrode of the transistor TIN2 is the other end of the inverter circuit INV3, a low-potential power supply terminal.

Here, since the inverter circuit INV3 is composed of a low threshold CMOS transistor, it can operate at high speed in the active mode.

The high-potential power supply terminal at one end of the inverter circuit INV3 is connected to the power supply VDD, and the low-potential power supply terminal at the other end is connected to the ground GND via the control transistor TSN5. The circuit constitutes an inverter circuit LGC5 having a power cutoff function.

Here, the sleep mode switching inversion signal SLB
, The control transistor TSP5 that performs conduction and cutoff control in response to the sleep mode (SLB) is constituted by a high threshold n-channel transistor.
= 0), the control transistor TSP5 is cut off to cut off the supply of power to the inverter circuit INV3 and also cut off the sub-threshold leakage current. In the active mode (SLB = 1), the transistor TSP5 turns on. Power can be supplied to the inverter circuit INV3.

The inverter circuit INV4 is formed of a low threshold CMOS transistor similarly to the inverter circuit INV3, and has the same circuit connection configuration.
The other output signal of the preceding transistor logic circuit FNC1 is used as an input signal.

The inverter circuit INV4 has a low threshold CM.
Since it is constituted by the OS transistor, high-speed operation can be performed in the active mode.

Here, the high-potential power supply terminal at one end of the inverter circuit INV4 is connected to the power supply VDD, and the low-potential power supply terminal at the other end is connected to the G terminal via the control transistor TSN6.
ND, and these circuits constitute an inverter circuit LGC6 having a power cutoff function.

Here, the sleep mode switching inversion signal SLB
The control transistor TSP6, which conducts the conduction and cutoff in response to the low-level control, is constituted by an n-channel transistor having a high threshold value.
= 0), the transistor TSP6 is cut off to cut off the supply of power to the inverter circuit INV4 and also to cut off the subthreshold leakage current. In the active mode (SLB = 1), the transistor TSP6 turns on and the inverter Power can be supplied to the circuit INV4.

[0034]

SUMMARY OF THE INVENTION The above-mentioned JP-A-6-2
No. 9834 discloses that a semiconductor integrated logic circuit is constituted by low-threshold transistors so that a logic circuit operates at a high speed in an active mode even under a low power supply voltage, and a power supply is supplied via a high-threshold transistor. By supplying the power, the high-threshold transistor is cut off in the sleep mode to cut off the power supply, and also cuts off the sub-threshold leakage current to reduce the power consumption. However, when the sleep mode operation is executed intermittently, since there is no means for observing the mode transition between the active mode and the sleep mode, the power is shut off particularly at the time of the mode transition from the sleep mode to the active mode. A problem that a malfunction occurs because all the transistor logic circuits provided with the function-equipped mode switching means start the operation as the active mode while not completely returning to the state where the power can be completely supplied. was there.

The means for controlling the mode transition between the active mode and the sleep mode included in the prior art semiconductor integrated logic circuit 100 shown in FIG. 20 is a sleep mode switching signal SL or a sleep mode switching inversion signal SLB.
And a plurality of transistor logic circuits LGC1 to LGG having a power cutoff function.
Control transistors TSN1, TSP2, TSP3, TSN4, and TSN5 as mode switching means provided in C6
, The sleep mode switching signal SL or the sleep mode switching inverted signal SLB must be individually supplied.

In the conventional example shown in FIG. 20, the semiconductor integrated logic circuit 100 composed of six transistor logic circuits LGC1 to LGC6 having a power cutoff function is shown. However, in a more practical semiconductor integrated logic circuit, Since a large number of transistor logic circuits with a power cutoff function are used, the number of sleep mode switching signals SL or sleep mode switching inversion signals SLB to be individually supplied also increases.

As a means for supplying a large number of sleep mode switching signals SL or inverted sleep mode switching signals SLB, a method in which signals are propagated and supplied in a branch shape via a plurality of buffer circuits is conceivable.

However, the sleep mode switching signal S
L or the sleep mode switching inversion signal SLB is the control transistor TSN1, TSP2, TSP3, TSN at the terminal.
4, the propagation time required to reach TSN5 is naturally different due to factors such as the driving capability and number of intervening buffer circuits, and the delay due to the load capacitance parasitic on the signal wiring. .

Further, the control transistors TSN1, TSN
P2, TSP3, TSN4 and TSN5 have different supply capacities of current to be supplied as mode switching means, and NAND logic circuits NAND1 and N to receive current supply.
Since the currents consumed by AND2, inverter circuits INV1 to INV4, and transistor logic circuit FNC1 also differ from each other, the state transits to the cutoff state or the conduction state in response to sleep mode switching signal SL or sleep mode switching inversion signal SLB. Therefore, there is a natural difference in the reaction time.

As a result of taking all of these factors into account, the prior art shows that all the transistor logic circuits having the mode switching means with the power cutoff function completely turn off the power at the time of the mode transition from the sleep mode to the active mode. The operation in the active mode is started while the state has not been completely restored to a state where the supply can be performed, and a malfunction is caused.

The present invention has been made in view of the above-mentioned problems of the related art, and particularly when the sleep mode operation is performed intermittently, the transition from the sleep mode to the active mode is performed. When detecting that all the transistor logic circuits having the mode switching means with the power supply cutoff function have completely returned to the state where the power can be completely supplied, the operation as the active mode is started and the malfunction is avoided. It is an object of the present invention to provide a semiconductor integrated logic circuit.

[0042]

In order to solve the above problems, a plurality of logic circuits, an active mode in which power is supplied to the plurality of logic circuits, and a sleep mode in which power to the plurality of logic circuits is cut off And a mode switching unit for performing a mode switching between the sleep mode and the active mode, wherein the mode switching unit instructs power supply and cutoff when switching between the sleep mode and the active mode intermittently. A signal is input to sequentially supply and shut off power to a plurality of logic circuits, and when switching from the sleep mode to the active mode, a signal indicating power supply is input to the plurality of logic circuits. Power supply to all logic circuits in a sequential manner, thereby returning all logic circuits to a state in which power can be supplied, and further operates as an active mode. And outputs a signal indicating that it is possible.

The mode switching means comprises a mode switching section provided in each of a plurality of logic circuits. The mode switching section comprises a p-channel MOS transistor and an n-channel MOS transistor, and includes a p-channel MOS transistor.
The gate electrode and the drain electrode of the OS-type transistor and the n-channel type MOS transistor are input and output, respectively, and are an inverter circuit. Power is supplied and supplied to the input part of the inverter circuit provided in the first-stage logic circuit. A sleep mode switching signal for instructing cutoff is input, and a sleep mode response signal indicating that operation in the active mode is possible is output from an output portion of an inverter circuit provided in the last logic circuit. It is characterized by.

The mode switching means functions as a switch for switching signals, and when switching from the active mode to the sleep mode, a p-channel MOS transistor constituting the mode switching means when a high level signal is input to its gate electrode. Shuts off, n-channel type M
When the OS transistor is turned on and the power to the plurality of logic circuits is cut off and the mode is switched from the sleep mode to the active mode, a low-level signal is input to the gate electrode of the p-channel type MO constituting the mode switching means.
The S transistor is turned on, the n-channel MOS transistor is turned off, and power is supplied to a plurality of logic circuits.

The mode switching means comprises a mode switching section provided in each of a plurality of logic circuits, and the mode switching section includes a predetermined number of p-channel type MOs provided in series.
An S transistor and a predetermined number of n-channel MOS transistors provided in parallel with the drain electrodes of a predetermined number of p-channel MOS transistors.
A gate electrode and a drain electrode of the S transistor serve as an input part and an output part, respectively, and are a NOR gate circuit in which the output part and the input part are sequentially connected. The input part of the NOR gate circuit provided in the first stage logic circuit is provided. A sleep mode switching signal is input to the section, and a sleep mode response signal is output from an output section of a NOR gate circuit provided in the final stage logic circuit.

The mode switching means comprises a mode switching section provided in each of a plurality of logic circuits, and the mode switching section includes a predetermined number of p-channel type MOs provided in parallel.
An S transistor, and a predetermined number of n-channel MOS transistors provided in series with the drain electrodes of a predetermined number of p-channel MOS transistors.
A gate electrode and a drain electrode of the S-transistor are an input unit and an output unit, respectively. The output unit and the input unit are sequentially connected to each other. The NAND gate circuit is connected to the input terminal of the NAND gate circuit provided in the first-stage logic circuit. A sleep mode switching signal is input to the section, and a sleep mode response signal is output from an output section of a NAND gate circuit provided in the last logic circuit.

The mode switching between an integrated logic circuit composed of a plurality of logic circuits and an active mode in which power is supplied to the plurality of logic circuits and a sleep mode in which power is supplied to the plurality of logic circuits is cut off. And a plurality of sleep mode switching signals and a plurality of sleep mode switching signals from a sleep mode switching signal instructing one of an active mode and a sleep mode as an input current mode. A distribution circuit for generating and distributing a sleep mode switching inversion signal in which the polarity of a signal is inverted, and a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit to determine a mode transition of the integrated logic circuit A plurality of logic circuits, wherein a plurality of sleep modes output by the distribution circuit are provided. And switching signal and the sleep mode switching inverted signal with each input, the current mode is characterized by outputting a sleep mode response signal indicating which one of the active mode and a sleep mode.

The determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit and outputs a NAND of them.
It is a gate circuit.

The determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit, and outputs a NAND of the sleep mode response signals.
It is a D-gate circuit.

Further, the determination circuit is an OR gate circuit which receives a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit and outputs a NOR of them.

Further, the determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit and outputs a NOR of them.
It is a gate circuit.

[0052] Further, there are provided a plurality of logic circuits, and mode switching means for performing mode switching between an active mode in which power is supplied to the plurality of logic circuits and a sleep mode in which power is supplied to the plurality of logic circuits. A power supply method for a semiconductor integrated logic circuit, comprising: when a sleep mode switching signal indicating one of an active mode and a sleep mode is input as a current mode input to a mode switching unit, a plurality of logics are supplied. The power supply to the circuit is sequentially supplied in a chain.

With the above configuration, when the sleep mode operation is intermittently executed in the semiconductor integrated circuit having the mode switching means with the power cutoff function, the mode transition between the active mode and the sleep mode is performed. All the transistors provided with a mode switching means with a power cutoff function when the sleep mode operation is intermittently performed, particularly when the mode transitions from the sleep mode to the active mode. After confirming that the logic circuit has completely returned to a state in which power can be completely supplied, an operation in the active mode can be started to avoid a malfunction.

[0054]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the first embodiment of the present invention.

As shown in FIG. 1, in this embodiment, NAND logic circuits NAND1a and NAND2a, inverter circuits INV2a to INV6a, an arbitrary transistor logic circuit FNC1, and NAND logic circuits NAND1a and NAN
D2a, inverter circuits INV2a to INV6a, mode switching means PSW1b to 6B (Power Switch) for supplying and cutting off power to the transistor logic circuit FNC1,
Consists of

In FIG. 1, the present embodiment is composed of a circuit group LGC1A to LGC56A having the above-described circuits therein, and each of the LGC1A to LGC6A has a PS.
W1b to PSW6b are provided. PSW1b-P
The switch SW6b switches between an active mode in which power is supplied to each circuit and a sleep mode in which power is cut off, and functions as a switch when a sleep mode switching signal SIN is input. Then, the PSWs 1b to 6b are turned ON / OFF to supply / cut off power to each circuit.

Here, IN1 to IN4 are data input, O
UT1 to OUT5 are data outputs, SIN is a sleep mode switching signal input, SOTB is a sleep mode response signal output, and the data inputs IN1 to IN4 and the sleep mode switching signal SIN are also supplied from an external circuit adjacent to this embodiment.

The supply / cutoff of power to each circuit in the semiconductor integrated logic circuit is performed as LGC2A → LGC as the sleep mode switching signal SIN flows through the semiconductor integrated logic circuit.
1A → LGC3A → LGC4A → LGC5A → LGC6
The sequence is performed in the order of A.

FIG. 2 is a detailed system diagram of the first embodiment of the semiconductor logic integrated circuit 101 provided with the mode switching means with the power cutoff response function shown in FIG.

In FIG. 2, mode switching observation means PSW
1 to PSW6 are all CMOS (Complementary Met)
al Oxide Semiconductor)
It is a low threshold or high threshold CMOS transistor. Of these, TSNP1A, TSP3A, TSNA1, TB
P1, TSN5A, TSBP2, TS6A, and TBP3 are high threshold p-channel and n-channel MOS transistors, and TSN2, TSP1, TDP1, TDP2,
TPN1, TPN2, TSN3, T1P1, T1N1,
TSP2, TBN1, TSP5, TBN2, T1P2
T1N2, TSP6, and TBN3 are low threshold P-channel and n-channel MOS transistors.

Since the low threshold MOSFET easily operates in a low voltage state, it can operate at high speed in the active mode, and the high threshold MOSFET transistor has a characteristic of turning on / off a high voltage level. .

Hereinafter, the mode switching means PSW1 to PSW6
The configuration of each circuit other than the above will be described.

First, the NAND logic circuit NAND1 includes a p-channel MOS transistor TDP1 and a transistor TDP2 connected in parallel, and an n-channel MOS transistor TDN1 and a transistor TDN2 connected in series to these transistors. The gate electrodes of the transistor TDP1 and the transistor TDN1 are commonly connected to receive the data signal IN1, and similarly the gate electrodes of the transistor TDP2 and the transistor TDN2 are commonly connected to receive the data signal IN2. Also,
Transistor TDP1 and transistor T connected in common
The drain electrodes of DP2 and the transistors TDN1 and TDN2 serve as output signal terminals of the NAND logic circuit NAND1, and the source electrodes of the commonly connected transistors TDP1 and TDP2 are connected to the NAND logic circuit NA.
ND1 is a high-potential-side power supply terminal (VDD) at one end, and the source electrode of the transistor TDN2 is connected to a NAND logic circuit NA.
It becomes the low potential side power supply terminal (GND) at the other end of ND1.

The NAND logic circuit NAND1 has a high-potential power supply terminal at one end connected to the power supply VDD, and a low-potential power supply terminal at the other end connected to the ground GND via the mode switching means PSW1.
These circuits constitute a NAND logic circuit LGC1A having a power supply cutoff function.

The NAND logic circuit NAND2 has the same circuit configuration and connection as the NAND logic circuit NAND1, and receives the data signals IN3 and IN4.

The NAND logic circuit NAND2 has a low-potential power supply terminal at one end connected to the ground GND, and a high-potential power supply terminal at the other end connected to the power supply VDD via the mode switching means PSW2.
These circuits constitute a NAND logic circuit LGC2A having a power cutoff function.

Next, the inverter circuit INV1 includes p-channel type MOS transistors TIP1 and n connected in series.
And a channel type MOS transistor TIN1. Transistor TIP1 and transistor TIN1
Gate electrodes are commonly connected to each other to form a NAND logic circuit N in the preceding stage.
The output signal of AND1 is input, and the drain electrodes of the transistor TIP1 and the transistor TIN1, which are connected in common, become the output signal terminals of the inverter circuit INV1. Further, the source electrode of the transistor TIP1 is a high-potential power supply terminal at one end of the inverter circuit INV1, and the source electrode of the transistor TIN1 is a low-potential power supply terminal at the other end of the inverter circuit INV1.

The inverter circuit INV2 has the same circuit connection configuration as the inverter circuit INV1, and uses the output signal of the preceding NAND logic circuit NAND2 as an input signal.

Here, inverter circuits INV1 and INV
2 is connected to the ground GND at one end, and the high potential side power terminal at the other end is connected to the mode switching means PSW.
3 and is commonly connected to the power supply VDD, and these circuits constitute a two-parallel inverter circuit LGC3A having a power cutoff function.

The transistor logic circuit FNC1 is composed of a low threshold CMOS transistor, receives the output signals of the inverter circuits INV1 and INV2 at the preceding stage, outputs two signals to the LGC5A and LGC6A at the next stage, and It has a pair of a potential side power supply terminal and a low potential side power supply terminal.

The transistor logic circuit FNC1 is
A high-potential power supply terminal at one end is connected to the power supply VDD, and a low-potential power supply terminal at the other end is connected to the ground GND via the mode switching means PSW4. It constitutes the LGC4A.

The inverter circuit INV3 comprises a p-channel MOS transistor TIP2 and an n-channel MOS transistor TIN2 connected in series. The gate electrodes of the transistor TIP2 and the transistor TIN2 are commonly connected to receive one output signal of the preceding transistor logic circuit FNC1, and the drain electrodes of the commonly connected transistor TIP2 and the transistor TIN2 are connected to the output signal of the inverter circuit INV3. The terminal T1 outputs the output signal OUT1, and the source electrode of the transistor TIP2 is connected to the inverter circuit INV3.
Of the transistor TIN
The source electrode 2 serves as a low-potential-side power supply terminal at the other end of the inverter circuit INV3.

The high-potential power supply terminal at one end of the inverter circuit INV3 is connected to the power supply VDD, and the low-potential power supply terminal at the other end is connected to the ground GND via the mode switching means PSW5. An inverter circuit LGC5A having a cutoff function is configured.

The inverter circuit INV4 has the same circuit configuration and connection as the inverter circuit INV3.
The other output signal of the preceding transistor logic circuit FNC1 is used as an input signal.

The high-potential power supply terminal at one end of the inverter circuit INV4 is connected to the power supply VDD, and the low-potential power supply terminal at the other end is connected to the ground G via the mode switching means PSW6.
ND, and these circuits constitute an inverter circuit LGC6A having a power cutoff function.

In the above, NAND2 and FNC1 are constituted by low threshold CMOS transistors, so that they can operate at high speed in the active mode.

As described above, the semiconductor integrated logic circuit 101 having the mode switching means with the power cutoff response function according to the present embodiment shown in FIG. 2 is different from the conventional semiconductor integrated logic circuit 100 shown in FIG. The circuits are logically the same in operation in a typical active mode.

Next, 6 which is a central circuit element of the present invention.
The circuit configuration of the mode transition observations PSW1 to PSW6 will be described below along the flow of the sleep mode switching signal SIN.

First, the mode switching means PSW2 comprises a p-channel MOS transistor TSP2A and an n-channel MOS transistor TSN2 connected in series. Transistor TSP2A and transistor TS
The gate electrodes of N2 are commonly connected, and the sleep mode switching signal SIN is input. Also, the transistor TSP2A
Is a high-potential-side power supply terminal at one end of the mode switching means PSW2, a source electrode of the transistor TSN2 is a low-potential-side power supply terminal at the other end of the mode switching means PSW2, and the transistors TSP2A and T
The drain electrode to which each of the transistors SN2 is connected in common becomes the high-potential-side power supply terminal N1 and the transistor logic circuit LGC
Power is supplied to the high potential side power supply terminal of the NAND logic circuit NAND2, which is another component of 2A.

Here, the current drivability of the p-channel MOS transistor TSP2A in the conductive state is necessary in consideration of the device parameters of the transistors constituting the NAND logic circuit NAND2, the basic operating frequency of the NAND logic circuit NAND2, and the signal transition probability. Set the appropriate current drive capability. Also, a p-channel MOS transistor TSP
The amount of leakage current in the 2A cutoff state is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current drive capability of the p-channel MOS transistor TSP2A in the conductive state is determined by setting the gate width larger than the sum of the gate widths of the p-channel MOS transistors TDP1 and TDP2 constituting the NAND logic circuit NAND2 to the p-channel MOS transistor TSP2A. Transistor TSP2
A is secured by giving it to A. Also, the p-channel MOS transistor TSP2A is set so that the amount of leakage current in the cutoff state of the p-channel MOS transistor TSP2A is smaller than the sub-threshold leakage current (standby current) of the NAND logic circuit NAND2.
It is ensured by increasing the threshold voltage of A, increasing the gate length, or increasing the thickness of the gate insulating film.

The mode switching means PSW1 includes a p-channel MOS transistor TSP1 and an n-channel MOS transistor TSN1A connected in series. The gate electrodes of the transistor TSP1 and the transistor TSN1A are connected in common, and the mode switching means PS of the preceding stage is connected.
The sleep mode response signal from the high-potential power supply terminal N1 of W2 is input, the source electrode of the transistor TSP1 is the high-potential power terminal at one end of the mode switching means PSW1, and the source electrode of the transistor TSN1A is the mode switch. The other terminal of the means PSW1 becomes a low-potential-side power supply terminal, and further includes a transistor TSP1 and a transistor TSN.
1A becomes a low-potential-side power supply terminal N2 and the drain electrode to which each of the transistors 1A is connected in common becomes a transistor logic circuit LGC1.
Power is supplied to the low potential side power supply terminal of the NAND logic circuit NAND1, which is another component of A.

Here, the current drivability of the n-channel MOS transistor TSN1A in the conductive state is necessary in consideration of the device parameters of the transistors constituting the NAND logic circuit NAND1, the basic operating frequency of the NAND logic circuit NAND1, and the signal transition probability. Set the appropriate current drive capability. Also, an n-channel MOS transistor TS
The amount of leakage current in the N1A cutoff state is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current driving capability of the n-channel MOS transistor TSN1A in the conductive state is determined by setting the gate width larger than the sum of the gate widths of the n-channel MOS transistors TDN1 and TDN2 constituting the NAND logic circuit NAND1 to the n-channel MOS transistor TSN1A. Transistor TSN1
A is secured by giving it to A. Also, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN1A is smaller than the sub-threshold leakage current of the NAND logic circuit NAND1.
This is ensured by increasing the threshold voltage of the n-channel MOS transistor TSN1A, increasing the gate length, or increasing the thickness of the gate insulating film.

The mode switching means PSW3 comprises a p-channel MOS transistor TSP3A and an n-channel MOS transistor TSN3 connected in series. The gate electrodes of the transistor TSP3A and the transistor TSN3 are connected in common, and the mode switching means PS of the preceding stage is connected.
The response signal from the low-potential-side power supply terminal N2 of W1 is input, the source electrode of the transistor TSP3A is a high-potential-side power terminal at one end of the mode switching means PSW3, and the source electrode of the transistor TSN3 is the mode switching means PSW3 Is connected to the low-potential-side power supply terminal N. The drain electrode to which the transistor TSP3A and the transistor TSN3 are commonly connected is connected to the high-potential-side power supply terminal N.
The power is supplied to the high potential side power supply terminals of the inverter circuits INV1 and INV2, which are other components of the transistor logic circuit LGC3A.

Here, the current driving capability of the p-channel MOS transistor TSP3A in the conductive state depends on the device parameters of the transistors constituting the inverter circuits INV1 and INV2 and the inverter circuits INV1 and IV2.
The necessary current drivability is set in consideration of the basic operating frequency of NV2 and the signal transition probability. Also, p-channel type MOS
The amount of leakage current in the cut-off state of the transistor TSP3A is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current driving capability of the p-channel MOS transistor TSP3A in the conductive state is determined by the p-channel MOS transistors T1 and T2 constituting the inverter circuits INV1 and INV2.
This is ensured by giving the p-channel MOS transistor TSP3A a gate width larger than the sum of the gate widths of the OS transistors TIP1 and TIN1. Also, p
The amount of leakage current in the cutoff state of the channel type MOS transistor TSP3A is determined by the inverter circuits INV1 and INV
2 so that the amount of leakage current is smaller than the sub-threshold leakage current
This is ensured by increasing the threshold voltage of P3A, increasing the gate length, or increasing the thickness of the gate insulating film.

The mode switching means PSW4 is formed of a CMOS transistor and is connected in series with a p-channel MOS transistor TSP4 and an n-channel MOS transistor TBP1, and a p-channel MOS transistor TBP1 and an n-channel MOS transistor TBN.
1 and connected in parallel with each other. Here, p-channel MOS transistors TSP4 and TSN
4A is a circuit functioning as a mode switching means, and includes a p-channel MOS transistor TBP1 and an n-channel M transistor.
The OS transistor TBN1 is an inverter that inverts the polarity of the signal.

Transistor TSP4 and transistor TS
The gate electrode of N4A is connected in common, and a sleep mode response signal from the high potential side power supply terminal N3 of the preceding mode switching means PSW3 is input, and the transistor TS
The source electrode of P4 is a high-potential power supply terminal at one end of the mode switching means PSW4, and the source electrode of the transistor TSN4A is a low-potential power supply terminal at the other end of the mode switching means PSW4. Further, the drain electrode to which the transistor TSP4 and the transistor TSN4A are commonly connected becomes a low-potential-side power supply terminal N4 to supply power to the low-potential-side power supply terminal of the transistor logic circuit FNC1, which is another component of the transistor logic circuit LGC4A. Supply.

On the other hand, the gate electrodes of the transistor TBP1 and the transistor TBN1 are commonly connected and a sleep mode response signal is input from the low potential side power supply terminal N4, and the source electrode of the transistor TBP1 is connected to one end of the mode switching means PSW4. A high-potential-side power supply terminal, and the source electrode of the transistor TBN1 is connected to the mode switching means PS
The other end of W4 becomes the low potential side power supply terminal, and the drain electrode to which the transistor TBP1 and the transistor TBN1 are commonly connected becomes the sleep mode response signal output terminal N5 to output the sleep mode response signal to the LGC 5A of the next stage. I do.

Here, the current drivability in the conductive state of the n-channel MOS transistor TSN4A is necessary in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC1, the basic operating frequency of the transistor logic circuit FNC1, and the signal transition probability. Set the appropriate current drive capability. Further, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN4A is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current drivability of the n-channel MOS transistor TSN4A in the conductive state depends on the gate width of the n-channel MOS transistor constituting the transistor logic circuit FNC1 in consideration of the basic operating frequency and the signal transition probability. The n-channel MOS transistor TSN4A has a gate width smaller than the sum. The amount of leakage current in the cut-off state of the n-channel MOS transistor TSN4A is determined by the transistor logic circuit FN
An n-channel MOS transistor T is selected so that the amount of leakage current is smaller than the sub-threshold leakage current of C1.
It is ensured by increasing the threshold voltage of SN4A, increasing the gate length, or increasing the thickness of the gate insulating film.

The p-channel MOS transistor T
The amount of leakage current in the cutoff state of the BP1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. For example, the threshold voltage is increased, the gate length is increased, or the gate insulating film is removed. Secure by thickening.

The mode switching means PSW5 comprises a p-channel MOS transistor TSP5 and an n-channel MOS transistor TSN5A and a p-channel MOS transistor TBP2 and an n-channel MOS transistor TBN2 connected in series, and are connected in parallel with each other. ing. Here, a p-channel MOS transistor T
SP5 and n-channel MOS transistor TSN5 are circuits that function as mode switching means, and p-channel MOS transistor TBP2 and n-channel MOS transistor TBN2 are inverters that invert the polarity of the signal.

Transistor TSP5 and transistor TS
The gate electrode of N5A is commonly connected to receive a response signal from the sleep mode response signal output terminal N5 of the preceding mode switching means PSW4.
Is a high-potential-side power supply terminal at one end of the mode switching means PSW5, and the source electrode of the transistor TSN5A is a low-potential-side power supply terminal at the other end of the mode transition observation PSW5. Further, the drain electrode to which the transistor TSP5 and the transistor TSN5A are commonly connected becomes the low-potential-side power supply terminal N6, and the transistor logic circuit L
Inverter circuit INV3 which is another component of GC5A
Is supplied to the low-potential-side power supply terminal. On the other hand, the gate electrodes of the transistor TBP2 and the transistor TBN2 are commonly connected, a sleep mode response signal is input from the low potential side power supply terminal N6, and the transistor TBP2
Is a high-potential-side power supply terminal at one end of the mode switching means PSW5, a source electrode of the transistor TBN2 is a low-potential-side power supply terminal at the other end of the mode switching means PSW5.
The drain electrode to which each of the BN2 is commonly connected becomes the sleep mode response signal output terminal N7, and the next stage LGC6A
Output a sleep mode response signal to the

Here, the current driving capability of the n-channel MOS transistor TSN5A in the conductive state is determined by the necessary current in consideration of the device parameters of the transistors constituting the inverter circuit INV3 and the basic operating frequency and signal transition probability of the inverter circuit INV3. Set the driving capacity. Further, an n-channel MOS transistor TSN5
The amount of leakage current in the cutoff state of A is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current drivability in the conductive state of the n-channel MOS transistor TSN5A is determined by considering the basic operating frequency of the inverter circuit INV3 and the signal transition probability, and taking into consideration the sum of the gate widths of the n-channel MOS transistors constituting the inverter circuit INV3. A smaller gate width is provided to the p-channel MOS transistor TSN5A. Also, n
The threshold voltage of the n-channel MOS transistor TSN5A is increased or the gate length is reduced so that the leakage current in the cutoff state of the channel MOS transistor TSN5A becomes smaller than the sub-threshold leakage current of the inverter circuit INV3. It is ensured by lengthening or increasing the thickness of the gate insulating film.

Further, a p-channel type MOS transistor T
The amount of leakage current in the cutoff state of the BP2 is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. For example, the threshold voltage is increased, the gate length is increased, or the gate insulating film is removed. Secure by thickening.

The mode switching means PSW6 comprises a p-channel MOS transistor TSP6, an n-channel MOS transistor TSN6A and a p-channel MOS transistor TBP3 and an n-channel MOS transistor TBN3 connected in series, and are connected in parallel with each other. ing. Here, a p-channel MOS transistor T
SP6 and n-channel MOS transistor TSN6A are circuits that function as mode switching means, and p-channel MOS transistor TBP3 and n-channel MOS transistor TBN3 are inverters that invert the polarity of the signal.

The transistor TSP6 and the transistor TS
The gate electrode of N6A is commonly connected to receive a sleep mode response signal from the sleep mode response signal output terminal N7 of the preceding mode switching means PSW5, and the source electrode of the transistor TSP6 is connected to the high potential side at one end of the mode switching means PSW6. Power supply terminal, transistor TSN6
The source electrode of A serves as a low-potential-side power supply terminal at the other end of the mode switching means PSW6. Further, the drain electrode to which the transistor TSP6 and the transistor TSN6A are commonly connected becomes a low-potential power supply terminal N8 to supply power to the low-potential power terminal of the inverter circuit INV4, which is another component of the transistor logic circuit LGC6A. Perform

On the other hand, the gate electrodes of the transistor TBP3 and the transistor TBN3 are commonly connected, and a sleep mode response signal is input from the low potential side power supply terminal N8. The source electrode of the transistor TBP3 is connected to one end of the mode switching means PSW6. A high-potential-side power supply terminal, and the source electrode of the transistor TBN3 is connected to the mode switching means PS.
The other end of W6 serves as a low-potential-side power supply terminal, and the drain electrode to which each of the transistors TBP3 and TBN3 is commonly connected serves as a sleep mode response signal output terminal, and a sleep mode response signal SOTB is output to the outside of the transistor logic circuit LGC6A. Is output.

Here, the current drivability in the conductive state of the n-channel MOS transistor TSN6A depends on the device parameters of the transistors constituting the inverter circuit INV4 and the necessary current in consideration of the basic operating frequency and signal transition probability of the inverter circuit INV4. Set the driving capacity. Also, an n-channel MOS transistor TSN6A
Is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

For example, the current drivability in the conductive state of the n-channel MOS transistor TSN6A is determined by taking into consideration the basic operating frequency of the inverter circuit INV4 and the signal transition rate, and the sum of the gate widths of the n-channel MOS transistors constituting the transistor. A smaller gate width is provided to the p-channel MOS transistor TSN6A. Also, the threshold voltage of the n-channel MOS transistor TSN6A is increased so that the leakage current in the cutoff state of the n-channel MOS transistor TSN6A is smaller than the sub-threshold leakage current of the inverter circuit INV4. It is ensured by increasing the gate length or increasing the thickness of the gate insulating film.

The n-channel MOS transistor T
The amount of leakage current in the cutoff state of the BSP 6 is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. For example, the threshold voltage is increased, the gate length is increased, or the gate insulating film is removed. Secure by thickening.

Semiconductor integrated logic circuit 10 having mode switching means with power cutoff response function according to the present invention shown in FIG.
The mode switching operation between the sleep mode and the active mode in the first operation will be briefly described below.

First, assuming that the semiconductor integrated logic circuit 101 is in the active mode state, the sleep mode switching signal SIN is at the low level, that is, SIN
= 0 is applied.

Therefore, in the active mode, n-channel MOS transistors TSN2 and TSN3 forming mode switching means PSW2 and PSW3 are in the cut-off state, while p-channel MOS transistors TSP2A and TSP3A are in the conductive state, respectively. Are connected to NAND logic circuit NAND2 and inverter circuits INV1 and INV1 via high potential side power supply terminals N1 and N3.
The high-potential-side power is supplied to each of the V2 parallel circuits. Similarly, p-channel MOS transistors T forming mode switching means PSW1, PSW4, PSW5 and PSW6
SP1, TSP4, TSP5, and TBP6 are in the cutoff state. Further, an n-channel MOS transistor TSN1
A, TSN4A, TSN5A, and TSN6A are in a conductive state, and the low potential side power supply terminals N2, N4, N6 and N
8, a low-potential-side power supply is supplied to each of the NAND logic circuit NAND1, the transistor logic circuit FNC1, the inverter circuit INV3, and the inverter circuit INV4.

The mode switching means PSW4, PSW5
And n-channel MOS transistors TBN1, TBN2, TBN3 constituting PSW6 are in a cut-off state,
p-channel type MOS transistors TBP1, TBP2,
Since TBP3 is conducting, response signal terminals N5 and N5
7 and the sleep mode response signal SOTB
A level signal is output.

Before starting the description of the actual circuit operation, the configuration and function of the inverter INV circuit, which is a basic circuit component of this embodiment, will be described here.

FIG. 3 is a diagram showing the configuration and functions of the inverter circuit.

In FIG. 3, a p-channel MOS transistor and an n-channel MOS transistor are connected in series. Here, the source of the p-channel MOS transistor is connected to the high potential side power supply (VDD), and the drain is connected to the drain of the n-channel MOS transistor. The source of the n-channel MOS transistor is connected to a low potential side power supply (GND). p
The gate electrodes of the channel type MOS transistor and the n-channel type MOS transistor are commonly connected to form an inverter circuit.

The inverter turns off when the voltage between the source and the drain of the p-channel MOS transistor falls below a certain fixed voltage (for example, 5 V), and turns off the n-channel MOS transistor with a certain fixed voltage (for example, 0 V).
When it becomes higher, there is a characteristic of conducting (ON). An inverter circuit that operates as a switch by connecting a p-channel type MOS transistor and an n-channel type MSO transistor in series utilizing this characteristic. As is well known, an inverter circuit is a circuit that outputs "1" when "0" is input and outputs "0" when "1" is input. In other words, gradually lower the input voltage,
When the voltage exceeds the threshold voltage, the current IDD starts flowing. At this time, since the n-channel MOS transistor is "OFF", the output voltage becomes 5V.

The input voltage is between the power supply VDD and the ground GN.
When the voltage reaches approximately 2.5 V, which is 1/2 of D, the p-channel MOS transistor and the n-channel MOS transistor are turned on, and the p-channel MOS transistor and the n-channel MOS transistor are in exactly the same state. And the output voltage becomes a conversion point (threshold voltage) at which the output voltage changes from 5V to 0V. Further, when the input voltage is increased to 5 V, the p-channel MOS transistor is now turned on by “OF”.
F "and the output voltage becomes 0V.

Here, the threshold voltage at which the output voltage changes from VDD to GND is about 2.5 V. However, the threshold voltage depends on variations in transistor characteristics such as transistor size, gate length, and gate oxide film thickness. Is done.

As described above, the current ID does not flow from VDD when the input voltage is between 0 V and the threshold voltage of the n-channel MOS transistor.
No current flows between the threshold voltages of the S transistors. That is, a current flows while the input voltage changes from 0 V to 5 V, but does not flow in a steady state where the input voltage is either 0 V or 5 V.

Here, when a high-level sleep mode switching signal SIN is input, the n-channel MOS transistor of the inverter circuit is cut off and turned off.
, The p-channel MOS transistor is turned “ON”, the power supply to the connected INV, NAND, transistor logic circuit and the like is cut off, and the function as the logic circuit is stopped.

On the other hand, when the low-level sleep mode switching signal SIN is input, the n-channel MOS
The transistor is turned “ON”, the p-channel MOS transistor is cut off and turned “OFF”, and power is supplied to the connected INV, NAND, transistor logic circuit, etc. Function starts.

In general, a low threshold CMOS transistor can operate at high speed in the active mode.

FIG. 4 is a mode transition diagram showing mode switching.

As shown in FIG. 4, there are two modes, an active mode 21 and a sleep mode 20. As described above, the active mode 21 refers to a state in which power is supplied to each mode switching unit, and the sleep mode refers to a state in which power supply to each mode switching unit is shut off. Switching from the active mode to the sleep mode or from the sleep mode to the active mode is performed by mode switching means. In this embodiment,
As shown in FIGS. 3 and 4, the mode switching means is realized by an INV circuit, a NAND gate circuit, a NOR gate circuit and the like. Actually, switching is performed according to the state of a signal input to the mode switching means, that is, whether the signal is High level (1) or Low level (0).

When switching from the active mode to the sleep mode, the sleep mode switching signal SIN is set to Low.
Change from level to high level. When the high-level sleep mode switching signal SIN is input, the mode switching unit cuts off power to the transistor logic circuit. As a result, the function as the transistor logic circuit stops.

On the other hand, when switching from the sleep mode to the active mode, the sleep mode switching signal SIN is changed from a high level to a low level. Low
When the sleep mode switching signal SIN of the level is input,
The mode switching means supplies power to the transistor logic circuit. As a result, the function as the transistor logic circuit starts.

When switching between the active mode and the sleep mode or in any one of the modes for switching from the sleep mode to the active mode, the switching is performed after completely switching to either mode.

FIG. 5 is a timing chart showing the operation of this embodiment.

The timing chart of FIG. 5 shows the sleep mode switching signal SIN of the semiconductor integrated logic circuit 101 of FIG.
, The high (low) potential side power supply terminals (N1 to N8) of the LGC1A to LGC6A, and the sleep mode switching signal SI at the output point of the sleep mode mode response signal SOTB.
It is a figure which shows the signal waveform of N in time series. Note that this timing chart is mainly for switching from the active mode (t1) to the sleep mode (t4), and when the sleep mode switching inversion signal SINB is used, the signal waveform becomes exactly the opposite.

As shown in FIG. 5, the active mode (t
There are four periods: 1), a transition period (t2) from the active mode to the sleep mode, a sleep mode (t3), and a transition period (t4) from the sleep mode to the active mode.

First, when a high-level sleep mode switching signal SIN is input, the polarity is inverted and output after a certain time (d1). Then, the transition from the active mode (t1) to the sleep mode transition period (t2) occurs at the midpoint where the sleep mode switching signal SIN changes from the low level to the high level. The transition period from a certain active mode to the sleep mode (t
After elapse of 2), the mode is switched from the active mode (t1) to the sleep mode. The sleep mode switching signal SIN output from the first circuit is input to the next circuit, and after a certain fixed time (d1) same as that of the first circuit, the polarity is inverted and output. Then, after a transition period (t1) from a certain active mode to the sleep mode has elapsed, the mode is switched from the active mode to the sleep mode.

Thereafter, when the sleep mode switching signal SIN changes from the high level to the low level, the transition period from the sleep mode (t3) to the active mode occurs at the midpoint where the sleep mode switching signal SIN changes from the high level to the low level. The process proceeds to t4). This time, the mode is switched from the active mode to the sleep mode in the reverse order.

FIG. 6A is a diagram showing the configuration and operation of an n-input NAND gate circuit.

In FIG. 6A, N p-channel MOS transistors PA1 to PAn are connected in parallel,
N n-channel MOS transistors NA1 to NAn
Are connected in series to p-channel MOS transistors PA1 to PAn. Here, the sources of the p-channel MOS transistors PA1 to PAn are connected to a high-potential-side power supply (VD
1), and the drains are connected to the drains of the n-channel transistors NA1 to NAn. Also, n
The sources of the channel type MOS transistors NA1 to NAn are connected to a low potential side power supply (VC). Gate electrodes of p-channel MOS transistor PA1 and n-channel MOS transistor NA1, p-channel MOS transistor PA2 and n-channel MOS transistor N
The gate electrode of A2 and the gate electrodes of the p-channel MOS transistor PAn and the n-channel MOS transistor NAn are commonly connected to form a NAND gate circuit.

As is well known, the output of a NAND circuit becomes "0" when all the inputs become "1", and all the outputs become "1" when any one of the inputs becomes "0". is there. That is, all the inputs of the sleep mode switching signals SINB1 to SINBn shown in FIG.
gh, the p-channel MOS transistors PA1 to PAn are turned off (OFF), and the n-channel MOS transistors PA1 to PAn are turned off.
The S transistors NA1 to NAn conduct (ON), and their outputs become “0”. At this time, since the p-channel MOS transistors PA1 to PAn are cut off and cut off, the power supply from the power supply VD1 to the transistor circuit is cut off.

On the other hand, sleep mode switching signal SINB1
When any one of the input signals -SINbn goes low, the p-channel MOS transistors PA1 to PAn
Are turned on, and n-channel MOS transistors NA1 to N
An is cut off and its output becomes "1". At this time, p
Since the channel MOS transistors PA1 to PAn conduct, power is supplied from the power supply VD1 to the transistor circuit (current ID1 flows).

As described above, when the high-level sleep mode switching signals SINB1 to SIBn are input, p
The channel type MOS transistors PA1 to PAn are cut off and cut off, and the n-channel type MOS transistor NA is cut off.
1 to NAn conduct, the power supply from the power supply VD1 to the transistor circuit connected thereto is cut off, and the function as a logic circuit stops.

When low-level sleep mode switching signals SINB1 to SINBn are input, p-channel MOS transistors PA1 to PAn are turned on, and n-channel MOS transistors NA1 to NAn are cut off.
The power supply VD1 is supplied to the transistor circuit connected to the
And the function as a logic circuit starts.

FIG. 6B is a diagram showing the configuration and operation of an n-input NOR gate circuit.

In FIG. 6B, N p-channel MOS transistors PB1 to PBn are connected in series.
N n-channel MOS transistors NB1 to NBn
Are p-channel MOS transistors connected in parallel. Here, the p-channel MOS transistor PB1
To PBn are connected to a high potential side power supply (VD),
The drain is connected to the drains of the n-channel transistors NB1 to NBn. Also, n-channel type MOS
The drains of the transistors NB1 to NBn are connected to the lower potential power supply (VS1). And p-channel type M
The gate electrodes of the OS transistor PB1 and the n-channel MOS transistor NB1, the p-channel MOS transistor PB2 and the n-channel MOS transistor NB2
Gate electrode and a p-channel MOS transistor PB
The gate electrodes of n and the n-channel MOS transistor NBn are commonly connected to form a NOR gate circuit.

As is well known, the NOR gate circuit is a circuit in which the output becomes "0" when any one of the inputs becomes "1", and the output becomes "1" when all the inputs become "0". That is, one of the inputs of the sleep mode switching signals SINB1 to SINBn shown in FIG.
gh level, the p-channel MOS transistors PB1 to PBn are shut off (OFF), and the n-channel MOS transistors PB1 to PBn are turned off.
The S transistors NB1 to NBn conduct (ON), and the output becomes “1”. At this time, since the p-channel MOS transistors PB1 to PBn are cut off and cut off,
The power supply from the power supply VD1 to the transistor circuit is cut off.

On the other hand, sleep mode switching signal SINB1
When all the inputs of ~ SINBn become Low level,
The p-channel MOS transistors PB1 to PBn conduct, the n-channel MOS transistors NB1 to NBn shut off, and the output becomes “1”. At this time, since the p-channel MOS transistors PB1 to PBn conduct, power is supplied from the power supply VD1 to the transistor circuit (current ID flows).

As described above, when the high-level sleep mode switching signals SINB1 to SIBn are input, the p-channel MOS transistors PB1 to PBn are cut off and cut off, and the n-channel MOS transistors NB1 to NBn are turned on. As a result, the power supply from the power supply VD is cut off to the transistor circuit connected thereto,
The function as a logic circuit stops.

When the low-level sleep mode switching signals SINB1 to SINBn are input, the p-channel MOS transistors PB1 to PBn become conductive, and n
The channel-type MOS transistors NB1 to NBn are cut off and cut off, and power is supplied from the power supply VDD to the transistor circuit connected to the cutoff, and the function as a logic circuit starts.

When the signals of the internal circuits of the semiconductor integrated logic circuit 101 according to the first embodiment of the present invention are set to the initial state, and the mode is changed from the active mode to the sleep mode with reference to FIGS. Will be described below.

The circuit response will be described along the flow of the sleep mode switching signal SIN.

To switch from the active mode to the sleep mode, the sleep mode switching signal SIN is changed from a low level to a high level. Then PSW
1 to PSW 6 sequentially shut off the power to each mode switching unit along the flow of the sleep mode switching signal, and switch to the sleep mode.

When the sleep mode switching signal SIN is changed from low level to high level, LGC1A
First, the p-channel MOS transistor TSP2A constituting the mode switching means PSW2 is turned off and the n-channel MOS transistor TSN2 is turned on, so that the supply of the high potential side power to the NAND logic circuit NAND2 is started. Stop and high potential side power supply terminal N1
Changes from a High level to a Low level. As a result, the logic operation of the NAND logic circuit LGC2A is forcibly stopped as a NAND logic circuit, and the power consumed by the NAND logic circuit LGC2A is a leakage current determined by the device parameters of the p-channel MOS transistor TSP2A in the cutoff state. Only. As described above, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSP2A is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

In the LGC 1A, the p-channel MOS transistor TSP1 constituting the mode switching means PSW1 becomes conductive and the n-channel type when the high-potential power supply terminal N1 transitions from the high level to the low level in the LGC 2A. MOS transistor TSN1A
Is shut off, the supply of the low-potential-side power to the NAND logic circuit NAND1 is stopped, and the low-potential-side power supply terminal N2 transits from a low level to a high level.
As a result, the NAND logic circuit LGC1 having the power cutoff function is provided.
A is an n-channel MOS transistor TSN in which the logic operation as a NAND logic circuit is forcibly stopped and the power consumed by the NAND logic circuit LGC1A is cut off.
There is only a leakage current determined by the device parameter of 1A. As described above, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN1A has a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

When the low potential side power supply terminal N2 transitions from the Low level to the High level in the LGC 2A, the p-channel MOS transistor TSP3A constituting the mode switching means PSW3 is turned off and the n-channel type is turned on. MOS transistor TSN3
Become conductive, and inverter circuits INV1, INV
The supply of the high-potential-side power to the two parallel circuits is stopped, and the high-potential-side power supply terminal N3 transitions from a high level to a low level. As a result, the logic operation of the two-parallel inverter circuit LGC3A with the power cutoff function is forcibly stopped as the two-parallel inverter circuit, and the power consumed by the two-parallel inverter circuit LGC3A is cut off. Only the leak current determined by the device parameters of the TSP 3A is obtained. Here, as described above, the p-channel MOS transistor TS
The amount of leakage current in the cutoff state of P3A is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

In the LGC 4A, the p-channel type MOS transistor TSP4 constituting the mode switching means PSW4 becomes conductive and the n-channel type when the high potential side power supply terminal N3 transitions from the High level to the Low level in the LGC 3A. MOS transistor TSN4A
Is turned off, the supply of the low-potential-side power to the transistor logic circuit FNC1 is stopped, and the low-potential-side power supply terminal N4 transits from a low level to a high level. As a result, the logic operation of the transistor logic circuit LGC4A having the power cutoff function as the transistor logic circuit is forcibly stopped, and the transistor logic circuit LGC4C is turned off.
The power consumed at 4A is n-channel type M
Only the leak current determined by the device parameter of the OS transistor TSN4A is obtained. As described above, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN4A is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. Further, the transition of the low-potential-side power supply terminal N4 from the Low level to the High level causes the p-channel MOS transistor TBP1 constituting the mode switching means PSW4 to be turned off and the n-channel MOS transistor TBN1 to be turned on. And the sleep mode response signal terminal N5 becomes Hi.
The state transits from the gh level to the Low level. As described above, the amount of leakage current in the cutoff state of the p-channel MOS transistor TBP1 is set to a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode.

When the response signal terminal N5 transitions from the high level to the low level in the LGC 4A, the p-channel MOS transistor TSP5 constituting the mode switching means PSW5 becomes conductive and the n-channel MOS transistor TSN5A Is turned off, the supply of the low-potential-side power to the inverter circuit INV3 is stopped, and the low-potential-side power supply terminal N6 is set to Lo.
The state transits from the w level to the High level. As a result,
The logic operation of the inverter circuit LGC5A with the power cutoff function as the transistor logic circuit is forcibly stopped,
In addition, the power consumed by inverter circuit LGC5A is turned off and n-channel MOS transistor TSN5A is turned off.
Only the leakage current determined by the device parameter of As described above, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN5A has a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. Further, the transition of the low-potential-side power supply terminal N6 from the Low level to the High level causes one of the p-channel MOS transistors TBP2 constituting the mode switching means PSW5 to be cut off and the n-channel MOS transistor TBn2 to be conductive. State, and the sleep mode response signal terminal N7 changes from the High level to the Lo level.
Transition to the w level. Here, as described above, the amount of leakage current in the cutoff state of the p-channel MOS transistor TBP2 is determined by the semiconductor integrated logic circuit 1 in the sleep mode.
Since the value is set in consideration of the current consumption of 01, the value is sufficiently small.

When the response signal terminal N7 transitions from the high level to the low level in the LGC 5A, the p-channel MOS transistor TSP6 constituting the mode switching means PSW6 becomes conductive and the n-channel MOS transistor TSN6A Is turned off, the supply of the low-potential-side power to the inverter circuit INV4 is stopped, and the low-potential-side power supply terminal N8 is set to Lo.
The state transits from the w level to the High level. As a result,
The logic operation of the inverter circuit LGC6A with the power cutoff function as the transistor logic circuit is forcibly stopped,
In addition, the power consumed by inverter circuit LGC6A is turned off and n-channel MOS transistor TSN6A
Only the leakage current determined by the device parameter of Here, as described above, the amount of leakage current in the cut-off state of the n-channel MOS transistor TSN6A is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 101 in the sleep mode. Further, the transition of the low-potential-side power supply terminal N8 from the Low level to the High level causes one of the p-channel MOS transistors TBP2 constituting the mode switching means PSW6 to be cut off and the n-channel MOS transistor TBN3 to be conductive. State, and the sleep mode response signal SOTB changes from the High level to the Lo level.
Transition to the w level. Here, as described above, the amount of leakage current when the p-channel MOS transistor TBP3 is in the cut-off state depends on the amount of the semiconductor integrated logic circuit 1 in the sleep mode.
Since the value is set in consideration of the current consumption of 01, the value is sufficiently small.

As described above, the sleep mode switching signal SIN is changed from the low level to the high level to transition from the active mode to the sleep mode, and as a result of the above-described series of chained circuit operations, the sleep mode The response signal SOTB changes from the high level to the low level.
Each of the circuits LGC1 having the power cutoff function, which constitute the semiconductor integrated logic circuit 101, is changed to the w level.
Power supply to A to LGC 6A can be completely stopped.

Next, the circuit response when the mode is changed from the sleep mode to the active mode will be described below with reference to FIGS.

When switching from the sleep mode to the active mode, the sleep mode switching signal SIN is set to Hig.
The level is changed from the h level to the Low level. Then PS
W1 to PSW6 sequentially supply power to each mode switching unit along the flow of the sleep mode switching signal, and switch to the active mode.

When sleep mode switching signal SIN is set to High
When changing from the level to the low level, the LGC2A
First, the p-channel MOS transistor TSP2A constituting the mode switching means PSW2 is turned on and the n-channel MOS transistor TSN2 is turned off, so that the supply of the high potential side power to the NAND logic circuit NAND2 is started. Start and the high potential side power supply terminal N1
Changes from a low level to a high level. As a result, the NAND logic circuit LGC2A with the power cutoff function is in a state where it can perform a logical operation as the NAND logic circuit.

In the LGC 1A, the p-channel type MOS transistor TSP1 constituting the mode switching means PSW1 is cut off and the n-channel type when the high potential side power supply terminal N1 transitions from the Low level to the High level in the LGC 2A. MOS transistor TSN1A
Is turned on, the supply of the low-potential-side power to the NAND logic circuit NAND1 starts, and the low-potential-side power supply terminal N2 transitions from the High level to the Low level.
As a result, the NAND logic circuit LGC1 having the power cutoff function is provided.
A is in a state where a logical operation as a NAND logic circuit is possible.

When the low-potential-side power supply terminal N2 transitions from the high level to the low level in the LGC 2A, the p-channel MOS transistor TSP3A constituting the mode switching means PSW3 becomes conductive and the n-channel type MOS transistor TSN3
Are shut off, and the inverter circuits INV1, INV
The supply of the high-potential-side power to the two parallel circuits starts, and the high-potential-side power supply terminal N3 transitions from a low level to a high level. As a result, the two-parallel inverter circuit LGC3A with the power cutoff function is in a state where the logical operation as the two-parallel inverter circuit is possible.

When the high potential power supply terminal N3 transitions from the low level to the high level in the LGC 3A, the p-channel MOS transistor TSP4 constituting the mode switching means PSW4 is turned off and the n-channel type MOS transistor TSN4A
Is turned on, the supply of the low-potential-side power to the transistor logic circuit FNC1 starts, and the low-potential-side power supply terminal N4 transitions from the High level to the Low level. As a result, the transistor logic circuit LGC4A with the power cutoff function is in a state where the logic operation as the transistor logic circuit is possible. Furthermore, the low potential side power supply terminal N4
Is changed from the High level to the Low level, one of the p-channel MOS transistors TBP1 constituting the mode switching means PSW4 is turned on and the n-channel MOS transistor TBN1 is turned off, and the response signal terminal is turned off. N5 becomes Hi from Low level
gh level.

In the LGC 5A, when the response signal terminal N5 transitions from the low level to the high level in the LGC 4A, the p-channel MOS transistor TSP5 constituting the mode switching means PSW5 is turned off and the n-channel MOS transistor TSN5A Becomes conductive, the supply of the low-potential-side power to the inverter circuit INV3 starts, and the low-potential-side power supply terminal N6 is set to Hi.
The state transits from the gh level to the Low level. As a result,
The inverter circuit LGC5A with a power cutoff function is in a state where a logic operation as a transistor logic circuit is possible.
Further, since the low-potential-side power supply terminal N6 transitions from the Hgih level to the Low level, one of the p-channel MOS transistors TBP2 constituting the mode switching means PSW5 becomes conductive and the n-channel MOS transistor TBP2 becomes conductive.
The S transistor TBN2 is turned off, and the sleep mode response signal terminal N7 transitions from a low level to a high level.

When the response signal terminal N7 changes from the low level to the high level in the LGC 5A, the p-channel MOS transistor TSP6 constituting the mode switching means PSW6 is cut off and the n-channel MOS transistor TSN6A Is turned on, the supply of the low-potential-side power to the inverter circuit INV4 starts, and the low-potential-side power supply terminal N8 becomes Hi.
The state transits from the gh level to the Low level. As a result,
The inverter circuit LGC6A with the power cutoff function is in a state where a logic operation as a transistor logic circuit is possible.
Further, the transition of the low-potential-side power supply terminal N8 from the High level to the Low level causes one of the p-channel MOS transistors TBP3 constituting the mode switching means PSW6 to be in a conducting state and the n-channel MO transistor
The S transistor TBN3 is turned off, and the sleep mode response signal SOTB changes from a low level to a high level.

As described above, in the present embodiment, when the sleep mode operation is intermittently executed, each of the circuits LGC1A to LGC6A of the semiconductor integrated logic circuit 101 is provided between the active mode and the sleep mode and between the sleep mode and the active mode. A mode switching means having a power cutoff function as a result of the above series of chained circuit operations, particularly when transitioning from the sleep mode to the active mode. After confirming that all the transistor logic circuits provided with have completely returned to a state where they can be completely supplied with power, the logic operation of the normal circuit as the active mode can be started. Perform stable active mode operation without causing Door can be.

In the first embodiment shown in FIG. 2, there is shown a system diagram of a semiconductor integrated logic circuit 101 having a mode switching means capable of shutting off a power supply and having a response function according to the present invention, and its circuit operation. In order to observe the mode transition between the active mode and the sleep mode when the sleep mode operation is executed intermittently, the mode switching means PSW1 to PSW6 and the mode switching means PS
The power supply method of the semiconductor integrated logic circuit for propagating the mode transition detection signal in a chain between the mode switching means of W1 to PSW6 has been described.

Therefore, another mode switching means capable of supplying and shutting off power and adding a function of a response circuit for controlling and observing a mode transition between the active mode and the sleep mode will be described below. I do.

FIG. 6A is a circuit diagram of a mode switching means PSW7 capable of shutting off power and having a response function according to the second embodiment of the present invention, and FIG. 7 is a truth table of a transistor logic circuit with mode switching means LGC7 including means PSW7 and transistor logic circuit FNC2 receiving power supply from mode switching means.

It should be noted that in the truth table of FIG.
Indicates an undefined state in which the input value is not determined, and "Z" indicates that the output is in a high impedance state.

In this embodiment, a p-channel MOS transistor having a high threshold voltage and an n-channel M
This is an example in which an OS transistor is used.

First, the mode switching means PSW7 includes p-channel MOS transistors TSPR1 to TSPR connected in series.
An n-input NOR composed of SPRn (where n is an arbitrary natural number) and high-threshold n-channel MOS transistors TSNR1 to TSNRn connected in parallel to the drain side in which p-channel MOS transistors are connected in series
It is a gate circuit. Transistors TSPR1 to TSPR
n and the gate electrodes of the transistors TSNR1 to TSNRn are connected in common, and the sleep mode switching inversion signal SINB
1 to SINBn are input, and the transistors TSBR1 to TSBRn and the transistor TSPR
Each of the drain electrodes 1 to TSPRn can serve as a high-potential-side power supply terminal for the transistor logic circuit FNC2 and also serve as an output terminal for the sleep mode response signal SOT.

As shown in FIG. 6 (b), when any one of the sleep mode switching signals SINB1 to SINBn goes high, the sleep mode response signal SOT goes low, and the NOR gate circuit goes to sleep mode switching. When all the inputs of the inverted signals SINB1 to SINBn become Low level, the output of the sleep mode response signal SOT becomes High level.

Incidentally, the transistor logic circuit FNC2
Is connected to the high-potential-side power supply VD2
And data signals A1 to Ai (where i is an arbitrary natural number) as input signals and data signals Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Furthermore, transistors TSNR1 to TSN connected in common
Each source electrode of Rn is a power supply terminal for the low-potential power supply VS at one end of the mode switching means PSW7, and the source electrodes of the transistors TSPR1 to TSPRn are power supply terminals for the high-potential power supply VD1 at the other end of the mode switching means PSW7. Supply terminal.

Here, the current drivability in the conductive state of the p-channel MOS transistors TSPR1 to TSPRn is determined in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2, the basic operating frequency of the transistor logic circuit FNC2, and the signal transition probability. To set the required current drive capability. Also, n-channel type MO
The amount of leakage current in the cutoff state of the S transistors TSNR1 to TSNRn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current driving capability of the p-channel MOS transistors TSPR1 to TSPRn in the conductive state is such that the gate width is larger than the sum of the gate widths of the p-channel MOS transistors forming the transistor logic circuit FNC2. TSNR1
ＴＳTSNRn is secured by giving the sum of the gate widths. Also, an n-channel MOS transistor TSN
The threshold voltage of the n-channel MOS transistors TSNR1 to TSNRn is increased or the gate length is set such that the leakage current amount in the cutoff state of R1 to TSNRn is smaller than the sub-threshold leakage current of the transistor logic circuit FNC2. Or by making the gate insulating film thicker.

In the configuration of the transistor logic circuit LGC7 with mode switching means including the mode switching means PSW7 as described above, first, the circuit operation of the PSW7 will be described with reference to FIGS.
The operation of the PSW 7 when changing from the active mode to the sleep mode will be described with reference to FIG.

Sleep mode switching inversion signals SINB1 to SINB1
If at least one input of SINBn is in a High level state, at least one p-channel MOS transistor TSP constituting the mode switching means PSW7
R1 to TSPRn enter a cutoff state and at least one
N-channel MOS transistors TSNR1 to TSNR
NRn becomes conductive, and the transistor logic circuit FN
The supply of the high-potential-side power supply VS to C2 is stopped, and the supply of the low-potential-side power supply VD1 is started, so that a low-level sleep mode response signal SOT is output. As a result, the operation of the transistor logic circuit LGC7 having the power cutoff function as a logic circuit is stopped.

Next, the operation of the PSW 7 when changing from the sleep mode to the active mode will be described.

Sleep mode switching inversion signals SINB1 to SINB1
If all the inputs of SINBn are at the low level, all of the p-channel MOS transistors TSPR1 to TSPRn constituting the mode switching means PSW7 become conductive and the n-channel MO
All the S transistors TSNR1 to TSNRn are turned off, and the transistor logic circuit F
The supply of the low-potential-side power supply VS to the NC2 is stopped and the supply of the high-potential-side power supply VD1 is started, and the high-level sleep mode response signal SOT is output. As a result,
The transistor logic circuit LGC7 having the power cutoff function is in a state where a logic operation as a normal logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is simply executed, the inverter circuit is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. In particular, when transitioning from the sleep mode to the active mode, all the logic circuits including the mode switching means PSW1 to PSW6 with the power shutoff function are completely After confirming that the power supply has been restored to a state where power can be supplied, normal logic operation as active mode can be started, so that stable active mode and sleep mode operation can be performed without causing malfunction. can do.

FIG. 7A is a circuit diagram of a mode switching means PSW7 capable of shutting off the power supply and having a response function according to the second embodiment of the present invention, and FIG. 7 is a truth table of a transistor logic circuit with mode switching means LGC7 including a transistor logic circuit FNC2 that receives power supply from the means PSW7 and the mode switching means PSW7.

This embodiment is an example in which a NOR gate circuit composed of a low threshold p-channel MOS transistor and a high threshold n-channel MOS transistor is used as the mode switching means.

First, the mode switching means PSW7 includes p-channel MOS transistors TSPR1 to TSPR1 connected in series.
SPRn (where n is an arbitrary natural number) and n-channel MOS transistor TSN connected in parallel to p-channel MOS transistors TSPR1 to TSPRn
This is an n-input NOR gate circuit composed of R1 to TSNRn. The gate electrodes of the transistors TSPR1 to TSPRn and the transistors TSNR1 to TSNRn are connected in common, and the sleep mode switching inversion signals SINB1 to SINB1
NBn is input, and the transistors T connected in common are
Each source electrode of SPR1 to TSPRn is a power supply terminal to the high potential side power supply terminal VD1 at one end of the mode switching means PSW7, and the transistors TSNR1 to TSNRn
Are the power supply terminals for the low-potential-side power supply VS at the other end of the mode switching means PSW7. Further, the drain electrodes of the transistors TSPR1 to TSPRn and the transistors TSNR1 to TSNRn which are connected in common serve as a low threshold side power supply terminal to the transistor logic circuit FNC2.

As shown in FIG. 7B, the NOR gate circuit comprises sleep mode switching inversion signals SINB1 to SINB.
When any one of the inputs n goes to a high level, the sleep mode response signal SOT goes to a low level, and when all the inputs of the sleep mode switching inversion signals SINB1 to SINBn go to a low level, the output of the sleep mode response signal SOT becomes low. High level.

By the way, the high-potential-side power supply terminal VD2 is supplied to one of the high-potential-side power supply terminals of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the high-potential-side power supply VD2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, the current driving capability of the n-channel MOS transistors TSNR1 to TSNRn in the conductive state is determined in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2, the basic operating frequency of the transistor logic circuit FNC2 and the signal transition probability. To set the required current drive capability. Also, n-channel type MO
The amount of leakage current in the cutoff state of the S transistors TSNR1 to TSNRn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current driving capability of the n-channel MOS transistors TSNR1 to TSNRn in the conductive state is such that the gate width is larger than the sum of the gate widths of the n-channel MOS transistors constituting the transistor logic circuit FNC2. TSNR1
ＴＳTSNRn is secured by giving the sum of the gate widths. Also, an n-channel MOS transistor TSN
The threshold voltage of the n-channel MOS transistors TSNR1 to TSNRn is increased or the gate length is set such that the leakage current amount in the cutoff state of R1 to TSNRn is smaller than the sub-threshold leakage current of the transistor logic circuit FNC2. Or by making the gate insulating film thicker.

In the configuration of the transistor logic circuit LGC7 with mode switching means including the mode switching means PSW7 as described above, the circuit operation of the PSW7 will be described with reference to FIGS.
The operation of the PSW 7 when the mode is changed from the active mode to the sleep mode will be described with reference to FIG.

Sleep mode switching inversion signals SINB1 to SINB1
If at least one input of SINBn is in a High level state, p constituting the mode switching means PSW7
Channel type MOS transistors TSPR1 to TSPRn
Is turned off, and n-channel type MOS transistors TSNR1 to TSN
At least one transistor of Rn is turned on, and the high-potential-side power supply VD is supplied to the transistor logic circuit FNC2.
1 is stopped, and a low-level sleep mode response signal SOT is output. As a result, the logic operation of the transistor logic circuit LGC7 having the power cutoff function as a normal logic circuit is stopped.

Next, the operation of the PSW 7 when changing from the sleep mode to the active mode will be described.

Sleep mode switching inversion signals SINB1 to SINB1
If all the signals of SINBn are at the low level, all the p-channel MOS transistors TSPR1 to TSPRn constituting the mode switching means PSW7 are turned on and all the n-channel MOS transistors TSNR1 to TSNRn are turned off. As a result, the supply of the high-potential-side power supply VD1 to the transistor logic circuit FNC2 starts, and the high-level sleep mode response signal SOT is output. As a result, the transistor logic circuit LGC7 with the power cutoff function is in a state where a logic operation as a logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the low threshold value is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. , A NOR gate circuit comprising a p-channel type MOS transistor and a high threshold n-channel type MOS transistor. Mode switching means PS with power cutoff function
After confirming that all the transistor logic circuits provided with W7 have completely returned to a state where they can be completely supplied with power, the normal logic operation as the active mode can be started. The operation as a stable active mode can be executed without causing the problem.

FIG. 8A is a circuit diagram of a mode switching means PSW8 capable of shutting off the power supply and having a response function according to the third embodiment of the present invention, and FIG. 7 is a truth table of a transistor logic circuit with mode switching means LGC8 including a transistor logic circuit FNC2 that receives power supply from the means PSW8 and the mode switching means PSW8.

This embodiment is an example in which a NAND gate circuit composed of a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor is used as the mode switching means.

First, the mode switching means PSW8 includes p-channel MOS transistors TSPD1 to TSPD1 connected in parallel.
SPDn (where n is an arbitrary natural number) and n-channel MOS transistor TSN connected in series to p-channel MOS transistors TSPD1 to TSPDn
This is an n-input NAND gate circuit composed of D1 to TSNDn. The gate electrodes of the transistors TSPD1 to TSPDn and the transistors TSND1 to TSNDn are commonly connected, and the sleep mode switching signals SIN1 to SINn are connected.
Is input, and the transistor TSPD connected in common is
1 to TSPDn are connected to the mode switching means PSW.
8 is a power supply terminal to the high-potential-side power supply terminal VD of each of the transistors TSND1 to TSNDn.
Power supply terminal to the Further, the transistors TSPD1 to TSPDn and the transistor TSND which are connected in common are connected.
The drain electrodes of 1 to TSNDn serve as high-potential-side power supply terminals for the transistor logic circuit FNC2.

As shown in FIG. 8 (b), when any one of the sleep mode switching signals SIN1 to SINn goes to a low level, the sleep mode response signal SOTB goes to a high level and the sleep mode switching signal All inputs of SIN1 to SINn are HIg
When the level becomes the h level, the output of the sleep mode response signal SOTB becomes the low level.

By the way, the low-potential-side power supply VS2 is supplied to one of the low-potential-side power supply terminals of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the low-potential-side power supply VS2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, the current drivability of the p-channel MOS transistors TSPD1 to TSPDn in the conductive state is determined in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2, the basic operating frequency of the transistor logic circuit FNC2 and the signal transition probability. To set the required current drive capability. Also p-channel type MO
The amount of leakage current in the cutoff state of S transistors TSPD1 to TSPDn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including transistor logic circuit FNC2 in the sleep mode.

For example, the current drivability of the p-channel MOS transistors TSPD1 to TSPDn in the conductive state is such that the gate width of the p-channel MOS transistor TSPD1 is larger than the sum of the p-channel transistors constituting the transistor logic circuit FNC2. ~ TS
This is ensured by giving the sum of the gate widths of PDn. Also, p-channel MOS transistors TSPD1 to TSPD1
The amount of leakage current in the cut-off state of TSPDn is smaller than the sub-threshold leakage current of transistor logic circuit FNC2, so that the p-channel type MO
It is ensured by increasing the threshold voltage of the S transistors TSPD1 to TSPDn, increasing the gate length, or increasing the thickness of the gate insulating film.

In the configuration of the transistor logic circuit LGC8 with mode switching means including the mode switching means PSW8 as described above, when the mode is changed from the active mode to the sleep mode with reference to FIGS. 8 (a) and 8 (b). P
The operation of SW8 will be described.

Sleep mode switching signals SIN1 to SIN
If all inputs of n are in a high level state,
All the p-channel MOS transistors TSPD1 to TSPDn constituting the mode switching means PSW8 are turned off, and all the n-channel MOS transistors TSND1 to TSNDn are turned on, so that the high potential side power supply VD is supplied to the transistor logic circuit FNC2. Is stopped and the low-level sleep mode response signal S
OTB is output. As a result, the operation of the transistor logic circuit LGC8 having the power cutoff function as a logic circuit is stopped.

Next, the operation of the PSW 8 when changing from the sleep mode to the active mode will be described.

Sleep mode switching signals SIN1 to SIN
If at least one input of n is in the Low level state, at least one of the p-channel MOS transistors TSPD1 to TSPDn constituting the mode switching means PSW8 is turned on and the n-channel MOS transistors TSND1 to TSNDn are turned on. At least one transistor is turned off, supply of the high-potential-side power supply VD1 to the transistor logic circuit FNC2 starts, and a high-level sleep mode response signal SOTB is output. As a result, the transistor logic circuit LGC8 having the power cutoff function is in a state where a logic operation as a normal logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the high threshold value is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. The NAND gate circuit comprising a p-channel MOS transistor and a low-threshold n-channel MOS transistor has the above-described series of chained circuit operations, particularly when transitioning from the sleep mode to the active mode. Mode switching means P with power cutoff function
After confirming that all the transistor logic circuits provided with SW8 have completely returned to a state in which power can be completely supplied, normal logic operation in the active mode can be started. The operation as a stable active mode can be executed without causing the problem.

FIG. 9A is a circuit diagram of a mode switching means PSW9 capable of shutting off the power supply and having a response function according to the fourth embodiment of the present invention, and FIG. 7 is a truth table of a transistor logic circuit with mode switching means LGC9 including a transistor logic circuit FNC2 receiving power supply from the means PSW9 and the mode switching means PSW9.

This embodiment is an example in which a NAND gate circuit composed of a low threshold p-channel MOS transistor and a high threshold n-channel MOS transistor is used as the mode switching means.

First, the mode switching means PSW9 comprises p-channel type MOS transistors TSPA1 to TSPA1 connected in parallel.
SPAn (where n is an arbitrary natural number) and an n-channel MOS transistor TSN connected in series to p-channel MOS transistors TSPAl to TSPAn
This is an n-input NAND gate circuit composed of A1 to TSNAn. The gate electrodes of the transistors TSPA1 to TSPAn and the transistors TSNA1 to TSNAn are connected in common, and the sleep mode switching inversion signals SINB1 to SINB1
INBn is input, and each of the source electrodes of the commonly connected transistors TSPAl to TSPAn is a power supply terminal to the high potential side power supply terminal VD1 at one end of the mode switching means PSW9, and the transistors TSNA1 to TSNA
Each of the n source electrodes serves as a power supply terminal to the low potential side power supply VS at the other end of the mode switching means PSW9. Further, the drain electrodes of the transistors TSPA1 to TSPAn and the transistors TSNA1 to TSNAn which are connected in common serve as a low-potential-side power supply terminal for the transistor logic circuit FNC2.

As shown in FIG. 9B, the NAND gate circuit comprises sleep mode switching inversion signals SINB1-SIN.
When all the inputs of Bn go high, the sleep mode response signal SOT goes low, and when any one of the sleep mode switching inversion signals SINB1 to SINBn goes low, the output of the sleep mode response signal SOT goes low. High level is reached.

By the way, the high-potential power supply VD2 is supplied to one high-potential power supply terminal of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the high-potential-side power supply VD2 does not relate to the cutoff / conduction of the power supply in the present embodiment.

Here, an n-channel MOS transistor T
The necessary current driving capability in the conductive state of SNA1 to TSNAn is set in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2 and the basic operating frequency and signal transition probability of the transistor logic circuit FNC2. N-channel MOS
The amount of leakage current in the cut-off state of the transistors TSNA1 to TSNAn is set in consideration of the current consumption of the entire semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current driving capability of the n-channel MOS transistors TSNA1 to TSNAn in the conductive state is such that the gate width is larger than the sum of the gate widths of the n-channel MOS transistors forming the transistor logic circuit FNC2. TSNA1
ＴＳTSNAn is secured by giving the sum of the gate widths. Also, an n-channel MOS transistor TSN
The threshold voltage of the n-channel MOS transistors TSNA1 to TSNAn is increased or the gate length is set so that the leakage current in the cutoff state of A1 to TSNAn is smaller than the subthreshold leakage current of the transistor logic circuit FNC2. Or by making the gate insulating film thicker.

In the above configuration of the transistor logic circuit LGC9 with mode switching means including the mode switching means PSW9, when the mode is changed from the active mode to the sleep mode with reference to FIGS. 9A and 9B. P
The operation of SW9 will be described.

Sleep mode switching inversion signals SINB1 to SINB1
If all the signals of SINBn are in the High level state, all the signals p constituting the mode switching means PSW9
Channel type MOS transistors TSPA1 to TSPAn
Is turned off and all the n-channel MOS transistors TSNA1 to TSNAn are turned on, and the high-potential-side power supply VD is supplied to the transistor logic circuit FNC2.
1 starts, and the low-level sleep mode response signal SOT is output. As a result, the logic operation of the transistor logic circuit LGC9 having the power cutoff function as the logic circuit stops.

Next, the operation of the PSW 9 when changing from the sleep mode to the active mode will be described.

The sleep mode switching inversion signals SINB1 to SINB1
If at least one input of SINBn is in a low level state, at least one of the p-channel MOS transistors TSPA1 to TSPAn constituting the mode switching means PSW9 becomes conductive and the n-channel MOS transistors TSNA1 to TSNA
n is turned off, and the high-side power supply VD is supplied to the transistor logic circuit FNC2.
1 starts, and a high-level sleep mode response signal SOT is output. As a result, the transistor logic circuit LGC9 having the power cutoff function is in a state where a logic operation as a normal logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the low threshold is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. , The NAND gate circuit including the p-channel MOS transistor and the n-channel MOS transistor having a high threshold value. After confirming that all the transistor logic circuits including the mode switching means PSW9 with the power cutoff function have completely returned to a state where power can be completely supplied, the normal logic operation as the active mode is performed. Can be started without causing malfunction It is possible to the active mode operation.

FIG. 10A is a circuit diagram of a mode switching means PSW10 capable of shutting off a power supply and having a response function according to a fifth embodiment of the present invention, and FIG. Transistor logic circuit with mode switching means LGC10 including transistor logic circuit FNC2 receiving power supply from observation PSW10 and mode switching means PSW10
Is a truth table.

This embodiment is an example in which a NOR gate circuit composed of a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor is used as the mode switching means PSW10. First, the mode transition observation PSW
Reference numeral 10 denotes serially connected p-channel MOS transistors TSPO1 to TSPOn (where n is an arbitrary natural number) and p-channel MOS transistors TSPO
An n-input NOR gate circuit comprising n-channel MOS transistors TSNO1 to TSNOn connected in parallel to 1 to TSPOn. Transistors TSPO1-T
SPOn and the gate electrodes of the transistors TSNO1 to TSNOn are commonly connected, and the sleep mode switching signal SIN
1 to SINn are input, and the source electrodes of the commonly connected transistors TSPO1 to TSPOn are power supply terminals to the high potential side power supply terminal VD at one end of the mode switching means PSW10, and the transistors TSNO1 to TSNO1
Each source electrode of NOn becomes a low-potential-side power supply terminal at the other end of the mode switching means PSW10. Further, the drain electrodes of the transistors TSPO1 to TSPOn and the transistors TSNO1 to TSNOn which are connected in common serve as a low-potential-side power supply terminal for the transistor logic circuit FNC2.

As shown in FIG. 10 (b), when all the inputs of the sleep mode switching signals SIN1 to SINn go to the low level, the sleep mode response signal SOTB goes to the high level, and the sleep mode switching signal SIN1 To SINn become High level, the sleep mode response signal SO
The output of TB becomes Low level.

By the way, the low-potential-side power supply VS2 is supplied to one of the low-potential-side power supply terminals of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the low-potential-side power supply VS2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, a p-channel MOS transistor T
The current driving capability in the conductive state of SPO1 to TSPOn sets a necessary current driving capability in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2 and the basic operating frequency and signal transition probability of the transistor logic circuit FNC2. Also p-channel MOS
The amount of leakage current in the cutoff state of the transistors TSPO1 to TSPOn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current drivability of the p-channel MOS transistors TSPO1 to TSPon in the conductive state is such that the gate width of the p-channel MOS transistors TSPO1 to TSPon is larger than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC2. It is ensured by giving the sum of the gate widths. Also, the threshold voltage of p-channel MOS transistors TSPO1-TSPOn is set so that the leakage current in the cutoff state of p-channel MOS transistors TSPO1-TSPOn is smaller than the sub-threshold leakage current of transistor logic circuit FNC2. It is ensured by increasing the height, increasing the gate length, or increasing the thickness of the gate insulating film.

Transistor logic circuit LGC1 with mode switching means including mode switching means PSW10 as described above
The operation of the PSW 10 when the mode is changed from the active mode to the sleep mode in the configuration of 0 will be described with reference to FIGS. 10 (a) and 10 (b).

Sleep mode switching signals SIN1 to SIN
If at least one input of n is at a high level, at least one of the p-channel MOS transistors TSPO1 to TSPOn constituting the mode switching means PSW10 is turned off and the n-channel MOS transistors TSNO1 to TSNOn are turned off. At least one transistor is turned on, supply of the high-potential-side power supply VD to the transistor logic circuit FNC2 is stopped, and a low-level sleep mode response signal SOTB is output. As a result, the logic operation of the transistor logic circuit LGC10 having the power cutoff function as a normal logic circuit is stopped.

Next, the operation of the PSW 10 when changing from the sleep mode to the active mode will be described.

Sleep mode switching signals SIN1 to SIN
If all inputs of n are in the Low level state, all the p-channel MOS transistors TSPO1 to TSPOn constituting the mode switching means PSW10 are turned on and all the n-channel MOS transistors TSNO1 to TSNOn are turned off. As a result, supply of the high-potential-side power supply VD to the transistor logic circuit FNC2 starts, and a high-level sleep mode response signal SOTB is output. As a result, the transistor logic circuit LGC11 with the power cutoff function is in a state where logic operation as a logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the high threshold value is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. Of the p-channel type MOS transistor and the n-channel type MOS transistor having a low threshold value, the above-mentioned series of chained circuit operations as a result particularly at the time of transition from the sleep mode to the active mode. Mode switching means PS with power cutoff function
After confirming that all the transistor logic circuits provided with W10 have completely returned to a state where they can be completely supplied with power, a normal logic operation in the active mode can be started, so that a malfunction occurs. , And a stable active mode operation can be performed.

FIG. 11A is a circuit diagram of a mode switching means PSW11 capable of shutting off a power supply and having a response function according to a sixth embodiment of the present invention, and FIG. Logic circuit LGC1 with mode switching means including means PSW11 and transistor logic circuit FNC2 supplied with power by mode switching means PSW11
1 is a truth table.

In this embodiment, the mode switching means PSW11 comprises a NAND circuit comprising a low threshold p-channel MOS transistor and a high threshold n-channel MOS transistor.
This is an example in which a gate circuit and an inverter circuit including a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor are used.

First, the mode switching means PSW11 includes p-channel MOS transistors TSPR1 to TSPR1 connected in series.
TSPRn (where n is any natural number) and p
Channel type MOS transistors TSPR1 to TSPRn
Channel type MOS transistor TS connected in series
An n-input NAND gate circuit composed of NR1 to TSNRn and a p-channel MOS transistor TBPR1
To TBPRn and n-channel MOS transistor TBN
Inverter circuits INV1 to R1 to TBNRn
INVn, and the transistor TSP
R1 to TSPRn and transistors TSNR1 to TSNR
n are connected in common to receive sleep mode switching inversion signals SINB1 to SINBn, and the drain electrodes of the commonly connected transistors TSPR1 to TSPRn and TSNR1 to TSNRn are connected to the low potential side power supply to the transistor logic circuit FNC2. Supply terminals and sleep mode response signals SOTB1 to SOT
Also serves as an output terminal for Bm.

Further, transistors TSPR1 to TSPR
Rn and the outputs of the transistors TSNR1 to TSNRn are connected to the gate electrode input of the inverter circuit. The inverter circuits are connected in parallel to each other, and also serve as output terminals for sleep mode switching signals SOTB1 to SOTBm.

By the way, the high-potential power supply VD2 is supplied to one high-potential power supply terminal of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the high-potential-side power supply VD2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, a p-channel MOS transistor T
The current driving capability in the conductive state of SPR1 to TSPRn sets a necessary current driving capability in consideration of the device parameters of the transistors included in the transistor logic circuit FNC2 and the basic operating frequency and signal transition probability of the transistor logic circuit FNC2. Also p-channel MOS
The amount of leakage current in the cut-off state of the transistors TSPR1 to TSPRn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current driving capability of the n-channel MOS transistors TSNR1 to TSNRn in the conductive state is such that the gate width of the n-channel MOS transistors TSNR1 to TSNRn is larger than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC2. It is ensured by giving the sum of the gate widths. The threshold voltage of the n-channel MOS transistors TSNR1 to TSNRn is set so that the leakage current in the cutoff state of the n-channel MOS transistors TSNR1 to TSNRn is smaller than the sub-threshold leakage current of the transistor logic circuit FNC2. It is ensured by increasing the height, increasing the gate length, or increasing the thickness of the gate insulating film.

Transistor logic circuit LGC1 with mode switching means including mode switching means PSW11 as described above
The operation of the PSW 11 when the mode is changed from the active mode to the sleep mode in the configuration of FIG. 11 will be described with reference to FIGS. If at least one input of the sleep mode switching inversion signals SINB1 to SINBn is in the High level state, at least one of the p-channel MOS transistors TSPR1 to TSPRn constituting the mode switching means PSW11 is turned off and the n-channel is turned off. At least one of the MOS transistors TSNR1 to TSNRn is turned on, and the transistor logic circuit F
The supply of the high-potential-side power supply VD1 to the NC2 is stopped and the inverter circuit inverts the high-level power supply VD1 to output the high-level sleep mode response signals SOTB1 to SOTBm. As a result, the logic operation of the transistor logic circuit LGC11 with the power cutoff function as a normal logic circuit is stopped.

Next, the operation of the PSW 11 when changing from the sleep mode to the active mode will be described.

The sleep mode switching inversion signals SINB1 to SINB1
If all the inputs of SINBn are in the low level state, all the ps constituting the mode switching means PSW11
Channel type MOS transistors TSPR1 to TSPRn
Is turned on, all the n-channel MOS transistors TSNR1 to TSNRn are turned off, and the high potential side power supply VD is supplied to the transistor logic circuit FNC2.
1 starts to be supplied and the inverter circuit inverts the low-level sleep mode response signal SOTB1
To SOTBm are output. As a result, the transistor logic circuit LGC11 with the power cutoff function is in a state where it can operate as a logic circuit.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the low threshold is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. , A NAND gate circuit composed of a p-channel MOS transistor and a high threshold n-channel MOS transistor, and an inverter circuit composed of a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor. Therefore, all the transistor logic circuits including the mode switching means PSW11 with the power cutoff function can be completely supplied with power as a result of the above-described series of chained circuit operations, particularly when transitioning from the sleep mode to the active mode. After confirming that it has completely returned to the state , In order to be able to start a normal logical operation of the active mode, without causing a malfunction, it is possible to stably active mode operation was.

FIG. 12A is a circuit diagram of a mode switching means PSW12 capable of shutting off the power supply and having a response function according to the seventh embodiment of the present invention, and FIG. Logic circuit LGC12 with mode switching means including means PSW12 and transistor logic circuit FNC2 receiving power supply from mode switching means PSW12
Is a truth table.

In this embodiment, the mode switching means PSW12 includes a NAND circuit comprising a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor.
This is an example in which an inverter circuit including a gate circuit, a low threshold p-channel MOS transistor, and a high threshold n-channel MOS transistor is used.

First, the mode switching means PSW12 includes p-channel MOS transistors TSPD1 to TSPD1 connected in parallel.
TSPDn (where n is any natural number) and p
Channel type MOS transistors TSPD1 to TSPDn
Channel type MOS transistor TS connected in series
An n-input NAND gate circuit composed of ND1 to TSNDn, and a p-channel MOS transistor TBPD1
To TBPDn and n-channel MOS transistor TBN
D1 to TBNDn, and the gate electrodes of the transistors TSPD1 to TSPDn and the transistors TSND1 to TSNDn are commonly connected to receive the sleep mode switching signals SIN1 to SINn.
To TSPDn and the drain electrodes of the transistors TSND1 to TSNDn serve as high-potential-side power supply terminals for the transistor logic circuit FNC2 and output terminals for the sleep mode response signals SOT1 to SOTm.

Further, transistors TSPD1 to TSPD1
Dn and the outputs of TSND1 to TSNDn are connected to the gate electrode input of the inverter circuit. The inverter circuits are connected in parallel with each other, and a sleep mode response signal SOT1 is provided.
To SOTm.

By the way, the low-potential-side power supply VS2 is supplied to one of the low-potential-side power supply terminals of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the low-potential-side power supply VS2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, a p-channel MOS transistor T
The current driving capability in the conductive state of SPD1 to TSPDn sets a necessary current driving capability in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2 and the basic operation frequency and signal transition probability of the transistor logic circuit FNC2. Also p-channel MOS
The amount of leakage current in the cut-off state of the transistors TSPD1 to TSPDn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current drivability of the p-channel MOS transistors TSPD1 to TSPDn in the conductive state is such that the gate width of the p-channel MOS transistors TSPD1 to TSPDn is larger than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC2. It is ensured by giving the sum of the gate widths. The threshold voltage of p-channel MOS transistors TSPD1 to TSPDn is set such that the leakage current in the cutoff state of p-channel MOS transistors TSPD1 to TSPDn is smaller than the sub-threshold leakage current of transistor logic circuit FNC2. It is ensured by increasing the height, increasing the gate length, or increasing the thickness of the gate insulating film.

Transistor logic circuit LGC1 with mode switching means including mode switching means PSW12 as described above
The operation of the PSW 12 when the mode is changed from the active mode to the sleep mode in the configuration 2 will be described with reference to FIGS.

Sleep mode switching signals SIN1 to SIN
If all inputs of n are in a high level state,
P-channel type MO constituting mode switching means PSW12
All of the S transistors TSPD1 to TSPDn are turned off, and all of the n-channel MOS transistors TSND1 to TSNDn are turned on, so that the transistor logic circuit FNC
2, the supply of the high-potential-side power supply VD is stopped, and at the same time, the high-level sleep mode response signals SOT1 to SOTm are inverted by the inverter circuit and output. As a result, the transistor logic circuit LGC1 having the power cutoff function is provided.
The logic operation of the normal logic circuit 2 is stopped.

Next, the operation of PSW 12 when the mode is changed from the sleep mode to the active mode will be described.

Sleep mode switching signals SIN1 to SIN
If at least one input of n is in a low level state, all the ps constituting the mode switching means PSW12
Channel type MOS transistors TSPD1 to TSPDn
Is turned on, all the n-channel MOS transistors TSNA1 to TSNAn are turned off, and the high potential side power supply VD is supplied to the transistor logic circuit FNC2.
Of the sleep mode response signals SOT <b> 1 -S
OTm is output. As a result, the transistor logic circuit LGC12 with the power cutoff function is in a state where a logic operation as a logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the high threshold value is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. And a inverter circuit composed of a low threshold p-channel MOS transistor and a high threshold n-channel MOS transistor, and a NAND gate circuit composed of a p-channel MOS transistor and a low threshold n-channel MOS transistor. In particular, when transitioning from the sleep mode to the active mode, as a result of the above series of chained circuit operations, all transistor logic circuits including the mode switching means with a power cutoff function can be completely supplied with power. After confirming that it has completely returned, In order to be able to start the normal logic operation as a mode without causing a malfunction, it is possible to stably active mode operation was.

FIG. 13A is a circuit diagram of a mode switching means PSW13 capable of shutting off the power supply and having a response function according to the eighth embodiment of the present invention, and FIG. 7 is a truth table of a transistor logic circuit with mode switching means LGC13 including means PSW13 and a transistor logic circuit FNC2 receiving power supply from the mode switching means.

In this embodiment, the mode switching means PSW13 includes a NAND circuit comprising a low threshold p-channel MOS transistor and a high threshold n-channel MOS transistor.
This is an example in which a gate circuit and an inverter circuit including a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor are used.

First, the mode switching means PSW13 includes p-channel MOS transistors TSPA1 to TSPA1 connected in parallel.
TSPAn (where n is any natural number) and p
An n-input NAND gate circuit composed of n-channel MOS transistors TSNA1 to TSNAn connected in series to channel MOS transistors, and an inverter circuit composed of p-channel MOS transistors TBPA1 to TBPAn and n-channel MOS transistors TBNA1 to TBNAn And transistors TSPA1 to TSPAn and transistor TSNA1
To TSNn are commonly connected, sleep mode switching inversion signals SINB1 to SINBn are input, and commonly connected transistors TSPA1 to TSPAn are connected.
And the drain electrodes of the transistors TSNA1 to TSNAn serve as low-potential-side power supply terminals for the transistor logic circuit FNC2, and the sleep mode response signals SOTB1 to SOTB1
Also serves as an output terminal of OTBm.

The high-potential-side power supply terminal VD2 is supplied to one of the high-potential-side power supply terminals of the transistor logic circuit FNC2. The data signals A1 to Ai (where i is an arbitrary natural number) are input as data signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the high-potential-side power supply VD2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, n channel type MOS transistor T
The necessary current driving capability in the conductive state of SNA1 to TSNAn is set in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2 and the basic operating frequency and signal transition probability of the transistor logic circuit FNC2. N-channel MOS
The amount of leakage current in the cut-off state of the transistors TSNA1 to TSNAn is set in consideration of the current consumption of the entire semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current driving capability of the n-channel MOS transistors TSNA1 to TSNAn in the conductive state is such that the gate width of the n-channel MOS transistors TSNA1 to TSNAn is larger than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC2. It is ensured by giving the sum of the gate widths. The threshold voltage of the n-channel MOS transistors TSNA1 to TSNAn is set so that the leakage current in the cutoff state of the n-channel MOS transistors TSNA1 to TSNAn becomes smaller than the sub-threshold leakage current of the transistor logic circuit FNC2. It is ensured by increasing the height, increasing the gate length, or increasing the thickness of the gate insulating film.

Transistor logic circuit LGC1 with mode switching means including mode switching means PSW13 as described above
The operation of the PSW 13 when the mode is changed from the active mode to the sleep mode in the configuration of FIG. 3 will be described with reference to FIGS. 13 (a) and 13 (b).

The sleep mode switching inversion signals SINB1 to SINB1
If all the inputs of SINBn are in the High level state, at least one of the p-channel MOS transistors TSPA1 to TSPAn constituting the mode switching means PSW13 is turned off and at least one of the n-channel MOS transistors TSNA1 to TSNAn is turned off. One transistor is turned on, the supply of the high-potential-side power supply VD1 to the transistor logic circuit FNC2 is stopped, and the transistor logic circuit FNC2 is inverted by the inverter circuit to L.
ow level sleep mode response signals SOTB1 to SOTB
TBm is output. As a result, the logic operation of the transistor logic circuit LGC13 having the function of shutting off the power as a normal logic circuit is stopped.

Next, the operation of the PSW 13 when the mode is changed from the sleep mode to the active mode will be described.

Sleep mode switching inversion signals SINB1 to SINB1
If at least one input of SINBn is at a low level, at least one n-channel MOS transistor TSP forming the mode switching means PSW13
A1 to TSPAn become conductive and at least 1
N-channel MOS transistors TSNA1 to TSNA1
NAn is cut off, and the transistor logic circuit FN
When the supply of the high-potential-side power supply VD1 to C2 starts, the inverter circuit inverts the low-level sleep mode response signals SOTB1 to SOTBm. As a result, a transistor logic circuit LGC having a power shutoff function is provided.
Reference numeral 13 indicates a state in which operation as a logic circuit is possible.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the low threshold is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. And a inverter circuit composed of a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor, and a NAND gate circuit composed of a p-channel MOS transistor and a high threshold n-channel MOS transistor. In particular, when the transition from the sleep mode to the active mode occurs, as a result of the above series of chained circuit operations, all transistor logic circuits including the mode switching means PSW13 with a power cutoff function can be completely supplied with power. After confirming that it has completely returned to In order to be able to start the normal logic operation as an active mode, without causing a malfunction, it is possible to stably active mode operation was.

FIG. 14A is a circuit diagram of the mode switching means PSW14 capable of shutting off the power supply and having a response function according to the ninth embodiment of the present invention, and FIG. Logic circuit LGC14 with mode switching means including means PSW14 and transistor logic circuit FNC2 receiving power supply from mode switching means PSW14
Is a truth table.

In this embodiment, the mode switching means PSW14 includes a NOR gate circuit composed of a high threshold p-channel MOS transistor and a low threshold n-channel MOS transistor, a low threshold p-channel MOS transistor and a high threshold This is an example in which an inverter circuit including an n-channel MOS transistor is used.

First, the mode switching means PSW14 includes p-channel MOS transistors TSPO1 to TSPO1 connected in series.
TSPOn (where n is any natural number) and p
Channel type MOS transistors TSNO1 to TSNOn
-Channel MOS transistor TS connected in parallel to
An n-input NOR gate circuit composed of NO1 to TSNOn and a p-channel MOS transistor TBPO1
TBPOn and n-channel MOS transistor TBNO
1 to TBNOn, and the gate electrodes of the transistors TSPO1 to TSPOn and the transistors TSNO1 to TSNOn are commonly connected to form a sleep mode switching signal SIN1 to SINn.
, And the commonly connected transistors TSPO
1 to TSPOn and transistors TSNO1 to TSNOn
Are drain terminals of the sleep mode response signals SOT1 to SOTm as well as high-potential power supply terminals for the transistor logic circuit FNC2.

Incidentally, the low-potential-side power supply VS2 is supplied to one of the low-potential-side power supply terminals of the transistor logic circuit FNC2, and the data signals A1 to Ai (where i is an arbitrary natural number) are used as input signals. Y1 to Yj
(Where j is an arbitrary natural number) is set as an output signal.
Note that the low-potential-side power supply VS2 is not involved in the supply / cutoff of the power supply of the present embodiment.

Here, p-channel type MOS transistor T
The current driving capability in the conductive state of SPO1 to TSPOn sets a necessary current driving capability in consideration of the device parameters of the transistors constituting the transistor logic circuit FNC2 and the basic operating frequency and signal transition probability of the transistor logic circuit FNC2. Also p-channel MOS
The amount of leakage current in the cutoff state of the transistors TSPO1 to TSPOn is set in consideration of the entire current consumption of the semiconductor integrated logic circuit including the transistor logic circuit FNC2 in the sleep mode.

For example, the current drivability of the p-channel MOS transistors TSPO1 to TSPon in the conductive state is such that the gate width of the p-channel MOS transistors TSPO1 to TSPon is larger than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC2. It is ensured by giving the sum of the gate widths. Also, the threshold voltage of p-channel MOS transistors TSPO1-TSPOn is set so that the leakage current in the cutoff state of p-channel MOS transistors TSPO1-TSPOn is smaller than the sub-threshold leakage current of transistor logic circuit FNC2. It is ensured by increasing the height, increasing the gate length, or increasing the thickness of the gate insulating film.

Transistor logic circuit LGC1 with mode switching means including mode switching means PSW14 as described above
The operation of the PSW 14 when the mode is changed from the active mode to the sleep mode in the configuration of FIG. 4 will be described with reference to FIGS.

Sleep mode switching signals SIN1 to SIN
If at least one input of n is at a high level, at least one of the p-channel MOS transistors TSPO1 to TSPOn constituting the mode switching means PSW14 is turned off and the n-channel MOS transistors TSNO1 to TSNOn are turned off. At least one transistor becomes conductive, the supply of the high-potential-side power supply VD to the transistor logic circuit FNC2 stops, and the transistor logic circuit FNC2 is inverted by the inverter circuit to Hi.
gh level sleep mode response signals SOT1 to SOT
m is output. As a result, the logic operation of the transistor logic circuit LGC14 with the power cutoff function as a normal logic circuit is stopped.

Next, the operation of the PSW 14 when the mode is changed from the sleep mode to the active mode will be described.

Sleep mode switching signals SIN1 to SIN
If all the inputs of n are in the Low level state, all the p-channel MOS transistors TSPO1 to TSPOn constituting the mode switching means PSW14 are turned on, and all the n-channel MOS transistors TSNO1 to TSNOn are turned off. As a result, the supply of the high-potential-side power supply VD to the transistor logic circuit FNC2 starts and the inverter circuits invert the low-level sleep mode response signals SOT1 to SOTm. As a result, the transistor logic circuit LGC13 with the power cutoff function is in a state where it can operate as a logic circuit.

As described above, in this embodiment, when the sleep mode operation is intermittently executed, the high threshold is used as a means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. And an inverter circuit composed of a p-channel MOS transistor having a low threshold value and an n-channel MOS transistor having a high threshold value. In particular, when transitioning from the sleep mode to the active mode, as a result of the above series of chained circuit operations, all transistor logic circuits including the mode switching means with a power cutoff function can be completely supplied with power. After confirming that it has fully recovered, In order to be able to start the normal logic operation as over de, without causing a malfunction, it is possible to stably active mode operation was.

As shown in FIG. 15, this embodiment is an example in which the mode switching means shown in the second to ninth embodiments actually responds. Mode switching means PSW10a-1
6a and arbitrary transistor logic circuits FNC3 to FNC
9.

Referring to FIG. 15, in the present embodiment, a circuit group LG
C15 to LGC21, and LGC15 to LGC21.
The LGC 21 is a mode switching observation means PSW10 between an active mode in which power is supplied to each circuit and a sleep mode in which power is not supplied.
b to PSW 16b. PSW 10a-1
6a functions as a switch when the sleep mode switching signal SIN is input, and the mode switching means PSW10b-1
6b is turned ON / OFF and the transistor logic circuit FNC3
To shut off / supply power to FNC9.

The supply / interruption of power to each circuit is performed by the LGC as the sleep mode switching signal SIN flows through each circuit.
15 → LGC16 → LGC17 → LGC18 → LGC1
9 → LGC20 → LGC21 in this order.

FIG. 16 shows a semiconductor logic integrated circuit 102 having the mode switching means with a power cutoff response function shown in FIG.
FIG. 21 is a detailed system diagram of the tenth embodiment of FIG.

In FIG. 16, mode switching means PSW1
5 to PSW21 are all constituted by CMOS and are low threshold or high threshold CMOS transistors. Among them, TSNR1, TBPR1, PBPR2,
TSNR1, TBPR1, TSNR1, TBPR1, T
SNR1, TSNR2, TBPR2, TBPR1, TS
NR1, TBPR1, TSNR1, TSNR2, TBP
R1 is a p-channel type and n-channel type MOS transistor having a high threshold value, and TSPR1, TBNR1, PBNR
2, TBNR2, TSPR2, TBNR2 are low threshold P
These are channel-type and n-channel-type MOS transistors.

A low-threshold MOSFET can easily operate in a low-voltage state, so that high-speed operation can be performed in the active mode. A high-threshold MOSFET transistor has a characteristic of turning on / off a high voltage level. .

Next, 6 which is a central circuit element of the present invention.
The circuit configuration of the mode switching means PSW15 to PSW21 will be described below along the flow of the sleep mode switching signal SIN.

First, the mode switching means PSW15 includes a p-channel MOS transistor TSPR1 connected in series.
, N-channel MOS transistor TSNR1, p-channel MOS transistor TSPR1, n-channel MOS transistor TSNR1, p-channel MOS transistor
It comprises a transistor TBPR1 and an n-channel MOS transistor TBNR1. Among them, the transistor TSPR1 and the transistor TSNR1 are circuits that function as the mode switching means PSW15, and include the p-channel MOS transistor TBPR1, the n-channel MOS transistor TBNR1, and the p-channel MO transistor.
The S transistor TBPR2 and the n-channel MOS transistor TBNR2 are inverter circuits that invert the polarity of the signal.

The transistors TSPR1 and T
The gate electrodes of SNR1 are commonly connected, and a sleep mode switching signal SIN is input. Transistor TSP
The source electrode of R1 is a high-potential power supply terminal at one end of the mode switching means PSW15, and the source electrode of the transistor TSNR1 is a low-potential power supply terminal at the other end of the mode switching means PSW15. Further, the drain electrode to which the transistor TSPR1 and the transistor TSNR1 are commonly connected becomes the low-potential-side power supply terminal N9, and the logic circuit LGC
15 other components, ie, a transistor logic circuit FNC
Power is supplied to the low-potential side power supply terminal 3.

Here, the current drivability in the conductive state of p-channel MOS transistor TSPR1 is necessary in consideration of the device parameters of the transistors constituting transistor logic circuit FNC3 and the basic operating frequency and signal transition probability of transistor logic circuit FNC3. Set the appropriate current drive capability. Further, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability of the p-channel MOS transistor TSPR1 in the conducting state is determined by the p-channel MOS transistor TNC3 constituting the transistor logic circuit FNC3.
A gate width larger than the sum of the gate widths of the transistors is p
This is ensured by providing the channel type MOS transistor TSPR1. Whether the threshold voltage of the p-channel MOS transistor TSPR1 is increased so that the leakage current in the cut-off state of the p-channel MOS transistor TSPR1 is smaller than the sub-threshold leakage current of the transistor logic circuit FNC3. , By increasing the gate length or increasing the thickness of the gate insulating film.

The mode transition observation PSW 16 includes a p-channel MOS transistor TSPR 1 and an n-channel MOS transistor TSNR 1, a p-channel MOS transistor TBPR 1 and an n-channel MOS
And a transistor TBNR1, and are connected in parallel with each other. Among them, the transistor TSPR1 and the transistor TSNR1 are circuits that function as the mode switching means PSW16, and include the p-channel MOS transistor TBPR1 and the n-channel MOS transistor TB
NR1 is an inverter circuit for inverting the polarity of the signal.

The transistors TSPR1 and T
The gate electrodes of SNR1 are connected in common, and a sleep mode response signal from the gate electrodes of the preceding transistors TBPR1 and TBNR1 is input. The source electrode of transistor TSPR1 is connected to the mode switching means PS.
W16 is a high-potential-side power supply terminal at one end, and the source electrode of the transistor TSNR1 is a low-potential-side power supply terminal at the other end of the mode switching means PSW16.
The drain electrode to which the SPR1 and the transistor TSNR1 are commonly connected becomes a low-potential power supply terminal N14 to supply power to the low-potential power terminal of the transistor logic circuit FNC4, which is another component of the transistor logic circuit LGC16. .

Here, the current drivability in the conductive state of p-channel MOS transistor TSPR1 is necessary in consideration of the device parameters of the transistors constituting transistor logic circuit FNC4 and the basic operating frequency and signal transition probability of transistor logic circuit FNC4. Set the appropriate current drive capability. Further, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability of the p-channel MOS transistor TSPR1 in the conductive state is determined by the p-channel MOS transistor TNC4 constituting the transistor logic circuit FNC4.
A gate width larger than the sum of the gate widths of the transistors is p
This is ensured by providing the channel type MOS transistor TSPR1. Also, is the threshold voltage of the p-channel MOS transistor TSPR1 raised such that the leakage current in the cutoff state of the p-channel MOS transistor TSPR1 becomes smaller than the sub-threshold leakage current of the transistor logic circuit FNC4? , By increasing the gate length or increasing the thickness of the gate insulating film.

The mode switching means PSW17 includes a p-channel MOS transistor TSPR1, an n-channel MOS transistor TSNR1, a p-channel MOS transistor TBPR1, and an n-channel MOS transistor connected in series.
And a transistor TBNR1 and connected in parallel with each other. Among them, the transistor TSPR1
And the transistor TSNR1 are connected to the mode switching means PSW17.
A p-channel MOS transistor TBPR1 and an n-channel MOS transistor T
BNR1 is an inverter circuit for inverting the polarity of the signal.

The transistors TSPR1 and T
The gate electrodes of SNR1 are commonly connected to receive a response signal from the gate electrodes of the preceding transistors TBPR2 and TBNR2.
The source electrode of R1 is a high-potential power supply terminal at one end of the mode switching means PSW16, the source electrode of the transistor TSNR1 is a low-potential power supply terminal at the other end of the mode switching means PSW16, and each of the transistors TSPR1 and TSNR1 is The commonly connected drain electrode serves as the low-potential-side power supply terminal N15 to supply power to the low-potential-side power supply terminal of the transistor logic circuit FNC5, which is another component of the transistor logic circuit LGC16.

Here, the current drivability in the conductive state of p-channel MOS transistor TSPR1 is necessary in consideration of the device parameters of the transistors constituting transistor logic circuit FNC5 and the basic operating frequency and signal transition probability of transistor logic circuit FNC5. Set the appropriate current drive capability. Further, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drive capability of the p-channel MOS transistor TSPR1 in the conductive state is determined by the p-channel MOS transistor TNC5 constituting the transistor logic circuit FNC5.
A gate width larger than the sum of the gate widths of the transistors is p
This is ensured by providing the channel type MOS transistor TSPR1. Whether the threshold voltage of the p-channel MOS transistor TSPR1 is increased so that the leakage current in the cut-off state of the p-channel MOS transistor TSPR1 is smaller than the sub-threshold leakage current of the transistor logic circuit FNC5. , By increasing the gate length or increasing the thickness of the gate insulating film.

The mode switching means PSW18 includes p-channel MOS transistors TSPR1 and TSPR1 connected in series.
A NOR gate circuit N comprising PR2 and n-channel MOS transistors TSNR1 and TSNR2 connected in parallel to the gate electrodes of transistors TSPR1 and TSPR2.
OR1 and a p-channel MOS transistor TBPR connected to the drain electrode output of NOR gate circuit NOR1.
1 and an n-channel MOS transistor TDNR1, p
It comprises a channel type MOS transistor TRPR2 and an n-channel type MOS transistor TBNR2. Here, the NOR gate circuit NOR1 is a circuit that functions as the mode switching means PSW18, and is a p-channel type M
OS transistor TBPR1, n-channel MOS transistor TBNR1, p-channel MOS transistor TBPR2, and n-channel MOS transistor TBN
R2 is an inverter circuit for inverting the polarity of the signal.

The gate electrodes of the transistors TSPR1 and TSNR1 are connected in common, and the mode switching means PSW of the preceding stage is connected.
16 transistors TBPR1 and TBNR
1, a source electrode of the transistor TSPR1 is a high-potential power supply terminal at one end of the mode switching means PSW18, and a source electrode of the transistor TSNR1 is connected to the other end of the mode switching means PSW18. Of the low potential side power supply terminal. On the other hand, the transistor TSPR2 and the transistor TBNR2
Are commonly connected to each other and the mode switching means P
SW17 transistor TBPR1 and transistor TB
The sleep mode response signal is input from the gate electrode of NR1, the source electrode of the transistor TSPR2 is a high potential side power supply terminal at one end of the mode switching means PSW18, and the source electrode of the transistor TSNR2 is the other end of the mode switching means PSW18. Of the low potential side power supply terminal. Further, the drain electrode of the NOR gate NOR1 serves as a sleep mode response signal output terminal N16, and outputs a sleep mode response signal to the next-stage LGC 19 and LGC 20 via the inverter.

The current drivability of the p-channel MOS transistors TSPR1 and TSPR2 in the conductive state depends on the device parameters of the p-channel MOS transistors constituting the transistor logic circuit FNC6, the basic operating frequency of the transistor logic circuit FNC6 and the signal transition. The necessary current driving capability is set in consideration of the probability. Also, p-channel MOS transistors TSPR1 and TSPR1
The amount of leakage current in the cutoff state of PR2 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability in the conductive state of the p-channel MOS transistors TSPR1 and TSPR2 is determined from the sum of the gate widths of the transistors constituting the transistor logic circuit FNC6 in consideration of the basic operating frequency and the signal transition probability. The p-channel MOS transistors TSPR1 and TSPRR2 have a smaller gate width. Also, a p-channel MOS transistor TSPR
The threshold voltage of the p-channel MOS transistors TSPR1 and TSPR2 is increased or the gate length is set so that the amount of leakage current in the cut-off state of the transistors 1 and TSPR2 is smaller than the sub-threshold leakage current of the transistor logic circuit FNC6. Or by making the gate insulating film thicker.

For example, the current drivability in the conductive state of the p-channel MOS transistors TSPR1 and TSPR2 is determined from the sum of the gate widths of the transistors constituting the transistor logic circuit FNC6 in consideration of the basic operating frequency and the signal transition probability. The p-channel MOS transistors TSPR1 and TSPR2 have a smaller gate width. Also, a p-channel MOS transistor TSPR
The threshold voltage of the p-channel MOS transistors TSPR1 and TSPR2 is increased or the gate length is set so that the amount of leakage current in the cut-off state of TSPR1 and TSPR2 is smaller than the sub-threshold leakage current of the transistor logic circuit FNC6. Or by making the gate insulating film thicker.

The mode switching means PSW19 includes a p-channel MOS transistor TSPR1, an n-channel MOS transistor TSNR1, a p-channel MOS transistor TBPR1, and an n-channel MOS transistor connected in series.
And a transistor TBNR1, and are connected in parallel with each other. Among them, the transistor TSPR1 and the transistor TSNR1 are circuits that function as the mode switching means PSW19, and the p-channel MOS transistor TBPR1 and the n-channel MOS transistor TB
NR1 is an inverter circuit for inverting the polarity of the signal.

The transistors TSPR1 and T
The gate electrode of SNR1 is connected in common, and the sleep mode response signal output from the transistor TBPR1, the transistor TBNR1 and the gate electrode of the preceding mode switching means PSW18 is input.
One source electrode is a high-potential-side power supply terminal at one end of the mode switching means PSW19, and a source electrode of the transistor TSNR1 is a low-potential-side power supply terminal at the other end of the mode switching means PSW19. Further, the drain electrode to which the transistor TSPR1 and the transistor TSNR1 are commonly connected becomes a low-potential-side power supply terminal N17 to supply power to the low-potential-side power supply terminal of the transistor logic circuit FNC7, which is another component of the transistor logic circuit LGC19. Supply.

Here, the current drivability of the p-channel MOS transistor TSPR1 in the conductive state is determined by the p-channel MOS transistor TNC7 constituting the transistor logic circuit FNC7.
The necessary current drivability is set in consideration of the device parameters of the transistor and the basic operating frequency and signal transition probability of the transistor logic circuit FNC7. Further, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability of the p-channel MOS transistor TSPR1 in the conductive state is smaller than the sum of the gate widths of the transistors constituting the transistor logic circuit FNC7 in consideration of the basic operating frequency and the signal transition probability. The gate width is given to the p-channel MOS transistor TSPR1. In addition, p-channel type M
The amount of leakage current in the cut-off state of the OS transistor TSPR1 is smaller than the sub-threshold leakage current of the transistor logic circuit FNC7.
This is ensured by increasing the threshold voltage of the p-channel MOS transistor TSNR1, increasing the gate length, or increasing the thickness of the gate insulating film.

The mode switching means PSW20 includes a p-channel MOS transistor TSPR1, an n-channel MOS transistor TSNR1, a p-channel MOS transistor TBPR1, and an n-channel MOS transistor connected in series.
And a transistor TBNR1. Among them, the transistor TSPR1 and the transistor TSNR
Reference numeral 1 denotes a circuit functioning as the mode switching means PSW20, and the p-channel MOS transistor TBPR1 and the n-channel MOS transistor TBNR1 are inverter circuits for inverting the polarity of a signal.

The transistors TSPR1 and T
The gate electrodes of SNR1 are connected in common, and the sleep mode response signal output from the gate electrodes of the transistor TSPR2 and the transistor TBNR2 of the preceding mode switching means PSW18 is input.
Is a high-potential-side power supply terminal at one end of the mode switching means PSW20, and a source electrode of the transistor TSNR1 is a low-potential-side power supply terminal at the other end of the mode switching means PSW20. Further, the drain electrode to which the transistor TSPR1 and the transistor TSNR1 are commonly connected becomes a low-potential-side power supply terminal N18 to supply power to a low-potential-side power supply terminal of a transistor logic circuit FNC8, which is another component of the transistor logic circuit LGC20. Supply.

Here, the current drivability in the conductive state of p-channel MOS transistor TSPR1 is necessary in consideration of the device parameters of the transistors constituting transistor logic circuit FNC8 and the basic operating frequency and signal transition probability of transistor logic circuit FNC8. Set the appropriate current drive capability. Further, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability in the conductive state of the p-channel MOS transistor TSPR1 is determined by considering the basic operating frequency and the signal transition rate of the transistor logic circuit FNC8 and the gate width of the p-channel MOS transistor constituting the transistor logic circuit FNC8. A gate width smaller than the sum is given to the p-channel MOS transistor TSPR1. The amount of leakage current in the cut-off state of the p-channel MOS transistor TSPR1 is determined by the transistor logic circuit FN
The p-channel MOS transistor T is set so that the amount of leakage current is smaller than the sub-threshold leakage current of C8.
This is ensured by increasing the threshold voltage of SPR1, increasing the gate length, or increasing the thickness of the gate insulating film.

The mode switching means PSW21 comprises p-channel MOS transistors TSPR1 and TB
PR2, transistor TSPR1, and transistor TS
N-channel type MO connected in parallel to the gate electrode of PR2
A NOR gate circuit NOR2 comprising S transistors TSNR1 and TSNR2; a p-channel MOS transistor TBPR1 and an n-channel MOS transistor TB connected to the drain electrode output of the NOR gate circuit NOR2
NR1. Here, the NOR gate circuit NOR2 is a circuit functioning as the mode switching means PSW21, and is a p-channel MOS transistor TBPR.
1 and an n-channel MOS transistor TBNR1 are inverter circuits for inverting the polarity of a signal.

The gate electrodes of the transistors TSPR1 and TSNR1 are connected in common, and the mode switching means PSW of the preceding stage is connected.
19 transistors TBPR1 and TBNR
The sleep mode response signal output from the first gate electrode is input, the source electrode of the transistor TSPR1 is a high potential side power supply terminal at one end of the mode switching means PSW21, and the source electrode of the transistor TSNR1 is the one of the mode switching means PSW21. It becomes the low potential side power supply terminal at the other end. On the other hand, the transistor TSPR2 and the transistor TB
The gate electrode of NR2 is connected in common, and the sleep mode response signal output from the gate electrode of the transistor TBPR1 and the gate electrode of the transistor TBNR1 of the preceding mode switching means PSW20 is input.
Is a high potential side power supply terminal at one end of the mode switching means PSW21, and a source electrode of the transistor TBNR2 is a low potential side power supply terminal at the other end of the mode switching means PSW21. Further, the drain electrode of the NOR gate circuit NOR2 becomes the sleep mode response signal output terminal N19, and the sleep mode response signal S via the inverter circuit.
OT is output to the outside.

Here, the current drivability in the conductive state of p-channel MOS transistors TSPR1 and TSPR2 depends on the device parameters of the p-channel MOS transistors constituting transistor logic circuit FNC9, the basic operating frequency of transistor logic circuit FNC9 and the signal transition. The necessary current driving capability is set in consideration of the probability. Also, p-channel MOS transistors TSPR1 and TSPR1
The amount of leakage current in the cutoff state of PR2 is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

For example, the current drivability of the p-channel MOS transistors TSPR1 and TSPR2 in the conductive state is determined by taking into consideration the basic operating frequency of the transistor logic circuit FNC9 and the signal transition probability, as well as the gate of the p-channel MOS transistor constituting the transistor logic circuit FNC9. A gate width smaller than the sum of the widths is provided to the p-channel MOS transistors TSPR1 and TSPR2. Also, the p-channel MOS transistors TSPR1 and TSPR2 are set so that the amount of leakage current when the p-channel MOS transistors TSPR1 and TSPR2 are cut off is smaller than the sub-threshold leakage current of the transistor logic circuit FNC9.
It is ensured by increasing the threshold voltage of PR2, increasing the gate length, or increasing the thickness of the gate insulating film.

For example, the current drivability of the p-channel MOS transistors TSPR1 and TSPR2 in the conductive state is determined by taking into consideration the basic operating frequency of the transistor logic circuit FNC9 and the signal transition probability, as well as the gate of the p-channel MOS transistor constituting the transistor logic circuit FNC9. A gate width smaller than the sum of the widths is provided to the p-channel MOS transistors TSPR1 and TSPR2. Also, the p-channel MOS transistors TSPR1 and TSPR2 are configured such that the amount of leakage current when the p-channel MOS transistors TSPR1 and TSPR2 are cut off is smaller than the sub-threshold leakage current of the transistor logic circuit FNC9.
It is ensured by increasing the threshold voltage of PR2, increasing the gate length, or increasing the thickness of the gate insulating film.

The signal of the internal circuit of the semiconductor integrated logic circuit 102 according to the tenth embodiment of the present embodiment is set to the initial state, and then the active mode is changed to the sleep mode with reference to FIGS. The circuit response at the time will be described below.

The circuit response will be described along the flow of the sleep mode switching signal SIN.

When switching from the active mode to the sleep mode, the sleep mode switching signal SIN is set to Low.
Change from level to high level. Then, the mode switching means PSW15 to PSW21 sequentially shut off the power to each circuit along the flow of the sleep mode switching signal, and switch to the sleep mode.

When the sleep mode switching signal SIN is changed from the low level to the high level, the LGC 15
First, p constituting the mode switching means PSW15
The channel type MOS transistor TSPR1 is turned off and the n-channel type MOS transistor TSNR1 is turned off.
Is turned on, the supply of the high-potential-side power supply to the transistor logic circuit FNC3 is stopped, and the low-potential-side power supply terminal N13 transitions from the High level to the Low level. As a result, the logic operation of the transistor logic circuit FNC3 as the transistor logic circuit is forcibly stopped, and the power consumed by the transistor logic circuit LGC15 is a leakage current determined by the device parameters of the p-channel MOS transistor TSPR1 in the cutoff state. Only. Here, as described above, the p-channel type M
The amount of leakage current in the cut-off state of the OS transistor TSPR1 is determined by the semiconductor integrated logic circuit 102 in the sleep mode.
Is sufficiently small because it is set in consideration of the current consumption.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC1 through the next-stage inverter circuit.
6 and output to the LGC 17.

In the LGC 16, the low-potential-side power supply terminal N13 transitions from the High level to the Low level in the LGC 15, and the inverter circuit switches from the Low level to the Hi level in the inverter circuit.
gh level, the mode switching means PS
P-channel MOS transistor TS constituting W16
PR1 becomes conductive and the n-channel MOS transistor TSNR1 becomes cut off, stopping the supply of the high-potential-side power to the transistor logic circuit FNC4, and changing the low-potential-side power supply terminal N14 from the High level to the L level.
Transition to the ow level. As a result, the logic operation of the transistor logic circuit LGC16 with the power cutoff function is forcibly stopped as a transistor logic circuit, and the power consumed by the transistor logic circuit LGC16 is cut off. Only the leak current determined by the parameter is obtained. As described above, the amount of leakage current in the cutoff state of the p-channel MOS transistor TSPR1 is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LOG1 through the next-stage inverter circuit.
8 is output.

In the LGC 17, the low-potential-side power supply terminal N13 transitions from the High level to the Low level in the LGC 15, and the inverter circuit switches the Low-level power supply terminal N13 from the Low level to the Hi level.
gh level, the mode switching means PS
P-channel MOS transistor TS constituting W17
PR1 becomes conductive and the n-channel MOS transistor TSNR1 becomes cut off, the supply of the high-potential-side power supply of the transistor logic circuit FNC5 stops, and the low-potential-side power supply terminal N15 changes from the High level to the L level.
Transition to the ow level. As a result, the logic operation of the transistor logic circuit LGC17 with the power cutoff function as the transistor logic circuit LGC17 is forcibly stopped,
In addition, the power consumed by the transistor logic circuit LGC17 is in a cut-off state.
Only the leak current determined by the device parameter of PR1 is obtained. Here, as described above, the p-channel type MOS
The amount of leakage current in the cut-off state of the transistor TSPR1 has a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC1 via the next-stage inverter circuit.
8 is output.

The LGC 18 is a p-channel type that constitutes the mode switching means PSW 18 when the sleep mode response signal terminal N 14 changes from the high level to the low level in the LGC 16, and further changes from the low level to the high level in the inverter circuit. MOS transistor TSPR1 is turned off and n-channel type MO
S transistor TSNR1 is turned on. Further L
In GC17, the sleep mode response signal terminal N15 is set to High.
The transition from the h level to the low level and the transition from the low level to the high level by the inverter circuit cause the p-channel MOS transistor TBPR2 constituting the mode switching means PSW18 to be cut off and the n-channel MOS transistor TBNR2 Is turned on, and the sleep mode response signal terminal N16 transitions from the High level to the Low level. As a result, the transistor logic circuit LGC1 having the power cutoff function is provided.
Numeral 8 indicates that the logic operation as the transistor logic circuit is forcibly stopped, and the power consumed by the transistor logic circuit LGC18 is only the leakage current determined by the device parameters of the p-channel MOS transistors TSPR1 and TSPR2 which are turned off. Here, as described above, the p-channel MOS transistors TBPR1 and TBPR1
The amount of leakage current in the cutoff state of PR2 is a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

In the LGC 19, the sleep mode response signal terminal N16 transitions from the high level to the low level in the LGC 18, and furthermore, the inverter switches from the low level to the high level in the inverter.
The transition to the high level causes the mode switching means P
P-channel type MOS transistor T constituting SW19
The SPR1 becomes conductive and the n-channel MOS transistor TSNR1 becomes cut off, the supply of the high-potential-side power to the transistor logic circuit FNC7 stops, and the low-potential-side power supply terminal N17 changes from the High level to the Low level. Transition. As a result, the logic operation of the transistor logic circuit LGC19 having the power cutoff function is forcibly stopped as a transistor logic circuit, and the power consumed by the transistor logic circuit LGC18 is cut off. Only the leak current determined by the parameter is obtained. As described above, the amount of leakage current in the cut-off state of the p-channel MOS transistor TSPR1 has a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode. .

In the LGC 20, the sleep mode response signal terminal N16 changes from the high level to the low level in the LGC 18, and the inverter circuit changes from the low level to the high level. MOS transistor TSPR1 is turned on and n-channel type MO
The S transistor TSNR1 is turned off, the supply of the high-potential-side power to the transistor logic circuit FNC8 stops, and the low-potential-side power supply terminal N18 transitions from the High level to the Low level. As a result, the logic operation of the transistor logic circuit LGC20 with the power cutoff function is forcibly stopped as a transistor logic circuit, and the power consumed by the transistor logic circuit LGC20 is cut off.
There is only a leakage current determined by one device parameter. As described above, the amount of leakage current in the cut-off state of the p-channel MOS transistor TSPR1 has a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode. .

In the LGC 21, the low-potential-side power supply terminal N17 transitions from the High level to the Low level in the LGC 19, and further, the inverter circuit switches the Low-level power supply terminal N17 from the Low level to the Hi level.
gh level, the mode switching means PS
P-channel MOS transistor TS constituting W21
PR1 is turned on and n-channel MOS transistor TSNR1 is turned off. Further LGC20
As a result, the sleep mode response signal terminal N18 transitions from the high level to the low level, and further the inverter circuit transitions from the low level to the high level, so that the p-channel MOS transistor TBPR2 constituting the mode switching means PSW21 becomes conductive. At the same time, the n-channel MOS transistor TSNR2 is turned off, and the sleep mode response signal terminal N19 becomes High.
The state transits from the h level to the Low level. As a result, the logic operation of the transistor logic circuit LGC21 with the power cutoff function is forcibly stopped as a transistor logic circuit, and the power consumed by the transistor logic circuit LGC21 is cut off to form the p-channel MOS transistors TSPR1 and TSPR2. Only the leakage current determined by the device parameter of Here, as described above, p
Channel type MOS transistors TSPR1 and TSPR2
The leakage current amount in the shut-off state is set to a sufficiently small value because it is set in consideration of the current consumption of the semiconductor integrated logic circuit 102 in the sleep mode.

As described above, the sleep mode switching signal SIN is changed from the low level to the high level to make a transition from the active mode to the sleep mode. When the response signal SOT changes from the high level to the low level.
The transition to the level makes it possible to completely shut off the power to each of the transistor logic circuits LGC15 to LGC21 having a power shutoff function that constitutes the semiconductor integrated logic circuit 102.

Next, a circuit response when the mode is changed from the sleep mode to the active mode will be described with reference to FIG.

When switching from the sleep mode to the active mode, the sleep mode switching signal SIN is set to Hig.
The level is changed from the h level to the Low level. Then, the mode switching means PSW15 to PSW16 sequentially supply power to each circuit along the flow of the sleep mode switching signal to switch to the active mode.

The sleep mode switching signal SIN is set to High.
When changing from level to low level, LGC15
First, p constituting the mode switching means PSW15
The channel type MOS transistor TSPR1 becomes conductive and the n-channel type MOS transistor TSNR1
Is turned off, the supply of the high-potential-side power to the transistor logic circuit FNC3 starts, and the low-potential-side power supply terminal N13 transitions from the Low level to the High level. As a result, the transistor logic circuit FNC3 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is sent to the transistor logic circuit LGC1 via the next-stage inverter circuit.
6 and output to the LGC 17.

In the LGC 16, the low-potential-side power supply terminal N13 transitions from the Low level to the High level in the LGC 15, and the inverter circuit changes the High-level power supply terminal N13 from the High level to the L level.
ow level, the mode switching means PS
P-channel MOS transistor TS constituting W16
PR1 is turned on and the n-channel MOS transistor TSNR1 is turned off, the supply of high-potential-side power to the transistor logic circuit FNC2 starts, and the low-potential-side power supply terminal N14 changes from low to high.
gh level. As a result, the transistor logic circuit FNC4 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is sent to the transistor logic circuit LGC1 through the next-stage inverter circuit.
8 is output.

In the LGC 17, the low-potential-side power supply terminal N13 transitions from the Low level to the High level in the LGC 15, and the inverter circuit switches from the High level to the L level.
ow level, the mode switching means PS
P-channel MOS transistor TS constituting W17
PR1 becomes conductive, and n-channel MOS transistor TSNR1 becomes cut off. Supply of high-potential power to the transistor logic circuit starts, and low-potential power supply terminal N15 transitions from High level to Low level. I do. As a result, the transistor logic circuit FNC17 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC18 via the next-stage inverter circuit.
Output to

In the LGC 18, the low-potential-side power supply terminal N14 transitions from the Low level to the High level in the LGC 16, and the inverter circuit switches from the High level to the L level.
ow level, the mode switching means PS
P-channel MOS transistor TS constituting W18
PR1 is turned on and n-channel MOS transistor TSNR1 is turned off.
At 17, the low-potential-side power supply terminal N15 transitions from the low level to the high level, and
By transitioning from the high level to the low level,
One of the p-channel MOS transistors TBPR2 constituting the mode switching means PSW17 is turned on and the n-channel MOS transistor TBNR2 is turned off. Further, the low potential side power supply terminal N
15 changes from the low level to the high level, and further changes from the high level to the low level by the inverter circuit, the p-channel MOS transistor TSPR2 constituting the mode switching means PSW18 becomes conductive and the n-channel MOS transistor Transistor T
SNR2 is turned off, and the response signal terminal N16 goes low.
The state transits from the ow level to the high level. As a result, the transistor logic circuit FNC6 having the power cutoff function
Becomes a state in which a logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC1 via the next-stage inverter circuit.
9 and output to the LGC 20.

In the LGC 19, the low-order power supply terminal N16 transitions from the Low level to the High level in the LGC 18, and the inverter circuit changes from the High level to the Lo level.
The mode switching means PSW
P-channel type MOS transistor TSP constituting the semiconductor device 19
R1 becomes conductive and the n-channel MOS transistor TSNR1 becomes cut off, the supply of high-potential-side power to the transistor logic circuit FNC7 starts, and the low-potential-side power supply terminal N17 changes from High level to Lo.
Transition to the w level. As a result, the transistor logic circuit LGC18 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC21 via the next-stage inverter circuit.
Output to

In the LGC 20, the low-potential-side power supply terminal N16 transitions from the low level to the high level at the LGC 18, and the inverter circuit switches the high-level power supply terminal N16 from the high level to the low level.
ow level, the mode switching means PS
P-channel MOS transistor TS forming W20
PR1 is turned on and the n-channel MOS transistor TSNR1 is turned off, the supply of high-potential-side power to the transistor logic circuit FNC9 starts, and the low-potential-side power supply terminal N18 changes from low to high.
gh level. As a result, the transistor logic circuit FNC8 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is transmitted to the transistor logic circuit LGC21 via the next-stage inverter circuit.
Output to

In the LGC 21, the low-potential-side power supply terminal N17 transitions from the low level to the high level at the LGC 19, and furthermore, the inverter circuit switches the high-level power supply terminal N17 from the high level to the low level.
As a result, the p-channel MOS transistor TSPR1 constituting the sleep mode switching means PSW21 becomes conductive and the n-channel M transistor
The OS transistor TSNR1 is turned off. Further, since the low potential side voltage supply terminal N18 transitions from the low level to the high level in the LGC 20, and further transitions from the high level to the low level in the inverter circuit, one of the p-channel MOS transistors constituting the sleep mode switching means PSW18 Transistor TSPR2 is rendered conductive and n-channel MOS transistor TS
NR2 is cut off, and the transistor logic circuit FN
The supply of the high-potential-side power to C9 starts, and the low-potential-side power supply terminal N19 transitions from a low level to a high level. As a result, the transistor logic circuit FNC9 with the power cutoff function is in a state where logic operation as a transistor logic circuit is possible.

Further, the sleep mode response signal is sent to the transistor logic circuit LGC2 via the next-stage inverter circuit.
1 is output to the outside.

As described above, in the present embodiment, when executing the sleep mode operation intermittently, each of the transistor logic circuits LGC15 to LGC15 of the semiconductor integrated logic circuit 102 is used.
The C21 is provided with a NOR gate circuit and an inverter circuit as means for observing the mode transition between the active mode and the sleep mode and between the sleep mode and the active mode. As a result of the circuit operation,
After confirming that all the transistor logic circuits including the mode switching means with the power cutoff function have completely returned to a state where power can be completely supplied, the logic operation of the normal circuit as the active mode is performed. Since the operation can be started, no malfunction is caused, and the operation as the stable active mode can be executed.

In any case, the mode is switched after completely switching to either mode.

In the tenth embodiment shown in FIG. 15, there is shown a system diagram of a semiconductor integrated logic circuit 101 according to the present invention having a mode switching means capable of shutting off a power supply and having a response function.
In addition, by explaining the circuit operation, the mode switching means PSW15 to PSW21 and the mode switching means PSW15 to PSW21 serving as means for observing a mode transition between the active mode and the sleep mode when the sleep mode operation is intermittently executed. The power supply method of the semiconductor integrated logic circuit for propagating the mode transition detection signal in a chain between the mode switching means has been described.

Then, another mode switching means capable of turning on and off the power supply and adding a function of a response circuit for controlling and observing the mode transition between the active mode and the sleep mode will be described below. I do.

FIG. 17 shows a semiconductor integrated logic circuit 10 provided with a mode switching means having a power cutoff response function according to the present invention.
3 shows another system diagram of FIG. As shown in FIG. 17, in the present embodiment, a sleep mode switching signal SIN is input, a plurality of sleep mode switching signals SIN1 to SINm and sleep mode switching inversion signals SINB1 to SINBi are generated, and the sleep mode switching inversion signals SINB1 to SINBi are transmitted in parallel to the integrated logic circuit 110. It is an example of transmitting.

The semiconductor integrated logic circuit 110 shown in FIG.
Alternatively, the sleep mode switching signal S shown in each of FIGS.
IN1 to SINm or sleep mode switching inversion signal S
A mode with a power cutoff response function having a pair of paths that chainly propagate sleep mode response signals SOT1 to SOTn or sleep mode switching inversion signals SOTB1 to SOTBj as output signals with INB1 to SINBi as input signals. 1 shows a semiconductor integrated logic circuit in which a plurality of circuits such as the semiconductor integrated logic circuits 101 and 102 each having a switching means group are connected in parallel.
More specifically, i (where i is an arbitrary natural number)
Sleep mode switching inversion signals SINB1 to SINBi
And m (where m is an arbitrary natural number) sleep mode switching signals SIN1 to SINm, and j (where j is an arbitrary natural number) sleep mode response inverted signals SOTB1 to SOTBj and n ( Here, n is an arbitrary natural number).
It has SOTn, and a plurality of sleep mode switching signals in a broad sense and a plurality of sleep mode response signals in a broad sense are organically arbitrarily associated.

The semiconductor integrated circuit 103 automatically distributes and generates the sleep mode switching inversion signals SINB1 to SINBi and the sleep mode switching signals SIN1 to SINm from one sleep mode switching signal SIN, and a sleep mode response. Inversion signal SOTB1
To SOTBj and sleep mode response signals SOT1 to SO
From Tn, when the sleep mode operation is intermittently performed, a mode transition between the active mode and the sleep mode is finally observed, and a circuit configuration is provided which allows the determination circuit 130 to output the determination signal JOT.

As described above, according to the present invention, since the distribution circuit and the determination circuit are provided in the integrated logic circuit having a plurality of chain paths for transmitting the sleep mode signal in parallel, a plurality of sleep mode switching signals and sleep mode switching are provided. By inputting the inverted signal, the mode transition of the integrated logic circuit can be determined by the determination circuit.

FIG. 18 shows a semiconductor integrated logic circuit 10 provided with a mode switching means having a power cutoff response function according to the present invention.
4 shows another system diagram of FIG.

Here, another embodiment using a NAND gate logic circuit NAND3 as a more specific judgment circuit 131 of the judgment circuit 130 shown in FIG. 12 will be described.

The sleep mode switching signal SIN is input and distributed to two signals by a distribution circuit (not shown) built in the integrated logic circuit 111.
Only when both OT1 and SOT2 output a high-level signal (SOT1 = 1 and SOT2 = 1), that is, when both of them output a signal indicating transition to the sleep mode, the determination output JOT1 has a low-level signal ( (JOT1 = 0) is output, and a Low level signal is output to at least one of them (SOT1 = 0).
Or SOT2 = 0), that is, if either one remains in the active mode, the judgment output JOT1 is set to High.
A level signal (JOT1 = 1) is output.

In this embodiment, the NAND gate circuit NAND3 is used as the judgment circuit. However, an AND gate circuit may be used instead of the NAND gate circuit. Further, instead of the two-input NAND gate circuit, an n-input NAND gate circuit may be used.

As described above, according to the present invention, the NAND gate circuit is provided in the integrated logic circuit having the two series and parallel chain paths for transmitting the sleep mode signal.
The mode transition of the integrated logic circuit can be determined by the NAND gate circuit.

FIG. 19 shows a semiconductor integrated logic circuit 10 provided with a mode switching means having a power cutoff response function according to the present invention.
5 shows another system diagram of FIG.

Here, another embodiment using a NOR gate logic circuit NOR1 as a more specific judgment circuit 131 of the judgment circuit 103 shown in FIG. 12 will be described.

The sleep mode cut-off signal SIN is input and distributed to two signals by a distribution circuit (not shown) built in the integrated logic circuit 111, and the sleep mode response signal SO is output.
Only when T1 and SOT2 output a low-level signal (SOT1 = 0 and SOT2 = 0), that is, when both of them output a signal indicating that they remain in the active mode, the judgment output JOT2 has a high-level signal. (JOT1 = 1) is output, and a High-level signal is output to at least one of them (SOT1 =
1 or SOT2 = 1), that is, if either one transits to the sleep mode, a high-level signal (JOT2 = 0) is output to the determination output JOT2.

In the present embodiment, the NOR gate circuit NOR1 is used as the determination circuit, but an OR gate circuit may be used instead of the NOR gate circuit. Also, an n-input NOR gate circuit may be used instead of a 2-input NOR gate.

As described above, in the present invention, since the NOR gate circuit is provided in the integrated logic circuit having the systematic and parallel integrated logic circuits for transmitting the sleep mode signal, the mode transition of the integrated logic circuit is performed by the NOR gate circuit. Can be determined.

[0352]

As described above, according to the present embodiment, the following remarkable effects are obtained.

(1) When the sleep mode operation is performed intermittently, each circuit of the semiconductor integrated logic circuit includes an inverter circuit as mode switching means between the active mode and the sleep mode and between the sleep mode and the active mode. In particular, when transitioning from the sleep mode to the active mode, as a result of the above series of chained circuit operations, all the logic circuits including the mode switching means with the power cutoff function are completely supplied with power. After confirming that it has completely returned to the state in which it can be obtained, it is possible to start the logical operation of the normal circuit as the active mode. can do.

(2) When the sleep mode operation is executed intermittently, since the NOR gate circuit is provided as the mode switching means between the active mode and the sleep mode and between the sleep mode and the active mode, the sleep mode is particularly used. As a result of the above-described series of circuit operations when transitioning from the mode to the active mode, all the transistor logic circuits including the mode switching means with the power cutoff function are completely returned to a state in which the power can be completely supplied. Since it is possible to start the normal logic operation as the active mode after confirming that the operation is performed, it is possible to execute the stable operation as the active mode without causing a malfunction.

(3) When the sleep mode operation is performed intermittently, the NAND gate circuit is provided as the mode switching means between the active mode and the sleep mode and between the sleep mode and the active mode. As a result of the above-described series of circuit operations when transitioning from the mode to the active mode, all the transistor logic circuits provided with the mode switching means with the power cutoff function completely return to a state where they can be completely supplied with power. Since it is possible to start the normal logical operation as the active mode after confirming that the operation is performed, it is possible to execute the stable operation as the active mode without causing a malfunction.

(4) When the sleep mode operation is performed intermittently, the NOR gate circuit is provided as a mode switching means between the active mode and the sleep mode and between the sleep mode and the active mode. As a result of the above-described series of circuit operations when transitioning from the mode to the active mode, all the transistor logic circuits including the mode switching means with the power cutoff function are completely returned to a state in which the power can be completely supplied. Since it is possible to start the normal logical operation as the active mode after confirming that the operation is performed, a stable active mode operation can be performed without causing a malfunction.

(5) Since the sleep mode operation is intermittently performed, since the NAND gate circuit and the inverter circuit are provided as mode switching means between the active mode and the sleep mode and between the sleep mode and the active mode. In particular, when transitioning from the sleep mode to the active mode, as a result of the above series of chained circuit operations, all transistor logic circuits including the mode switching means with a power cutoff function can be completely supplied with power. After confirming that the operation is completely restored, the normal logic operation in the active mode can be started. Therefore, a stable active mode operation can be performed without causing a malfunction.

(6) Since a distribution circuit and a decision circuit are provided in an integrated logic circuit having a plurality of chain paths for transmitting sleep mode signals in parallel, a plurality of sleep mode switching signals and a sleep mode switching inversion signal are inputted. The mode transition of the integrated logic circuit can be determined by the determination circuit.

(7) Since the OR gate circuit is provided in the integrated logic circuit having two parallel paths for transmitting the sleep mode signal, the mode transition of the integrated logic circuit can be determined by the OR gate circuit.

(8) Since the NOR gate circuit is provided in the integrated logic circuit having two parallel paths for transmitting the sleep mode signal, the mode transition of the integrated logic circuit can be determined by the NOR gate circuit.

(9) Since the AND gate circuit is provided in the integrated logic circuit having the two parallel paths for transmitting the sleep mode signal, the mode transition of the integrated logic circuit can be determined by the AND gate circuit.

(10) NAN is added to an integrated logic circuit having two parallel and parallel paths for transmitting a sleep mode signal.
Since the D gate circuit is provided, the mode transition of the integrated logic circuit can be determined by the NAND gate circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of a first embodiment of the present invention.

FIG. 2 is a detailed system diagram of a first embodiment of a semiconductor integrated logic circuit including the mode switching means with a power cutoff response function shown in FIG. 1;

FIG. 3 is a diagram showing a configuration and operation of an inverter circuit.

FIG. 4 is a mode transition diagram showing mode switching.

FIG. 5 is a timing chart showing the operation of the present embodiment.

FIG. 6A is a diagram illustrating the configuration and function of an n-input NAND gate circuit, and FIG. 6B is a diagram illustrating the configuration and function of an n-input NOR gate circuit.

FIG. 7A shows a mode switching means PSW7 capable of shutting off a power supply and having a response function according to a second embodiment of the present invention.
(B) is a circuit diagram of (a) mode switching means PS
7 is a truth table of a transistor logic circuit with mode switching means LGC including a transistor logic circuit FNC2 receiving power supply from W7 and mode switching means.

FIG. 8A shows a mode switching means PSW8 capable of shutting off a power supply and having a response function according to a third embodiment of the present invention.
(B) is a circuit diagram of (a) mode switching means PS
7 is a truth table of a transistor logic circuit LGC with mode switching means including a transistor logic circuit FNC3 that receives power supply from W8 and mode switching means. .

FIG. 9A shows a mode switching means PSW9 capable of shutting off the power supply and having a response function according to the fourth embodiment of the present invention.
(B) is a circuit diagram of (a) mode switching means PS
7 is a truth table of a transistor logic circuit with mode switching means LGC including a transistor logic circuit FNC4 that receives power supply from W9 and mode switching means. .

FIG. 10A shows a mode switching means PSW capable of shutting off a power supply and having a response function according to a fifth embodiment of the present invention.
FIG. 10B is a circuit diagram of FIG. 10, and FIG. 10B is a truth table of the transistor logic circuit with mode switching means LGC including (a) the mode switching means PSW10 and the transistor logic circuit FNC5 which receives power supply from the mode switching means.

FIG. 11A shows a mode switching means PSW capable of shutting off a power supply and having a response function according to a sixth embodiment of the present invention.
FIG. 11B is a circuit diagram of FIG. 11, and FIG. 11B is a truth table of the transistor logic circuit with mode switching means LGC including (a) the mode switching means PSW11 and the transistor logic circuit FNC6 which receives power supply from the mode switching means.

FIG. 12A shows a mode switching means PSW capable of shutting off a power supply and having a response function according to a seventh embodiment of the present invention.
12 is a circuit diagram of FIG. 12, and (b) is a truth table of the transistor logic circuit LGC with mode switching means including (a) the mode switching means PSW12 and the transistor logic circuit FNC7 which receives power supply from the mode switching means.

FIG. 13A shows a mode switching means PSW capable of shutting off a power supply and having a response function according to an eighth embodiment of the present invention.
13 is a circuit diagram of FIG. 13, and (b) is a truth table of the transistor logic circuit LGC with mode switching means including (a) the mode switching means PSW13 and the transistor logic circuit FNC8 which receives power supply from the mode switching means.

FIG. 14A shows a mode switching means PSW capable of shutting off a power supply and having a response function according to a ninth embodiment of the present invention.
FIG. 14B is a circuit diagram of FIG. 14B, and FIG. 14B is a truth table of the transistor logic circuit LGC with mode switching means including (a) the mode switching means PSW14 and the transistor logic circuit FNC9 which receives power supply from the mode switching means.

FIG. 15 is a block diagram showing an overall configuration of a tenth embodiment of the present invention.

FIG. 16 is a detailed system diagram of a tenth embodiment of a semiconductor integrated logic circuit including the mode switching means with a power cutoff response function shown in FIG. 15;

FIG. 17 is a diagram showing a circuit configuration of an eleventh embodiment of the present invention.

FIG. 18 is a diagram showing a circuit configuration of a twelfth embodiment of the present invention.

FIG. 19 is a diagram showing a circuit configuration of a thirteenth embodiment of the present invention.

FIG. 20 is a system diagram of a semiconductor integrated logic circuit including a mode switching unit with a power cutoff response function according to the related art.

[Explanation of symbols]

3a, 5a, 6a, 3c INV (inverter) circuit 1a, 2a NAND gate circuit NOR1, NOR2 NOR gate circuit 1b, 2b, 3b, 4b, 5b, 6b, 10, 11b,
12, 13b, 14b, 15b, 16b Mode switching means PSW TSP2A, TSP1, TDP1, TDP2, TSP3
A, TIP1, TSP4, TBP1, TSP5, TIP
2, TBP2, TSP6, TBP3, TSPR1, TB
PR1, PBPR2, TSPR1, TBPR1, TSP
R1, TBPR1, TSPR2, TSNR1 P-channel MOS transistor TSN2, TSN1A, TDN1, TDN2, TSN
3, TIN1, TSN4A, TBN1, TSN5A, T
BN2, TIN2, TSN6A, TBN3, TSNR
1, TBNR1, PBNR2, TSNR1 n-channel MOS transistors FNC1, FBC2, FNC3, FNC4, FNC5
FNC5, FNC6, FNC7, FNC8, FNC9
Transistor logic circuit 20 Mode switching means 21 Active mode state 22 Sleep mode state 101 First embodiment of the present invention 102 Second embodiment of the present invention 103 Eleventh embodiment of the present invention 120 Distribution circuit 110 Multiple sleep signals And an integrated logic circuit having a chain path for transmitting a sleep signal 111 and an integrated logic circuit having two parallel chain paths for transmitting a sleep signal 130 a judgment circuit N1, N3, PA1, PA2, PAn a high potential side power supply terminal N2 N4, N6, N7, N8, N9, N10, N1
1, N12, N13, N14, N15, NA1, NA
2, NAn Low potential side power supply terminal

Claims (11)

[Claims] A plurality of logic circuits; and a mode switching unit configured to perform mode switching between an active mode in which power is supplied to the plurality of logic circuits and a sleep mode in which power is supplied to the plurality of logic circuits. The mode switching means, when intermittently switching between the sleep mode and the active mode, inputs a signal for instructing supply and cutoff of power to the plurality of logic circuits. Supply and cut off power supply to
When switching from the sleep mode to the active mode, a state in which power can be supplied to all the logic circuits by inputting a signal indicating power supply and sequentially supplying power to the plurality of logic circuits sequentially And outputting a signal indicating that operation is possible in the active mode. 2. The semiconductor integrated logic circuit according to claim 1, wherein said mode switching means comprises a mode switching section provided in each of said plurality of logic circuits, wherein said mode switching section is a p-channel MOS transistor. And n-channel type M
An OS transistor, the p-channel MOS
The gate electrode and the drain electrode of the n-channel type MOS transistor and the n-channel type MOS transistor are input and output parts, respectively, are inverter circuits, and supply and cut off power to the input part of the inverter circuit provided in the first stage logic circuit. And a sleep mode response signal indicating that the operation in the active mode is possible is output from the output section of the inverter circuit provided in the last-stage logic circuit. Characteristic semiconductor integrated logic circuit. 3. The semiconductor integrated logic circuit according to claim 2, wherein the mode switching means functions as a switch for switching a signal, and when switching from an active mode to a sleep mode, a high-level signal is input to its gate electrode. Then, the p-channel type M constituting the mode switching means
When the OS transistor is turned off, the n-channel MOS transistor is turned on and the power to the plurality of logic circuits is cut off, and the mode is switched from the sleep mode to the active mode, a low-level signal is input to the gate electrode of the mode, and the mode is switched off. P-channel type M constituting switching means
A semiconductor integrated logic circuit, wherein an OS transistor is turned on, an n-channel MOS transistor is turned off, and power is supplied to the plurality of logic circuits. 4. The semiconductor integrated logic circuit according to claim 1, wherein said mode switching means comprises a mode switching section provided in each of said plurality of logic circuits, and said mode switching section is provided in series with a predetermined mode. A plurality of p-channel MOS transistors, and a predetermined number of n-channel MOS transistors provided in parallel with the drain electrodes of the predetermined number of p-channel MOS transistors. And n-channel MOS
A gate electrode and a drain electrode of a transistor are an input part and an output part, respectively. These are NOR gate circuits in which the output part and the input part are sequentially connected. The input part of the NOR gate circuit provided in the first stage logic circuit A sleep mode switching signal is input to the NOR gate circuit, and a sleep mode response signal is output from an output part of a NOR gate circuit provided in the last stage logic circuit. 5. The semiconductor integrated logic circuit according to claim 1, wherein said mode switching means comprises a mode switching section provided in each of said plurality of logic circuits, and said mode switching section is provided in parallel with a predetermined mode. A predetermined number of p-channel MOS transistors, and a predetermined number of n-channel MOS transistors provided in series with the drain electrodes of the predetermined number of p-channel MOS transistors. And n-channel MOS
A gate electrode and a drain electrode of the transistor are an input unit and an output unit, respectively, and the output unit and the input unit are sequentially connected to each other. A sleep mode switching signal, and a sleep mode response signal is output from an output part of a NAND gate circuit provided in a final stage logic circuit. 6. An integrated logic circuit composed of a plurality of logic circuits, and a mode switch between an active mode in which power is supplied to the plurality of logic circuits and a sleep mode in which power is cut off to the plurality of logic circuits. And a plurality of sleep mode switching signals from a sleep mode switching signal indicating one of the active mode and the sleep mode as an input current mode. A distribution circuit for generating and distributing a sleep mode switching inversion signal in which the polarity of a sleep mode switching signal is inverted; and a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit, the integrated logic circuit And a determination circuit for determining a mode transition of the plurality of logic circuits, wherein the plurality of logic circuits are output by the distribution circuit. A plurality of sleep mode switching signals and a sleep mode switching inversion signal to output a sleep mode response signal indicating whether a current mode is the active mode or the sleep mode. Logic circuit. 7. The semiconductor integrated logic circuit according to claim 6, wherein the determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit and outputs a NAND of them. A semiconductor integrated logic circuit, comprising: 8. The semiconductor integrated logic circuit according to claim 6, wherein the determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit and outputs a NAND of them. A semiconductor integrated logic circuit, which is a NAND gate circuit. 9. The semiconductor integrated logic circuit according to claim 6, wherein the determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit, and outputs a NOR of them. A semiconductor integrated logic circuit, which is an OR gate circuit. 10. The semiconductor integrated logic circuit according to claim 6, wherein the determination circuit inputs a sleep mode response signal output from each of a plurality of logic circuits constituting the integrated logic circuit, and outputs a NOR of them. A semiconductor integrated logic circuit, which is a NOR gate circuit. 11. A plurality of logic circuits, and mode switching means for performing mode switching between an active mode in which power is supplied to the plurality of logic circuits and a sleep mode in which power is supplied to the plurality of logic circuits, A power supply method for a semiconductor integrated logic circuit, comprising: when a sleep mode switching signal indicating one of the active mode and the sleep mode is input as a current mode input to the mode switching means, ,
A power supply method for a semiconductor integrated logic circuit, wherein the power supply to the plurality of logic circuits is sequentially and sequentially supplied.