JP2000150912A - Static induction transistor - Google Patents
Static induction transistorInfo
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- JP2000150912A JP2000150912A JP10314314A JP31431498A JP2000150912A JP 2000150912 A JP2000150912 A JP 2000150912A JP 10314314 A JP10314314 A JP 10314314A JP 31431498 A JP31431498 A JP 31431498A JP 2000150912 A JP2000150912 A JP 2000150912A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、静電誘導トランジ
スタの構造に関する。The present invention relates to a structure of a static induction transistor.
【０００２】[0002]
【従来の技術】電力変換器の大電力かつ高周波化の要求
にともなって、可制御電流が大きいだけでなく、低損失
で、かつ高速に動作する半導体スイッチング素子の開発
が望まれている。このような要求に応える方法として、
以下に示す二つの取り組みが考えられる。一つは今日、
最も多用されているシリコンを素子材料に使い、素子構
造や動作原理の組み合わせを見直して、既存素子の一層
の高性能化を計る方法である。この方法には高度に確立
した製造技術と多くの知見を活用できることから、素子
性能の向上が容易である反面、性能がシリコンの持つ物
理的理論限界で制限を受け、素子性能の大幅な向上は望
めないという課題がある。2. Description of the Related Art With the demand for higher power and higher frequency of power converters, it is desired to develop a semiconductor switching element which not only has a large controllable current but also operates at high speed with low loss. As a method to meet such demands,
The following two approaches can be considered. One is today,
This method uses silicon, which is most frequently used, as the element material, reviews the combination of the element structure and the operating principle, and further enhances the performance of existing elements. Since this method can utilize highly established manufacturing technology and a lot of knowledge, it is easy to improve the device performance, but the performance is limited by the physical theoretical limits of silicon, and the device performance is greatly improved. There is a problem that we cannot hope for.
【０００３】もう一つは、素子の原材料から見直して、
シリコンの限界をはるかに越えた、高性能なパワー半導
体素子を実現する方法がある。例えば、シリコンカーバ
イド（以下ＳｉＣ）を用いた場合、素子性能がシリコン
を用いた素子の１０倍以上になることが、文献：IEEE E
lectron Device Letters, Vol. 10, No. 10, p. 455(19
89)の中に示されている。このように、ＳｉＣを利用す
ることで、優れた素子性能のデバイスが実現できる理由
は、アバランシェ降伏電界が大きいことにある。例え
ば、ＳｉＣはアバランシェ降伏電界がシリコンの約１０
倍と大きく、素子のドリフト層の電気抵抗を約２桁小さ
くできることが、文献：IEEE Transactionof Electron
Devices, Vol. 40, No. 3, p. 645 (1993)に示されてい
る。そのため、素子がオン状態の時に発生する電力損失
を小さくできるとして、大きな期待がもたれている。The other is to review the raw materials of the device,
There is a method for realizing a high-performance power semiconductor device far beyond the limit of silicon. For example, when silicon carbide (hereinafter referred to as SiC) is used, the performance of the device is more than 10 times that of a device using silicon.
lectron Device Letters, Vol. 10, No. 10, p. 455 (19
89). The reason why a device having excellent element performance can be realized by using SiC is that the avalanche breakdown electric field is large. For example, SiC has an avalanche breakdown field of about 10 times that of silicon.
That the electrical resistance of the drift layer of the device can be reduced by about two orders of magnitude.
Devices, Vol. 40, No. 3, p. 645 (1993). For this reason, great expectations are placed on reducing the power loss that occurs when the element is in the ON state.
【０００４】ＳｉＣのMOSFETの試作例はこれまでに、い
くつか報告されている。しかし、反転層の移動度が低
く、オン抵抗が高くなる。われわれは、ＳｉＣにおいて
は、反転層の移動度の向上は困難と考え、静電誘導トラ
ンジスタ（Static InductionTransistor）に注目した。
静電誘導トランジスタは反転層がないため、反転層の移
動度が低い問題を回避できる。Several prototypes of SiC MOSFETs have been reported so far. However, the mobility of the inversion layer is low, and the on-resistance is high. It, in SiC, considered difficult improvement in the mobility of the inversion layer, and focused on a static induction transistor (S tatic I nduction T ransistor) .
Since the static induction transistor has no inversion layer, the problem of low mobility of the inversion layer can be avoided.
【０００５】図２は従来の静電誘導トランジスタの鳥瞰
図を示す。この半導体基板はｐ+ 型領域１，ｎ- 型領域
２，ｎ+ 型領域３，ｎ+ 型領域４，ｐ型領域５からな
り、ソース電極１１と、ドレイン電極１２と、ゲート電
極１３が設けられている。ソースに対して、ゲートの電
位を低くすることにより、ｐ型領域５とｐ+ 型領域１の
間、いわゆるチャネルと呼ばれる領域に空乏層を広げ、
ドレイン電極１２とソース電極１１を流れる電流をオフ
することができる。なお、ｐ+ 型領域１の電位、すなわ
ち基板電位はソースまたはゲートと同電位とする。FIG. 2 is a bird's-eye view of a conventional static induction transistor. This semiconductor substrate is composed of a p + type region 1, an n − type region 2, an n + type region 3, an n + type region 4, and a p type region 5, and a source electrode 11, a drain electrode 12, and a gate electrode 13 are provided. Have been. By lowering the potential of the gate with respect to the source, the depletion layer is expanded between the p-type region 5 and the p + -type region 1 in a region called a channel,
The current flowing through the drain electrode 12 and the source electrode 11 can be turned off. Note that the potential of the p + type region 1, that is, the substrate potential is the same as the source or the gate.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、図２の
構造では、オフ特性が著しく悪いものとなる。すなわ
ち、オフするために大きなゲート電圧を加えなければな
らない。However, in the structure shown in FIG. 2, the off characteristic is extremely poor. That is, a large gate voltage must be applied to turn off.
【０００７】ＳｉＣにおいて、上記したようにオフ特性
が悪いのは、ドリフト層と呼ばれるｎ- 型領域の不純物
濃度が高いため、空乏層が伸びにくいためである。シリ
コンの静電誘導トランジスタと同じ耐電圧で比較した場
合、ＳｉＣのｎ- 型領域の不純物濃度は約１００倍とな
る。[0007] The reason why the off characteristics of SiC is poor as described above is that the depletion layer does not easily extend due to the high impurity concentration of the n - type region called the drift layer. When compared with a silicon static induction transistor at the same withstand voltage, the impurity concentration of the n − -type region of SiC is about 100 times.
【０００８】不純物濃度Ｎと空乏層幅Ｗには、次のよう
な関係がある。The following relationship exists between the impurity concentration N and the depletion layer width W.
【０００９】Ｗ∝Ｎ＾０.５したがって、ＳｉＣの空乏
層幅はシリコンの約１／１０となる。不純物濃度が高い
ことは、導通時の抵抗低減には有効であるが、オフ特性
が著しく悪いという問題を引き起こす。W∝N ＾ 0.5 Therefore, the depletion layer width of SiC is about 1/10 of silicon. A high impurity concentration is effective in reducing the resistance during conduction, but causes a problem that the off characteristic is extremely poor.
【００１０】以上より、従来構造ではオフ特性の優れた
ＳｉＣ静電誘導トランジスタを実現することは困難であ
る。As described above, it is difficult to realize a SiC electrostatic induction transistor having excellent off characteristics with the conventional structure.
【００１１】[0011]
【課題を解決するための手段】上記問題を解決するため
に、本発明ではゲートを表面ｐ型領域と縦型ｐ型領域か
ら構成し、オフ状態で空乏層を二次元的に広げる。In order to solve the above problem, in the present invention, the gate is constituted by a surface p-type region and a vertical p-type region, and the depletion layer is two-dimensionally expanded in an off state.
【００１２】以上の手段により、空乏層が横および縦方
向に延びるため、低ゲート電圧でチャネルをピンチで
き、オフ特性を大幅に向上することが可能となる。By the above means, since the depletion layer extends in the horizontal and vertical directions, the channel can be pinched with a low gate voltage, and the off characteristics can be greatly improved.
【００１３】[0013]
【発明の実施の形態】以下、本発明を実施例を開示しな
がら詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.
【００１４】図１は本発明の第１の実施例であり、シリ
コンカーバイド（ＳｉＣ）静電誘導トランジスタの鳥瞰
図を示す。FIG. 1 is a bird's-eye view of a silicon carbide (SiC) static induction transistor according to a first embodiment of the present invention.
【００１５】この半導体基板はｐ+ 型領域１、ｎ- 型領
域２，ｎ+ 型領域３，ｎ+ 型領域４，ｐ型領域５からな
り、ソース電極１１と、ドレイン電極１２と、ゲート電
極１３が設けられている。This semiconductor substrate comprises a p + type region 1, an n − type region 2, an n + type region 3, an n + type region 4 and a p type region 5, and a source electrode 11, a drain electrode 12, a gate electrode 13 are provided.
【００１６】本実施例の特徴は、ゲートとしてｐ型領域
５の他に、縦型ｐ型領域６を用いたことである。A feature of the present embodiment is that a vertical p-type region 6 is used in addition to the p-type region 5 as a gate.
【００１７】従来例とのオフ状態での動作の違いを以下
説明する。図３は従来例の図２の導通状態での鳥瞰図を
示す。２１は電子の流れを示す。断面２０は、ソース，
ドレイン方向に対して、ゲート電極の位置で垂直に切っ
た面を表している。The difference in the operation in the off state from the conventional example will be described below. FIG. 3 shows a bird's-eye view of the conventional example in the conducting state of FIG. 21 indicates a flow of electrons. Section 20 is the source,
The plane perpendicular to the position of the gate electrode with respect to the drain direction is shown.
【００１８】図４はオフ状態での図３における断面２０
の空乏層の様子を示す。２１は電子の流れを示し、手前
から奥に向かう向きである。２２は空乏層を示す。な
お、ｐ+ 型領域１の電位をゲート電位と同じとした。こ
の場合、空乏層はｐ+ 型領域１とｐ型領域５から、ｎ-
型領域２の方向に上下に広がることが分かる。すなわ
ち、空乏層は一次元的に広がる。FIG. 4 shows a cross section 20 in FIG. 3 in the off state.
The state of the depletion layer is shown. Reference numeral 21 denotes a flow of electrons, which is a direction from the front to the back. 22 denotes a depletion layer. Note that the potential of the p + type region 1 was the same as the gate potential. In this case, the depletion layer is formed from p + -type region 1 and p-type region 5 to n −
It can be seen that it spreads up and down in the direction of the mold region 2. That is, the depletion layer extends one-dimensionally.
【００１９】図５は本発明の第一の実施例である図１の
導通状態での鳥瞰図を示す。２１は電子の流れを示す。
電子は縦型ｐ型領域６がないところを流れる。断面２０
は、ソース，ドレイン方向に対して、ゲート電極の位置
で垂直に切った面を表している。FIG. 5 is a bird's-eye view of the first embodiment of the present invention in the conducting state of FIG. 21 indicates a flow of electrons.
The electrons flow where there is no vertical p-type region 6. Cross section 20
Indicates a plane cut perpendicularly to the position of the gate electrode with respect to the source and drain directions.
【００２０】図６はオフ状態での図５における断面２０
の空乏層の様子を示す。２１は電子の流れを示し、手前
から奥に向かう向きである。２２は空乏層を示す。な
お、ｐ+ 型領域１の電位をゲート電位と同じとした。こ
の場合、空乏層はｐ+ 型領域１とｐ型領域５の間、およ
び縦型ｐ型領域６の間に広がる。すなわち、空乏層は二
次元的に広がる。以上より、本発明では低いゲート電圧
でチャネルがピンチするため、優れたオフ特性のＳｉＣ
静電誘導トランジスタを実現することができる。FIG. 6 shows a cross section 20 in FIG. 5 in the off state.
The state of the depletion layer is shown. Reference numeral 21 denotes a flow of electrons, which is a direction from the front to the back. 22 denotes a depletion layer. Note that the potential of the p + type region 1 was the same as the gate potential. In this case, the depletion layer extends between p + -type region 1 and p-type region 5 and between vertical p-type region 6. That is, the depletion layer spreads two-dimensionally. As described above, in the present invention, since the channel is pinched at a low gate voltage, SiC having excellent off characteristics is obtained.
An electrostatic induction transistor can be realized.
【００２１】図７は本発明の第二の実施例であり、Ｓｉ
Ｃのショットキーゲート電界効果トランジスタの鳥瞰図
を示す。FIG. 7 shows a second embodiment of the present invention.
1 shows a bird's-eye view of a C Schottky gate field effect transistor.
【００２２】この半導体基板はｐ+ 型領域１，ｎ- 型領
域２，ｎ+ 型領域３，ｎ+ 型領域４からなり、ソース電
極１１と、ドレイン電極１２と、ｎ- 型領域２とショッ
トキー接合を形成するショットキーゲート電極１４が設
けられている。This semiconductor substrate is composed of a p + type region 1, an n − type region 2, an n + type region 3, and an n + type region 4, and a source electrode 11, a drain electrode 12, an n − type region 2, A Schottky gate electrode 14 for forming a key junction is provided.
【００２３】本実施例の特徴は、ゲートとしてショット
キーゲート電極１４の他に、縦型ショットキーゲート領
域１５を用いたことである。この構造でも、図６と同様
に空乏層は二次元的に広がる。以上より、本発明では低
いゲート電圧でチャネルがピンチするため、優れたオフ
特性のＳｉＣ静電誘導トランジスタを実現することがで
きる。The feature of this embodiment is that a vertical Schottky gate region 15 is used in addition to the Schottky gate electrode 14 as a gate. Also in this structure, the depletion layer spreads two-dimensionally as in FIG. As described above, in the present invention, since the channel is pinched at a low gate voltage, a SiC static induction transistor having excellent off characteristics can be realized.
【００２４】図８は本発明の第三の実施例であり、Ｓｉ
Ｃのショットキーゲート電界効果トランジスタの鳥瞰図
を示す。FIG. 8 shows a third embodiment of the present invention.
1 shows a bird's-eye view of a C Schottky gate field effect transistor.
【００２５】この半導体基板はｐ+ 型領域１，ｎ- 型領
域２，ｎ+ 型領域３，ｎ+ 型領域４からなり、ソース電
極１１と、ドレイン電極１２と、ｎ- 型領域２とショッ
トキー接合を形成するショットキーゲート電極１４が設
けられている。This semiconductor substrate comprises a p + type region 1, an n − type region 2, an n + type region 3, and an n + type region 4. The source electrode 11, the drain electrode 12, the n − type region 2, A Schottky gate electrode 14 for forming a key junction is provided.
【００２６】本発明の特徴は、ゲートとしてショットキ
ーゲート電極１４の下に、縦型ｐ型領域６を用いたこと
である。この構造でも、図６と同様に空乏層は二次元的
に広がる。以上より、本実施例では低いゲート電圧でチ
ャネルがピンチするため、優れたオフ特性のＳｉＣ静電
誘導トランジスタを実現することができる。A feature of the present invention is that a vertical p-type region 6 is used below the Schottky gate electrode 14 as a gate. Also in this structure, the depletion layer spreads two-dimensionally as in FIG. As described above, in the present embodiment, the channel is pinched at a low gate voltage, so that a SiC electrostatic induction transistor having excellent off characteristics can be realized.
【００２７】図９は本発明の第四の実施例であり、Ｓｉ
Ｃの静電誘導トランジスタの鳥瞰図を示す。FIG. 9 shows a fourth embodiment of the present invention.
1 shows a bird's-eye view of a C static induction transistor.
【００２８】図１と異なる本実施例の特徴は、基板とし
てｐ+ 型領域１の代わりに、高抵抗領域７を用いたこと
である。この構造でも、図６と同様に空乏層は二次元的
に広がる。以上より、本発明では低いゲート電圧でチャ
ネルがピンチするため、優れたオフ特性のＳｉＣ静電誘
導トランジスタを実現することができる。The feature of the present embodiment different from FIG. 1 is that a high resistance region 7 is used instead of the p + type region 1 as a substrate. Also in this structure, the depletion layer spreads two-dimensionally as in FIG. As described above, in the present invention, since the channel is pinched at a low gate voltage, a SiC static induction transistor having excellent off characteristics can be realized.
【００２９】図１０は本発明の第五の実施例であり、Ｓ
ｉＣの縦型静電誘導トランジスタの断面図である。ｐ+
型領域１の代わりに、埋込ｐ型領域９を用いたことが、
第一の実施例と異なる。ソース電極に対してドレイン電
極が半導体基板の反対の表面に形成されているが、チャ
ネルは横方向である。この構造でも、図６と同様に空乏
層は二次元的に広がる。以上より、本実施例では低いゲ
ート電圧でチャネルがピンチするため、優れたオフ特性
のＳｉＣ静電誘導トランジスタを実現することができ
る。FIG. 10 shows a fifth embodiment of the present invention.
It is sectional drawing of the vertical electrostatic induction transistor of iC. p +
The use of the buried p-type region 9 instead of the type region 1
This is different from the first embodiment. A drain electrode is formed on the opposite surface of the semiconductor substrate with respect to the source electrode, but the channel is lateral. Also in this structure, the depletion layer spreads two-dimensionally as in FIG. As described above, in the present embodiment, the channel pinches at a low gate voltage, so that a SiC electrostatic induction transistor having excellent off characteristics can be realized.
【００３０】図１１は、本発明を適用したＳｉＣ静電誘
導トランジスタおよびダイオードを用いて、電動機駆動
用インバータを構成した一例を示したものである。六個
の静電誘導トランジスタ、ＳＷ１１，ＳＷ１２，ＳＷ２
１，ＳＷ２２，ＳＷ３１，ＳＷ３２により、三相誘導電
動機を制御する例である。ＳｉＣ静電誘導トランジスタ
は損失が小さく、冷却系を簡素化することができる。す
なわち、インバータ装置を用いたシステムの低コスト
化，高効率化が達成できる。FIG. 11 shows an example in which an inverter for driving a motor is formed using a SiC static induction transistor and a diode to which the present invention is applied. Six static induction transistors, SW11, SW12, SW2
This is an example in which a three-phase induction motor is controlled by 1, SW22, SW31, and SW32. The SiC static induction transistor has a small loss and can simplify the cooling system. That is, cost reduction and high efficiency of the system using the inverter device can be achieved.
【００３１】以上、本発明の実施例を説明したが、本発
明はさらに多くの適用範囲あるいは派生範囲をカバーす
るものである。While the embodiments of the present invention have been described above, the present invention covers a wider range of application or derivative.
【００３２】本明細書では、ＳｉＣ素子の場合のみを述
べたが、他の半導体材料にも適用できる。特に、ダイヤ
モンド，ガリウムナイトライドなどのワイドギャップ半
導体材料に有効である。In this specification, only the case of the SiC element has been described, but the present invention can be applied to other semiconductor materials. In particular, it is effective for wide gap semiconductor materials such as diamond and gallium nitride.
【００３３】本明細書では、ｎ型素子の場合のみを述べ
たが、本明細書におけるｎ型層をｐ型層に変えた素子に
も、本発明の構造は適用できる。In this specification, only the case of an n-type element has been described. However, the structure of the present invention can be applied to an element in which the n-type layer in this specification is changed to a p-type layer.
【００３４】[0034]
【発明の効果】本発明によれば、オフ特性が優れたＳｉ
Ｃ静電誘導トランジスタを実現することができる。According to the present invention, Si having excellent off-characteristics can be obtained.
A C static induction transistor can be realized.
【図１】本発明を適用したＳｉＣ静電誘導トランジスタ
の第一の実施例を示す鳥瞰図。FIG. 1 is a bird's-eye view showing a first embodiment of a SiC static induction transistor to which the present invention is applied.
【図２】従来の静電誘導トランジスタを示す鳥瞰図。FIG. 2 is a bird's-eye view showing a conventional electrostatic induction transistor.
【図３】図２のＳｉＣ静電誘導トランジスタの導通状態
での電子の流れを示す鳥瞰図。FIG. 3 is a bird's-eye view showing a flow of electrons in a conductive state of the SiC static induction transistor of FIG. 2;
【図４】図２のオフ状態での空乏層の延びを示す断面
図。FIG. 4 is a sectional view showing an extension of a depletion layer in an off state of FIG. 2;
【図５】図１のＳｉＣ静電誘導トランジスタの導通状態
での電子の流れを示す鳥瞰図。FIG. 5 is a bird's-eye view showing a flow of electrons in a conductive state of the SiC electrostatic induction transistor of FIG. 1;
【図６】図１のオフ状態での空乏層の延びを示す断面
図。FIG. 6 is a sectional view showing the extension of a depletion layer in an off state of FIG. 1;
【図７】本発明を適用したＳｉＣショットキーゲート電
界効果トランジスタの第二の実施例を示す鳥瞰図。FIG. 7 is a bird's-eye view showing a second embodiment of the SiC Schottky gate field effect transistor to which the present invention is applied.
【図８】本発明を適用したＳｉＣショットキーゲート電
界効果トランジスタの第三の実施例を示す鳥瞰図。FIG. 8 is a bird's-eye view showing a third embodiment of the SiC Schottky gate field effect transistor to which the present invention is applied.
【図９】本発明を適用したＳｉＣ静電誘導トランジスタ
の第四の実施例を示す鳥瞰図。FIG. 9 is a bird's-eye view showing a fourth embodiment of the SiC static induction transistor to which the present invention is applied.
【図１０】本発明を適用したＳｉＣ縦型静電誘導トラン
ジスタの第五の実施例を示す鳥瞰図。FIG. 10 is a bird's-eye view showing a fifth embodiment of the SiC vertical electrostatic induction transistor to which the present invention is applied;
【図１１】本発明を適用したＳｉＣ静電誘導トランジス
タを使ったインバータ装置の一実施例の主回路。FIG. 11 is a main circuit of an embodiment of an inverter device using a SiC static induction transistor to which the present invention is applied.
１…ｐ+ 型領域、２…ｎ- 型領域、３…ｎ+ 型領域、４
…ｎ+ 型領域、５…ｐ型領域、６…縦型ｐ型領域、７…
高抵抗領域、８…ｎ+ 型基板、９…埋込ｐ型領域、１１
…ソース電極、１２…ドレイン電極、１３…ゲート電
極、１４…ショットキー電極、１５…縦型ショットキー
電極、２０…ソース，ドレイン方向に対して垂直な方向
にゲート位置で切った断面、２１…電子の流れ、２２…
空乏層。1 ... p + type region, 2 ... n - type region, 3 ... n + type region, 4
... n + type region, 5 ... p type region, 6 ... vertical p type region, 7 ...
High resistance region, 8 ... n + type substrate, 9 ... embedded p-type region, 11
... Source electrode, 12 ... Drain electrode, 13 ... Gate electrode, 14 ... Schottky electrode, 15 ... Vertical Schottky electrode, 20 ... Cross section at gate position in the direction perpendicular to the source and drain directions, 21 ... The flow of electrons, 22 ...
Depletion layer.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大野 俊之 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 小野瀬 秀勝 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 Ｆターム(参考） 5F102 FB01 GB01 GB04 GD04 GJ02 GL02 GR09 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Toshiyuki Ohno 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hidekatsu Onose 7-1, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 F term in Hitachi Research Laboratory, Hitachi, Ltd. F-term (reference) 5F102 FB01 GB01 GB04 GD04 GJ02 GL02 GR09
Claims (6)
導電型の基体と、前記基体の第一主表面に形成された第
二導電型のゲート領域と、前記基体の主表面に形成され
た第一導電型のソース領域とドレイン領域と、前記基体
の、第二主表面に形成された第二導電型の基板領域と、
前記ゲート領域に接触するゲート電極と前記ソース電極
に接触するソース電極と前記ドレイン電極に接触するド
レイン電極からなる静電誘導トランジスタにおいて、ゲ
ート領域と基板領域の間にゲート領域に接触した複数の
第二導電型領域を設けたことを特徴とする静電誘導トラ
ンジスタ。1. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, a gate region of a second conductivity type formed on a first main surface of the base, and a main surface of the base A first conductivity type source region and a drain region formed in the, the substrate, the second conductivity type substrate region formed on the second main surface,
In a static induction transistor including a gate electrode in contact with the gate region, a source electrode in contact with the source electrode, and a drain electrode in contact with the drain electrode, a plurality of first electrodes in contact with the gate region between the gate region and the substrate region. An electrostatic induction transistor comprising a two-conductivity type region.
導電型の基体と、前記基体の主表面に形成された第一導
電型のソース領域とドレイン領域と、前記基体の、第二
主表面に形成された第二導電型の基板領域と、ソース領
域とドレイン領域の間にあり、前記第一導電型の基体と
ショットキー接合を形成するショットキーゲート電極と
前記ソース電極に接触するソース電極と前記ドレイン電
極に接触するドレイン電極からなるショットキーゲート
電界効果トランジスタにおいて、ショットキーゲート電
極と基板領域の間にショットキーゲート電極に接触した
複数の第二ショットキーゲート電極を設けたことを特徴
とする静電誘導トランジスタ。2. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, a source region and a drain region of a first conductivity type formed on the main surface of the base, A second conductivity type substrate region formed on the second main surface, between the source region and the drain region, the Schottky gate electrode and the source electrode forming a Schottky junction with the first conductivity type substrate In a Schottky gate field effect transistor including a source electrode in contact with and a drain electrode in contact with the drain electrode, a plurality of second Schottky gate electrodes in contact with the Schottky gate electrode are provided between the Schottky gate electrode and the substrate region. An electrostatic induction transistor, characterized in that:
導電型の基体と、前記基体の主表面に形成された第一導
電型のソース領域とドレイン領域と、前記基体の、第二
主表面に形成された第二導電型の基板領域と、ソース領
域とドレイン領域の間にあり、前記第一導電型の基体と
ショットキー接合を形成するショットキーゲート電極と
前記ソース電極に接触するソース電極と前記ドレイン電
極に接触するドレイン電極からなるショットキーゲート
電界効果トランジスタにおいて、ショットキーゲート電
極と基板領域の間にショットキーゲート電極に接触した
複数の第二導電型領域を設けたことを特徴とする静電誘
導トランジスタ。3. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, a source region and a drain region of a first conductivity type formed on the main surface of the base, A second conductivity type substrate region formed on the second main surface, between the source region and the drain region, the Schottky gate electrode and the source electrode forming a Schottky junction with the first conductivity type substrate In a Schottky gate field effect transistor including a source electrode in contact and a drain electrode in contact with the drain electrode, a plurality of second conductivity type regions in contact with the Schottky gate electrode are provided between the Schottky gate electrode and the substrate region. An electrostatic induction transistor characterized by the above-mentioned.
導電型の基体と、前記基体の第一主表面に形成された第
二導電型のゲート領域と、前記基体の主表面に形成され
た第一導電型のソース領域とドレイン領域と、前記基体
の、第二主表面に形成された高抵抗基板領域と、前記ゲ
ート領域に接触するゲート電極と前記ソース電極に接触
するソース電極と前記ドレイン電極に接触するドレイン
電極からなる静電誘導トランジスタにおいて、ゲート領
域と基板領域の間にゲート領域に接触した複数の第二導
電型領域を設けたことを特徴とする静電誘導トランジス
タ。4. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration, a gate region of a second conductivity type formed on the first main surface of the base, and a main surface of the base A source region and a drain region of the first conductivity type, a high-resistance substrate region formed on the second main surface of the base, a gate electrode in contact with the gate region, and a source in contact with the source electrode. An electrostatic induction transistor including an electrode and a drain electrode in contact with the drain electrode, wherein a plurality of second conductivity type regions in contact with the gate region are provided between the gate region and the substrate region. .
導電型の基体と、前記基体の第一主表面に形成された、
第二導電型の第一のゲート領域と、前記基体の第一主表
面に形成された第一導電型のソース領域と、前記基体の
第二主表面に形成されたドレイン領域と、前記ソース領
域と接触したソース電極と、前記ゲート領域に接触した
ゲート電極と、前記ドレイン領域に接触したドレイン電
極と、前記基体の第一主表面に露出しない埋込型の第二
導電型の第二のゲート領域からなる静電誘導トランジス
タにおいて、第一のゲート領域と第二のゲート領域の間
に、第一のゲート領域と第二のゲート領域に接触した第
二導電型領域を設けたことを特徴とする静電誘導トラン
ジスタ。5. A base of a first conductivity type having a pair of main surfaces and having a low impurity concentration and formed on a first main surface of the base.
A first gate region of a second conductivity type, a source region of a first conductivity type formed on a first main surface of the base, a drain region formed on a second main surface of the base, and the source region A source electrode in contact with the gate region, a gate electrode in contact with the gate region, a drain electrode in contact with the drain region, and a buried second conductivity type second gate not exposed on the first main surface of the base. In a static induction transistor comprising a region, a second conductivity type region in contact with the first gate region and the second gate region is provided between the first gate region and the second gate region. Static induction transistor.
流端子と直流端子と交流端子の間に接続される半導体ス
イッチング素子とを備える電力変換器において、 半導体スイッチング素子に請求項１から請求項５のうち
少なくとも一つを実施したことを特徴とする電力変換
器。6. A power converter comprising: a pair of DC terminals; a number of AC terminals equal to the number of phases; and a semiconductor switching device connected between the DC terminal and the AC terminal. A power converter characterized by implementing at least one of claims 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31431498A JP3616263B2 (en) | 1998-11-05 | 1998-11-05 | Static induction transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31431498A JP3616263B2 (en) | 1998-11-05 | 1998-11-05 | Static induction transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000150912A true JP2000150912A (en) | 2000-05-30 |
| JP3616263B2 JP3616263B2 (en) | 2005-02-02 |
Family
ID=18051868
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31431498A Expired - Fee Related JP3616263B2 (en) | 1998-11-05 | 1998-11-05 | Static induction transistor |
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| Country | Link |
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| JP (1) | JP3616263B2 (en) |
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|---|---|---|---|---|
| WO2004010489A1 (en) * | 2002-07-24 | 2004-01-29 | Sumitomo Electric Industries, Ltd. | Vertical junction field effect transistor and method for fabricating the same |
| JP2004079631A (en) * | 2002-08-12 | 2004-03-11 | Sumitomo Electric Ind Ltd | Vertical junction field effect transistor and its manufacturing method |
| DE10325748B4 (en) * | 2003-06-06 | 2008-10-02 | Infineon Technologies Ag | Junction Field Effect Transistor (JFET) with compensation structure and field stop zone |
| US20110198612A1 (en) * | 2010-02-12 | 2011-08-18 | Denso Corporation | Sic semiconductor device having cjfet and method for manufacturing the same |
-
1998
- 1998-11-05 JP JP31431498A patent/JP3616263B2/en not_active Expired - Fee Related
Cited By (12)
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|---|---|---|---|---|
| WO2004010489A1 (en) * | 2002-07-24 | 2004-01-29 | Sumitomo Electric Industries, Ltd. | Vertical junction field effect transistor and method for fabricating the same |
| JP2004063507A (en) * | 2002-07-24 | 2004-02-26 | Sumitomo Electric Ind Ltd | Vertical junction field-effect transistor and method of manufacturing the same |
| EP1542270A1 (en) * | 2002-07-24 | 2005-06-15 | Sumitomo Electric Industries, Ltd. | Vertical junction field effect transistor and method for fabricating the same |
| US7282760B2 (en) | 2002-07-24 | 2007-10-16 | Sumitomo Electric Industries, Ltd. | Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors |
| EP1542270A4 (en) * | 2002-07-24 | 2009-07-22 | Sumitomo Electric Industries | Vertical junction field effect transistor and method for fabricating the same |
| US7750377B2 (en) | 2002-07-24 | 2010-07-06 | Sumitomo Electric Industries, Ltd. | Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors |
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| JP2004079631A (en) * | 2002-08-12 | 2004-03-11 | Sumitomo Electric Ind Ltd | Vertical junction field effect transistor and its manufacturing method |
| DE10325748B4 (en) * | 2003-06-06 | 2008-10-02 | Infineon Technologies Ag | Junction Field Effect Transistor (JFET) with compensation structure and field stop zone |
| US20110198612A1 (en) * | 2010-02-12 | 2011-08-18 | Denso Corporation | Sic semiconductor device having cjfet and method for manufacturing the same |
| JP2011166025A (en) * | 2010-02-12 | 2011-08-25 | Denso Corp | Silicon carbide semiconductor device with complementary junction field effect transistor, and method of manufacturing the same |
| US8748948B2 (en) | 2010-02-12 | 2014-06-10 | Denso Corporation | SiC semiconductor device having CJFET and method for manufacturing the same |
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| Publication number | Publication date |
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| JP3616263B2 (en) | 2005-02-02 |
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