JP2000150727A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JP2000150727A JP2000150727A JP31738698A JP31738698A JP2000150727A JP 2000150727 A JP2000150727 A JP 2000150727A JP 31738698 A JP31738698 A JP 31738698A JP 31738698 A JP31738698 A JP 31738698A JP 2000150727 A JP2000150727 A JP 2000150727A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- sealing resin
- semiconductor
- semiconductor device
- dyn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
半導体装置の製造方法に関するものである。The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.
【０００２】[0002]
【従来の技術】近年、半導体装置は高集積化および高密
度化する傾向にあり、それに伴い半導体装置に搭載され
る半導体チップは配線が微細化すると共に大型化してい
る。一方、半導体チップのケースであるパッケージは安
価な樹脂封止型が多用される状況にある。また、樹脂封
止型のパッケージは、用途によって形態が多様化してい
る。この場合、熱膨張量が異なる封止樹脂と半導体チッ
プとが密着する界面には応力が発生し、半導体チップの
たとえば表面保護膜に損傷を与えることがある。そこ
で、多くの半導体メーカでは、半導体チップの表面に緩
衝膜を設けたりして応力を緩和している。2. Description of the Related Art In recent years, semiconductor devices have tended to have higher integration and higher density, and accordingly, semiconductor chips mounted on semiconductor devices have become finer and larger in wiring. On the other hand, in the case of a package which is a case of a semiconductor chip, an inexpensive resin sealing type is often used. In addition, the forms of resin-sealed packages are diversified depending on the application. In this case, stress is generated at the interface between the sealing resin having different thermal expansion and the semiconductor chip, which may damage the surface protection film of the semiconductor chip, for example. Therefore, many semiconductor manufacturers reduce the stress by providing a buffer film on the surface of the semiconductor chip.
【０００３】以下、従来の半導体装置について、図面を
参照しながら説明する。図７に示すように、複数個のボ
ンディングパッド１０１を有する半導体チップ１０２上
には封止樹脂１０３と半導体チップ１０２との間に発生
する応力を緩和するために緩衝膜１０４が形成されてい
る。また、ボンディングパッド１０１とリード１０５と
がワイヤー１０６で接続され、それらと、半導体チップ
１０２を固定するダイパッド１０７とを一体的に封止樹
脂１０３で封止している。Hereinafter, a conventional semiconductor device will be described with reference to the drawings. As shown in FIG. 7, a buffer film 104 is formed on a semiconductor chip 102 having a plurality of bonding pads 101 in order to reduce stress generated between the sealing resin 103 and the semiconductor chip 102. Further, the bonding pad 101 and the lead 105 are connected by a wire 106, and the die pad 107 for fixing the semiconductor chip 102 is integrally sealed with a sealing resin 103.
【０００４】このような封止樹脂型の半導体装置の場
合、封止樹脂１０３と半導体チップ１０２との間の応力
発生部分１０８に発生する応力を緩衝膜１０４が緩和す
る働きをして、半導体装置の特性を安定化させていた。In the case of such a sealing resin type semiconductor device, the buffer film 104 acts to relieve the stress generated in the stress generating portion 108 between the sealing resin 103 and the semiconductor chip 102, so that the semiconductor device The characteristics of were stabilized.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
構造では封止樹脂１０３が緩衝膜１０４を介して半導体
チップ１０２と密着しているため、緩衝膜の膜厚が設定
値より薄くなったり、不均一になると、半導体チップ表
面の応力の増大あるいはばらつきが生じ、半導体装置の
特性が変動し、不良となる。However, in the conventional structure, since the sealing resin 103 is in close contact with the semiconductor chip 102 via the buffer film 104, the thickness of the buffer film becomes thinner than the set value, If it is uniform, the stress on the surface of the semiconductor chip will increase or vary, and the characteristics of the semiconductor device will fluctuate, resulting in failure.
【０００６】上記に鑑みて本発明は、封止樹脂と半導体
チップとの間に発生する応力による半導体装置の特性変
動をなくすことができる半導体装置とその製造方法とを
提供するものである。In view of the above, the present invention provides a semiconductor device and a method of manufacturing the same, which can eliminate fluctuations in characteristics of the semiconductor device due to stress generated between the sealing resin and the semiconductor chip.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体装置は、
半導体チップをエポキシ系の封止樹脂で封じた半導体装
置であって、半導体チップの表面保護膜の少なくとも一
部の領域の限界表面張力が２０ｄｙｎ／ｃｍ以下であ
り、領域と封止樹脂との間に空間を有することを特徴と
し、半導体チップに封止樹脂からの応力がかからず、半
導体装置の特性変動をなくすことができる。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device in which a semiconductor chip is sealed with an epoxy-based sealing resin, wherein a critical surface tension of at least a part of a surface protection film of the semiconductor chip is 20 dyn / cm or less, and a gap between the region and the sealing resin is reduced. In this case, the semiconductor chip is not subjected to stress from the sealing resin, and the characteristics of the semiconductor device can be prevented from fluctuating.
【０００８】また本発明の半導体装置の製造方法は、半
導体ウェハまたは半導体チップの表面保護膜の少なくと
も一部の領域をプラズマアッシングし、領域の限界表面
張力を２０ｄｙｎ／ｃｍ以下にする工程と、半導体ウェ
ハまたは半導体チップを組立、封止して、領域とエポキ
シ系の封止樹脂との間に空間を形成する工程とを有する
ことを特徴とする。Further, in the method of manufacturing a semiconductor device according to the present invention, a step of plasma ashing at least a part of a surface protective film of a semiconductor wafer or a semiconductor chip to reduce a critical surface tension of the region to 20 dyn / cm or less; Assembling and sealing a wafer or a semiconductor chip to form a space between the region and the epoxy-based sealing resin.
【０００９】また本発明の半導体装置の製造方法では、
プラズマアッシングにフロロカーボンまたはフロロカー
ボン系の混合ガスを用いることが望ましい。In the method of manufacturing a semiconductor device according to the present invention,
It is desirable to use fluorocarbon or a fluorocarbon-based mixed gas for plasma ashing.
【００１０】また本発明の半導体装置の製造方法は、半
導体ウェハまたは半導体チップの表面保護膜の少なくと
も一部の領域に表面張力が２０ｄｙｎ／ｃｍ以下の液体
を塗布する工程と、半導体ウェハまたは半導体チップを
組立、封止して、領域とエポキシ系の封止樹脂との間に
空間を形成する工程とを有することを特徴とする。The method of manufacturing a semiconductor device according to the present invention also includes a step of applying a liquid having a surface tension of 20 dyn / cm or less to at least a part of a surface protective film of the semiconductor wafer or the semiconductor chip; Assembling and sealing to form a space between the region and the epoxy-based sealing resin.
【００１１】[0011]
【発明の実施の形態】以下、本発明の第１の実施の形態
について、図面を参照しながら説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
【００１２】図１は本発明の半導体装置を示す断面図で
あり、図１において、１は半導体チップ、２はボンディ
ングパッド、３はリード、４はワイヤー、５はダイパッ
ド、６はエポキシ系の封止樹脂、７は半導体チップ１と
封止樹脂６との間の空間である。所定の回路形成が終了
した半導体チップ１の複数個のボンディングパッド２と
リード３とがワイヤー４で接続され、それらと半導体チ
ップ１を固定するダイパッド５とを一体的に封止樹脂６
が封止している。半導体チップ１の表面と封止樹脂６と
の間には空間７がある。この空間７は、対向する半導体
チップ１の表面の限界表面張力が２０ｄｙｎ／ｃｍ以下
であるために、エポキシ系の封止樹脂６を用いて封止し
たときに生じるもので、封止樹脂６の環境変化による伸
縮によって発生する界面応力を半導体チップ１に伝達し
ないように設けられ、閉じた空間であることが望まし
い。FIG. 1 is a sectional view showing a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 denotes a semiconductor chip, 2 denotes a bonding pad, 3 denotes a lead, 4 denotes a wire, 5 denotes a die pad, and 6 denotes an epoxy-based seal. The stop resin 7 is a space between the semiconductor chip 1 and the sealing resin 6. A plurality of bonding pads 2 and leads 3 of the semiconductor chip 1 on which a predetermined circuit has been formed are connected by wires 4, and a die pad 5 for fixing the semiconductor chip 1 is integrally formed with a sealing resin 6.
Is sealed. There is a space 7 between the surface of the semiconductor chip 1 and the sealing resin 6. This space 7 is formed when the semiconductor chip 1 is sealed with an epoxy-based sealing resin 6 because the surface tension of the opposing surface of the semiconductor chip 1 is 20 dyn / cm or less. It is desirable to provide a closed space provided so as not to transmit the interface stress generated by expansion and contraction due to an environmental change to the semiconductor chip 1.
【００１３】また、上記目的を果たすものであれば空間
７の大きさは特に限定しないが、高さは１μｍ以下で、
できるだけ薄く、例えば応力がかかった状態でも半導体
チップの表面と封止樹脂とが接しない１０ｎｍ程度に形
成するのが望ましい。これは、あまり大きく形成する
と、パッケージの曲げ強度が低下し、プリント基板への
実装時にパッケージクラックの原因になることがあるか
らである。また、空間７を形成するのは、半導体チップ
１上の応力に対して敏感な領域、たとえば微細配線が集
中する領域やトランジスタの集積度が高い領域に限定し
て設けることもできる。The size of the space 7 is not particularly limited as long as the above purpose is achieved, but the height is 1 μm or less.
It is desirable that the semiconductor chip is formed as thin as possible, for example, about 10 nm so that the surface of the semiconductor chip does not come into contact with the sealing resin even under stress. This is because, if formed too large, the bending strength of the package is reduced, which may cause cracking of the package when mounted on a printed circuit board. The space 7 can be formed only in a region sensitive to stress on the semiconductor chip 1, for example, a region where fine wirings are concentrated or a region where the degree of integration of transistors is high.
【００１４】以下、本発明の第２の実施の形態につい
て、図面を参照しながら説明する。図２および図３は本
発明の半導体装置の製造方法を示す図であり、８はプラ
ズマアッシングガス、９は限定アッシング領域である。
その他の図面上の番号は第１の実施の形態と同一のもの
を使用している。まず図２に示すように、所定の回路形
成が終了した半導体ウェハまたはそれらを分割した半導
体チップ１をプラズマアッシングガス８で限界表面張力
が２０ｄｙｎ／ｃｍ以下になるように表面改質する。半
導体チップに限定的に空間７を形成する場合は、図３に
示すように、限定アッシング領域９以外を感光性レジス
トなどのパターンニングで保護し、非マスク部のみにプ
ラズマアッシングをして改質し、その後レジストの除去
を行う。これにより、半導体チップ１の限定アッシング
領域９のみが改質されて、後のエポキシ系の封止樹脂を
用いた樹脂封止工程で溶融した封止樹脂と結合せずに、
空間７が形成される。Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. 2 and 3 are views showing a method of manufacturing a semiconductor device according to the present invention, wherein 8 is a plasma ashing gas, and 9 is a limited ashing region.
Other numbers on the drawings are the same as those in the first embodiment. First, as shown in FIG. 2, a semiconductor wafer on which a predetermined circuit has been formed or a semiconductor chip 1 obtained by dividing the semiconductor wafer is surface-modified with a plasma ashing gas 8 so that the critical surface tension becomes 20 dyn / cm or less. When the space 7 is limitedly formed in the semiconductor chip, as shown in FIG. 3, the area other than the limited ashing area 9 is protected by patterning with a photosensitive resist or the like, and the non-mask part is modified by plasma ashing only. Then, the resist is removed. Thereby, only the limited ashing region 9 of the semiconductor chip 1 is modified, and is not combined with the sealing resin melted in the resin sealing step using the epoxy-based sealing resin later.
A space 7 is formed.
【００１５】プラズマアッシングを行うガスは、フロロ
カーボン系のガスなど、半導体チップ１の表面を限界表
面張力が２０ｄｙｎ／ｃｍ以下になるようにするガスで
あれば、その他の混合ガスでもよい。これは、半導体チ
ップ１の表面の限界表面張力は、親水性の官能基が増加
すると共に増加し、２０ｄｙｎ／ｃｍ以上になるとエポ
キシ系の封止樹脂６の親水性官能基と半導体チップ１表
面の親水性官能基とが互いに結合し始め、空間が形成し
にくくなるからである。従って、図４に示すように、半
導体チップ１の限界表面張力を２０ｄｙｎ／ｃｍ以下に
することで、組立工程でエポキシ系の封止樹脂６と半導
体チップ１とが結合せず、その間に空間７を容易に形成
できる。The gas for performing the plasma ashing may be any other mixed gas, such as a fluorocarbon gas, as long as the surface of the semiconductor chip 1 has a critical surface tension of 20 dyn / cm or less. This is because the critical surface tension of the surface of the semiconductor chip 1 increases with an increase in the number of hydrophilic functional groups. When the surface tension exceeds 20 dyn / cm, the hydrophilic surface of the semiconductor chip 1 and the hydrophilic functional groups of the epoxy-based encapsulating resin 6 increase. This is because the hydrophilic functional groups start to bond with each other, and it is difficult to form a space. Therefore, as shown in FIG. 4, by setting the critical surface tension of the semiconductor chip 1 to 20 dyn / cm or less, the epoxy-based sealing resin 6 and the semiconductor chip 1 are not bonded in the assembling process, and the space 7 therebetween. Can be easily formed.
【００１６】ただし、半導体チップ１の表面を２０ｄｙ
ｎ／ｃｍ以下に改質するときには、たとえばフロロカー
ボン単体のガスでアッシングしてしまうと、後の組立工
程でワイヤー４とボンディングパッド２との接合に接着
不良の支障が発生する場合がある。このため本発明で
は、図５に示すように、フロロカーボン系のガスに親水
性基を形成しやすい酸素ガスを２０％以下の範囲で混合
させて半導体チップ１の限界表面張力を２０ｄｙｎ／ｃ
ｍ以下に調節することが望ましい。本実施の形態では、
プラズマアッシング装置を用いて、圧力を１４００ｍｔ
ｏｒｒ、９００Ｗのパワーに設定し、ＣＦ4とＯ2のガス
を８：２の割合で混合してプラズマを発生させた。また
アッシング時間を６０ｓｅｃにすることで約１８ｄｙｎ
／ｃｍの半導体チップ１表面の限界表面張力を得た。こ
れらのアッシング条件は、限界表面張力が２０ｄｙｎ／
ｃｍ以下に半導体チップ１の表面が改質される範囲で各
々を調節できる。このように改質した表面を有する半導
体チップ１を所定の工程で組み立てて、約０．５μｍの
空間を有する半導体装置を得た。However, the surface of the semiconductor chip 1 is 20 dy.
When the reforming is performed to n / cm or less, for example, if ashing is performed using a single gas of fluorocarbon, there may be a case where a failure in bonding between the wire 4 and the bonding pad 2 occurs in a subsequent assembly process. Therefore, in the present invention, as shown in FIG. 5, the limiting surface tension of the semiconductor chip 1 is reduced to 20 dyn / c by mixing a fluorocarbon-based gas with an oxygen gas that easily forms a hydrophilic group in a range of 20% or less.
It is desirable to adjust it to m or less. In the present embodiment,
Using a plasma ashing device, set the pressure to 1400 mt
Orr was set to 900 W power, and CF 4 and O 2 gases were mixed at a ratio of 8: 2 to generate plasma. By setting the ashing time to 60 seconds, about 18 dyn
/ Cm of the surface of the semiconductor chip 1 was obtained. Under these ashing conditions, the critical surface tension is 20 dyn /
cm or less within a range where the surface of the semiconductor chip 1 is modified. The semiconductor chip 1 having the surface thus modified was assembled by a predetermined process to obtain a semiconductor device having a space of about 0.5 μm.
【００１７】以下、本発明の第３の実施の形態につい
て、図面を参照しながら説明する。図６は本発明の半導
体装置の製造方法を示す要部断面図であり、１０は表面
張力が２０ｄｙｎ／ｃｍ以下の液体、１１は限界表面張
力が２０ｄｙｎ／ｃｍ以下の層である。その他の図面上
の番号は第１の実施の形態と同一のものを使用してい
る。本実施の形態では図６（ａ）に示すように、組立工
程のワイヤーボンディング後にポッティング法によって
液体１０を塗布した。この液体１０は半導体ウェハ状態
でスピンコートしてもよく、図６（ｂ）に示す限界表面
張力が２０ｄｙｎ／ｃｍ以下の層１１を形成する。液体
１０の材質は、シリコーン変性樹脂や有機系混合材料な
ど、半導体チップ１の表面の限界表面張力が２０ｄｙｎ
／ｃｍ以下になるものであれば、特に限定はしない。例
えば、イソペンタン、エチルアミン、ジエチルエーテ
ル、１−ヘキセン、メチルアミン等を使用しても同等の
効果が得られる。ただし、これらの液体材料は、作業性
を考えてできるだけ室温における揮発性の低いものを選
択して使用することが望ましい。Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a cross-sectional view of a principal part showing a method for manufacturing a semiconductor device according to the present invention, wherein 10 is a liquid having a surface tension of 20 dyn / cm or less, and 11 is a layer having a critical surface tension of 20 dyn / cm or less. Other numbers on the drawings are the same as those in the first embodiment. In this embodiment, as shown in FIG. 6A, the liquid 10 is applied by the potting method after the wire bonding in the assembling process. The liquid 10 may be spin-coated in a semiconductor wafer state, and forms a layer 11 having a critical surface tension of 20 dyn / cm or less as shown in FIG. The liquid 10 is made of a material such as a silicone-modified resin or an organic mixed material, which has a critical surface tension of 20 dyn on the surface of the semiconductor chip 1.
/ Cm or less is not particularly limited. For example, the same effect can be obtained by using isopentane, ethylamine, diethyl ether, 1-hexene, methylamine and the like. However, it is desirable to select and use these liquid materials that are as volatile as possible at room temperature in consideration of workability.
【００１８】本実施の形態では、フッ素含有シリコーン
樹脂を使用して、約１μｍの層１１を形成した。ここで
も空間７の大きさは限定しないが、高さは１μｍ以下で
できるだけ薄く形成するのが望ましい。層１１の限界表
面張力は１８ｄｙｍ／ｃｍで、その後にエポキシ系の封
止樹脂を用いて樹脂封止を行い、半導体チップ１と封止
樹脂６との間に空間７を形成した。In this embodiment, the layer 11 having a thickness of about 1 μm is formed using a fluorine-containing silicone resin. Again, the size of the space 7 is not limited, but it is desirable that the height be 1 μm or less and be formed as thin as possible. The critical surface tension of the layer 11 was 18 dym / cm. Thereafter, resin sealing was performed using an epoxy-based sealing resin to form a space 7 between the semiconductor chip 1 and the sealing resin 6.
【００１９】[0019]
【発明の効果】以上のように本発明の半導体装置は、半
導体チップとエポキシ系の封止樹脂との間に空間がある
ために、封止樹脂と半導体チップの間で発生する応力を
なくすことができ、応力による半導体装置の特性変動を
防ぐことができる。As described above, in the semiconductor device of the present invention, since there is a space between the semiconductor chip and the epoxy-based sealing resin, the stress generated between the sealing resin and the semiconductor chip is eliminated. Accordingly, it is possible to prevent the characteristics of the semiconductor device from fluctuating due to the stress.
【００２０】また、本発明の半導体装置の製造方法は、
半導体チップの表面をアッシングによって改質するた
め、後の組立工程で半導体チップとエポキシ系の封止樹
脂との空間を容易に形成することができる。Further, a method of manufacturing a semiconductor device according to the present invention
Since the surface of the semiconductor chip is modified by ashing, a space between the semiconductor chip and the epoxy-based sealing resin can be easily formed in a later assembly process.
【００２１】また、本発明の半導体装置の製造方法は、
表面張力が２０ｄｙｎ／ｃｍ以下の液体を塗布すること
で半導体チップ表面に限界表面張力が２０ｄｙｎ／ｃｍ
以下の層が形成されるため、後の組立工程で半導体チッ
プとエポキシ系の封止樹脂との間に空間を容易に形成す
ることができる。Further, the method of manufacturing a semiconductor device according to the present invention
By applying a liquid having a surface tension of 20 dyn / cm or less, a critical surface tension of 20 dyn / cm is applied to the semiconductor chip surface.
Since the following layers are formed, a space can be easily formed between the semiconductor chip and the epoxy-based sealing resin in a later assembly process.
【図１】本発明の第１の実施の形態における半導体装置
の要部断面を示す図FIG. 1 is a view showing a cross section of a main part of a semiconductor device according to a first embodiment of the present invention;
【図２】本発明の第２の実施の形態における半導体装置
の製造方法を示す図FIG. 2 is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;
【図３】本発明の第２の実施の形態における半導体装置
の製造方法を示す図FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to a second embodiment of the present invention;
【図４】本発明の第２の実施の形態における半導体チッ
プの限界表面張力と剥離発生率との関係を示す図FIG. 4 is a diagram showing a relationship between a critical surface tension of a semiconductor chip and a rate of occurrence of peeling according to a second embodiment of the present invention.
【図５】本発明の第２の実施の形態におけるフロロカー
ボンに対する酸素混合比と半導体チップの限界表面張力
との関係を示す図FIG. 5 is a diagram showing a relationship between an oxygen mixture ratio to fluorocarbon and a critical surface tension of a semiconductor chip according to a second embodiment of the present invention.
【図６】本発明の第３の実施の形態における半導体装置
の製造方法を示す図FIG. 6 is a diagram illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention.
【図７】従来の半導体装置の要部断面を示す図FIG. 7 is a diagram showing a cross section of a main part of a conventional semiconductor device.
１ 半導体チップ ２ ボンディングパッド ３ リード ４ ワイヤー ５ ダイパッド ６ 封止樹脂 ７ 半導体チップと封止樹脂との空間 ８ プラズマアッシングガス ９ 限定アッシング領域 １０ 液体 １１ 層 Reference Signs List 1 semiconductor chip 2 bonding pad 3 lead 4 wire 5 die pad 6 sealing resin 7 space between semiconductor chip and sealing resin 8 plasma ashing gas 9 limited ashing region 10 liquid 11 layer
Claims (4)
封じた半導体装置であって、前記半導体チップの表面保
護膜の少なくとも一部の領域の限界表面張力が２０ｄｙ
ｎ／ｃｍ以下であり、前記領域と前記封止樹脂との間に
空間を有することを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip is sealed with an epoxy-based sealing resin, wherein a critical surface tension of at least a part of a surface protection film of the semiconductor chip is 20 dy.
n / cm or less and a space between the region and the sealing resin.
保護膜の少なくとも一部の領域をプラズマアッシング
し、前記領域の限界表面張力を２０ｄｙｎ／ｃｍ以下に
する工程と、前記半導体ウェハまたは前記半導体チップ
を組立、封止して、前記領域とエポキシ系の封止樹脂と
の間に空間を形成する工程とを有することを特徴とする
半導体装置の製造方法。2. A step of performing plasma ashing on at least a part of a surface protective film of a semiconductor wafer or a semiconductor chip to reduce a critical surface tension of the region to 20 dyn / cm or less, and assembling the semiconductor wafer or the semiconductor chip. Forming a space between the region and an epoxy-based sealing resin.
ンまたはフロロカーボン系の混合ガスを用いることを特
徴とする請求項２に記載の半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein a fluorocarbon or a fluorocarbon-based mixed gas is used for said plasma ashing.
保護膜の少なくとも一部の領域に表面張力が２０ｄｙｎ
／ｃｍ以下の液体を塗布する工程と、前記半導体ウェハ
または前記半導体チップを組立、封止して、前記領域と
エポキシ系の封止樹脂との間に空間を形成する工程とを
有することを特徴とする半導体装置の製造方法。4. A semiconductor wafer or a semiconductor chip having a surface tension of 20 dyn on at least a part of a surface protective film thereof.
/ Cm or less, and assembling and sealing the semiconductor wafer or the semiconductor chip to form a space between the region and an epoxy-based sealing resin. Manufacturing method of a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31738698A JP2000150727A (en) | 1998-11-09 | 1998-11-09 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31738698A JP2000150727A (en) | 1998-11-09 | 1998-11-09 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000150727A true JP2000150727A (en) | 2000-05-30 |
Family
ID=18087682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31738698A Pending JP2000150727A (en) | 1998-11-09 | 1998-11-09 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000150727A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005510084A (en) * | 2001-11-23 | 2005-04-14 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device and method for enclosing an integrated circuit |
-
1998
- 1998-11-09 JP JP31738698A patent/JP2000150727A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005510084A (en) * | 2001-11-23 | 2005-04-14 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Semiconductor device and method for enclosing an integrated circuit |
| JP2010147500A (en) * | 2001-11-23 | 2010-07-01 | Taiwan Semiconductor Manufacturing Co Ltd | Semiconductor device |
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