CN100474543C - Semiconductor device and method of making the same - Google Patents
Semiconductor device and method of making the same Download PDFInfo
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- CN100474543C CN100474543C CNB2006101517025A CN200610151702A CN100474543C CN 100474543 C CN100474543 C CN 100474543C CN B2006101517025 A CNB2006101517025 A CN B2006101517025A CN 200610151702 A CN200610151702 A CN 200610151702A CN 100474543 C CN100474543 C CN 100474543C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Abstract
A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device ( 150 ) has a semiconductor chip provided with electrodes ( 158 ), a resin layer ( 152 ) forming a stress relieving layer provided on the semiconductor chip, wiring ( 154 ) formed from the electrodes ( 158 ) to over the resin layer ( 152 ), and solder balls ( 157 ) formed on the wiring ( 154 ) over the resin layer ( 152 ); the resin layer ( 152 ) is formed so as to have a depression ( 152 a) in the surface, and the wiring ( 154 ) is formed so as to pass over the depression ( 152 a).
Description
The application is that denomination of invention is " semiconductor device and manufacture method thereof, circuit substrate and electronic equipment ", the applying date to be that December 4, application number in 1997 are dividing an application of 97192033.8 applications.
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, circuit substrate and electronic equipment, particularly, relate to semiconductor device and manufacture method, circuit substrate and the electronic equipment of package dimension near chip size.
Background technology
When pursuing the semiconductor device high-density packages, the nude film encapsulation is desirable., nude film is difficult to guarantee product quality and processing.So, developed encapsulation CSP (chip scale package) near chip size.
In semiconductor device, as a kind of scheme, have the flexible substrate of having made figure is set on active face one side of semiconductor chip, and on this flexible substrate, form the scheme of a plurality of outer electrodes with the CSP type of various solution developments.In addition, everybody also knows, injects resin between the active face of semiconductor chip and flexible substrate, in the hope of absorbing thermal stress.
But, only can not fully absorb under the occasion of thermal stress with resin, other way is just necessary.
Summary of the invention
The present invention solves above-mentioned this problem, and its purpose is to provide a kind of package dimension near chip size, except that so-called stress absorbing layer, can absorb semiconductor device and manufacture method, circuit substrate and the electronic equipment of thermal stress effectively.
The manufacture method of semiconductor device of the present invention has:
Preparation has formed the operation of the wafer of electrode;
At least a portion of avoiding above-mentioned electrode is provided with the operation of the 1st stress-buffer layer on above-mentioned wafer;
Form the operation of the 1st conducting portion up to above-mentioned the 1st stress-buffer layer from above-mentioned electrode;
Form the operation of the outer electrode that is connected with above-mentioned the 1st conducting portion in the top of above-mentioned the 1st stress-buffer layer; And
Above-mentioned wafer is cut into the operation of each small pieces;
With the operation that above-mentioned the 1st stress-buffer layer is set and at least one operation that forms in above-mentioned the 1st conducting portion operation, form the structure that makes stress relax increase.
According to the present invention, owing on stress-buffer layer, form conducting portion and outer electrode, so do not need the substrate of the film that sets in advance outer electrode and made figure etc.
And the conducting portion of connection electrode and outer electrode is owing to can be freely formed according to design, so the not configuration of pipe electrode and determine the configuration of outer electrode.Thereby, even do not change the circuit design of the device that forms on the wafer, also can make the different various semiconductor devices in outer electrode position simply.
And then, according to the present invention,, obtain each semiconductor device so can cut off wafer owing on wafer, form stress-buffer layer, conducting portion and outer electrode.Therefore, owing to carry out the formation of stress-buffer layer, conducting portion and outer electrode simultaneously to many semiconductor devices, so can simplify manufacturing process.
As making above-mentioned stress relax the structure that strengthens, also can on above-mentioned the 1st stress buffer laminar surface, form recess, and form above-mentioned the 1st conducting portion, make it pass through the top of above-mentioned recess.
Like this,, absorb stress, prevent broken string so can change with case of bending owing to the surface of counter stress resilient coating forms conducting portion to crisscross bending.
As strengthening the structure that above-mentioned stress relaxes, also can be in the operation that forms above-mentioned the 1st conducting portion, the in-plane on above-mentioned the 1st stress-buffer layer is bent to form above-mentioned first conducting portion.
Can also be included in the operation of filled elastomer on above-mentioned the 1st conducting portion that is positioned at above-mentioned recess.Further absorb stress with this elastomer.
Can also be included on above-mentioned the 1st stress-buffer layer that has formed above-mentioned the 1st conducting portion, the operation of the 2nd stress-buffer layer and the 2nd conducting portion that is connected with above-mentioned the 1st conducting portion is set.
Like this, stress-buffer layer has been formed multistage, stress is further disperseed.
Also can form at least 1 conducting portion among above-mentioned the 1st conducting portion and above-mentioned the 2nd conducting portion and have the planar of the planar extension also bigger than thickness.
Like this, owing near transmission signals planar earthing potential, so become desirable drive access.
In the top of above-mentioned the 1st stress-buffer layer that has formed above-mentioned the 1st conducting portion, the 2nd stress-buffer layer and the 2nd conducting portion are set;
In the top of above-mentioned the 2nd stress-buffer layer that has formed above-mentioned the 2nd conducting portion, the 3rd stress-buffer layer and the 3rd conducting portion are set;
Above-mentioned the 2nd conducting portion is formed wire, and the above-mentioned the 1st and the 3rd conducting portion is formed planar, it is had than the also big planar extension of above-mentioned the 2nd conducting portion.
Like this, because the 2nd conducting portion that wire is formed is clipped in the middle of a pair of planar conducting portion, so become around the wiring covering with ground connection.So, obtain the structure same with coaxial cable, just becoming through the signal of the 2nd conducting portion is difficult to be subjected to the influence of noise.
Also can clip a pair of wiring that above-mentioned first conducting portion forms abreast becomes earthing potential.Like this, clipped with a pair of wiring, make around the wiring covering with ground connection owing to form first conducting portion of wire.Like this, just obtain the structure same with coaxial cable, signal just becomes and is difficult to be subjected to the influence of noise.
Semiconductor device of the present invention has:
Semiconductor chip with electrode;
On above-mentioned semiconductor chip, avoid the 1st stress-buffer layer that at least a portion of above-mentioned electrode is provided with;
From above-mentioned electrode on above-mentioned the 1st stress-buffer layer and the 1st conducting portion that forms; And
Be positioned at above-mentioned the 1st stress-buffer layer above above-mentioned the 1st conducting portion on the outer electrode that forms,
Above-mentioned the 1st stress-buffer layer is formed, make it have recess from the teeth outwards, and through forming above-mentioned the 1st conducting portion on the above-mentioned recess.
Like this,, formed, absorb stress so can change, and prevent broken string with case of bending to the direction bending that intersects owing to make the surface of conducting portion counter stress resilient coating.
Also can elastomer be set being positioned on above-mentioned the 1st conducting portion of above-mentioned recess, make it to be filled in the recess.
Above-mentioned the 1st conducting portion also can form on above-mentioned the 1st stress-buffer layer agley.
Above-mentioned the 1st conducting portion also can form accordion-like.
Can also form on above-mentioned the 1st stress-buffer layer of above-mentioned the 1st conducting portion, have the 2nd stress-buffer layer and the 2nd conducting portion that is connected with the 1st conducting portion.
Like this, just stress-buffer layer has been formed multistage, further dispersive stress becomes easily.
Also can make the side among 2 conducting portions that are made of above-mentioned the 1st conducting portion and the 2nd conducting portion make wire, the opposing party forms has the planar of the planar extension wideer than the conducting portion of above-mentioned wire.
Also can make above-mentioned planar conducting portion is earthing potential, and signal is input in the conducting portion of above-mentioned wire.
Also can have: forming the 2nd stress-buffer layer and the 2nd conducting portion that is provided with on above-mentioned the 1st stress-buffer layer of above-mentioned the 1st conducting portion; And
The 3rd stress-buffer layer that on the 2nd stress-buffer layer that has formed the 2nd conducting portion, is provided with and the 3rd conducting portion,
Above-mentioned the 2nd conducting portion is formed wire, and that the above-mentioned the 1st and the 3rd conducting portion forms is planar, makes it have the expansion on the plane also bigger than above-mentioned the 2nd conducting portion.
Like this, the 2nd conducting portion that forms owing to wire ground is sandwiched in the middle of a pair of planar conducting portion, so the wiring that becomes to being grounded current potential is on every side covered.Therefore, obtain the structure same with coaxial cable, becoming through the signal of the 2nd conducting portion is difficult to be subjected to the influence of noise.
Also can form concurrently and make it to clip above-mentioned the 1st conducting portion, and have a pair of wiring that becomes earthing potential.
Like this, the 1st conducting portion that wire ground forms covers so be grounded the wiring of current potential around becoming owing to pick up with a pair of wiring.Therefore, obtain the structure same with coaxial cable, signal becomes and is difficult to be subjected to the influence of noise.
Also can have radiator having on the opposite side of the face of above-mentioned electrode with above-mentioned semiconductor chip.
The above-mentioned semiconductor device of encapsulation on circuit substrate of the present invention.
Electronic equipment of the present invention has this circuit substrate.
Description of drawings
Figure 1A～Fig. 1 E is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 2 A～Fig. 2 E is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 3 A～Fig. 3 D is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 4 A～Fig. 4 C is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 5 is the semiconductor device plane graph that expression becomes prerequisite of the present invention;
Fig. 6 A～Fig. 6 C is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 7 A～Fig. 7 C is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 8 A～Fig. 8 D is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Fig. 9 A～Fig. 9 D is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Figure 10 is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Figure 11 A～Figure 11 D is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Figure 12 A～Figure 12 C is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Figure 13 A～Figure 13 D is the figure that the manufacture method of the semiconductor device that becomes prerequisite of the present invention is described;
Figure 14 A～Figure 14 D is the figure of the semiconductor device of expression the 1st embodiment of the present invention;
Figure 15 is the figure of the semiconductor device of expression the 2nd embodiment;
Figure 16 is the figure of the semiconductor device of expression the 3rd embodiment;
Figure 17 A and Figure 17 B are the figure of manufacture method of the semiconductor device of explanation the 3rd embodiment;
Figure 18 A and Figure 18 B are the figure of manufacture method of the semiconductor device of explanation the 3rd embodiment;
Figure 19 A and Figure 19 B are the figure of manufacture method of the semiconductor device of explanation the 3rd embodiment;
Figure 20 A and Figure 20 B are the figure of manufacture method of the semiconductor device of explanation the 3rd embodiment;
Figure 21 is illustrated in to use illustration of the present invention in the electronic unit of surface encapsulation;
Figure 22 is illustrated in to use illustration of the present invention in the electronic unit of surface encapsulation;
Figure 23 is illustrated in to have used the illustration that has formed protective layer on the semiconductor device of the present invention;
Figure 24 is illustrated in to have used the illustration that radiator has been installed on the semiconductor device of the present invention;
Figure 25 is the figure that the circuit substrate of the electronic unit of using method manufacturing of the present invention is installed in expression;
Figure 26 is the electronic equipment that expression has the circuit substrate that assembles the electronic unit of using method manufacturing of the present invention.
Embodiment
Before explanation most preferred embodiment of the present invention, explanation is as the technology of prerequisite of the present invention earlier.
(the 1st prerequisite technology)
Fig. 5 is the plane graph that expression becomes the semiconductor device of prerequisite of the present invention.This semiconductor device is the device that is classified among the so-called CSP, so from the electrode 12 of semiconductor chip 1, form wiring 3 to the center direction of active face 1a, and be provided with outer electrode 5 in each wiring 3.Because whole outer electrodes 5 all are located at the top of stress-buffer layer 7, be assembled to the stress mitigation of circuit substrate (scheme not shown) when going up so can reach.And, externally on the electrode 5, form anti-flux layer 8 as diaphragm.
Also have, as shown in the drawing, on the active region (having formed the zone of active device) of semiconductor chip 1, rather than on the electrode 12 of semiconductor chip 1, outer electrode 5 is set.Because stress-buffer layer 7 is set on active region, laying-out and wiring 3 (introducing) in active region again is so can be set to outer electrode 5 in the active region.Therefore, when configuring external electrode 5, become, promptly, greatly increase the degree of freedom of setting outer electrode 5 positions as the zone of regulation area to providing in the source region.
And, adopt the way that makes wiring 3 bendings in the top of stress-buffer layer 7, outer electrode 5 is arranged to clathrate arranges.And at the junction surface of electrode 12 with wiring 3, the size of the electrode 12 that has illustrated and wiring 3 sizes are though become
Wiring 3＜electrode 12
But also can make
Particularly, become
Occasion under, 3 the resistance value of not only connecting up reduces, and also gains in strength to prevent broken string.
Figure 1A～Fig. 4 C is the figure of manufacture method of the semiconductor device of explanation the 1st prerequisite technology, and is corresponding with the I-I line section of Fig. 5.
At first, according to well-known technology, usually, on wafer 10, form electrode 12 and other device.Also in this example, form electrode 12 with aluminium.As the example except that electrode 12, also can be with the material (for example, aluminium silicon or aluminium copper silicon etc.) of aluminium alloy system.
And,, on the surface of wafer 10, form the passivating film (scheming not shown) that constitutes by oxide-film etc. in order to prevent variation chemically.Passivating film is not only avoided electrode 12, and the line that will avoid cutting forms.Owing in line, do not form passivating film, thus generation dust can avoid cutting the time, and then, can prevent breaking of passivating film.
Shown in Figure 1A like that, on wafer 10, apply photosensitive polyimide resin with electrode 12, form (for example using spin-coating method) resin bed 14.Resin bed 14, with the scope of 1～100 μ m, it is desirable that best thickness with about 10 μ m forms.Also have, owing to use spin-coating method, it is a lot of to become useless polyimide resin, thereby also can use the device with the banded ejection of pump polyimide resin.As such device, the FAS ultraprecise ejection type application system that FAS company makes (with reference to No. the 4696885th, United States Patent (USP)) etc. is for example arranged.
Shown in Figure 1B like that, on resin bed 14, form contact hole 14a for electrode 12.Specifically, through overexposure, develop and cure processing, and near electrode 12, remove polyimide resin, so on resin bed 14, form contact hole 14a.Again on figure, when having formed contact hole 14a, resin bed 14 does not have residual and electrode 12 overlapping areas fully.Because on electrode 12, there is not cull layer 14 fully, thus below after the operation, though have and the metal of set wiring etc. between electrically contact the advantage that becomes kilter, not necessarily must make such structure.That is, near the structure that will make as resin bed 14 periphery of electrode 12 if having formed the hole exposes the part of electrode 12, just achieves the goal fully.Under these circumstances, because the minimizing of the number of bends of wiring layer, so can prevent to wait the wiring reliability decrease that causes because of broken string.Here, contact hole 14a has tapering.And the end forming contact hole 14a has been formed obliquely resin bed 14.Form such shape by the condition of setting exposure and develop.And then, if to carrying out O on the electrode 12
2Plasma treatment even for example residual on electrode 12 have some polyimide resins, also can be removed this polyimide resin fully.In the semiconductor device as manufactured goods, the resin bed 14 of Xing Chenging has just become stress-buffer layer like this.
Also have, in this example,, also can use the photostability resin though aspect resin, used the photosensitive polyimide resin.For example use silicone modified polyimide resin, epoxy resin or silicone modified epoxy resin etc., low (1 x 10 of Young's modulus during curing
10Pa is following), the material that plays the stress buffer effect is good.
Shown in Fig. 1 C like that, use sputtering method, on whole wafer 10, form chromium (Cr) layers 16.On resin bed 14, all form chromium (Cr) layer 16 from electrode 12.Here, selected the material of chromium (Cr) layer 16, be because and the tack that constitutes between the polyimides of resin bed 14 good.Perhaps, if consider anti-crackle, also can be with the aluminium alloy or the copper alloy that resemble aluminium or aluminium silicon, aluminum bronze etc., or copper or the such malleable metal of gold.Perhaps, if select the good titanium of moisture-proof, then can prevent the broken string that takes place because of etching.Titanium, from and polyimides between the viewpoint of tack also be desirable, also can use titanium tungsten.
Consider with chromium (Cr) layers 16 between tack the time, it is desirable then making the surperficial chap roughening of the resin bed 14 of formation such as polyimides.For example, by being exposed to plasma (O
2, CF
4) in dry process and the wet treatment of acid or alkali, just can make the surface roughening of resin bed 14.
In contact hole 14a,, in this zone, equally also be formed obliquely chromium (Cr) layer 16 because the end of resin bed 14 tilts.In the semiconductor device as finished product, chromium (Cr) layer 16 has become wiring 3 (with reference to Fig. 5), simultaneously in manufacture process, and the diffusion impervious layer of the polyimide resin when after this becoming to cambium layer.In addition, also be not limited to chromium (Cr) as diffusion impervious layer, above-mentioned wiring material is all effective.
Shown in Fig. 1 D like that, on chromium (Cr) layer 16, apply resist and form resist layer 18.
Shown in Fig. 1 E like that, through overexposure, develop and cure processing, remove the part of resist layer 18.The resist layer 18 that stays is formed from electrode 12 towards resin bed 14 center direction.In detail, in the top of resin bed 14, the resist layer that stays 18 structures are, make one on the electrode 12 resist layer 18 and the resist layer 18 discontinuous (becoming separately independently state) on another electrode 12.
And, only stay the zone (being mask promptly) that is covered with by the contact resist layer 18 shown in Fig. 1 E with resist layer 18, etching chromium (Cr) layer 16, and peel off resist layer 18.More than, in these preceding operations, use the metallic film formation technology in the wafer process process exactly.And the chromium after the etching (Cr) layer 16 just becomes the appearance shown in Fig. 2 A.
In Fig. 2 A, from electrode 12 to resin bed 14, all formed chromium (Cr) layer 16.In detail, chromium (Cr) layer 16 constitutes, and makes between one electrode 12 and another electrode 12 discontinuous.Just, resemble and to constitute the wiring corresponding and be made like chromium (Cr) layer 16 with each self-electrode 12.
Shown in Fig. 2 B like that, the top in the superiors of containing chromium (Cr) layer 16 at least forms copper (Cu) layer 20 with sputtering method.Copper (Cu) layer 20 becomes the bottom that is used to form outer electrode.Perhaps, also can form nickel (Ni) layer, to replace copper (Cu) layer 20.
Shown in Fig. 2 C like that, the top at copper (Cu) layer 20 forms resist layer 22, shown in Fig. 2 D like that, expose, develop and cure processing, and remove the part of resist layer 22.So, the zone of removing is exactly the top of resin bed 14, and, at least a portion of having removed the resist layer 22 that is positioned at chromium (Cr) layer 16 top.
Shown in Fig. 2 E like that, removing on the zone of resist layer 22 in part, form pedestal 24.Pedestal 24 forms with copper facing (Cu) method, forms solder ball on it.And pedestal 24 is formed on the top of copper (Cu) layer 20, by copper (Cu) layer 20 and chromium (Cr) layer 16 and electrode 12 conductings.
As shown in Figure 3A, in the top of pedestal 24, thick-layer shape ground forms the scolder that will become solder ball 26 as outer electrode 5 (with reference to Fig. 5).Wherein, thickness will be thus back amount of solder corresponding when solder ball forms with desired sphere diameter decide.The layer of scolder 26 is with formation such as electrolytic plating method or method for printing.
Shown in Fig. 3 B, peel off the resist layer 22 shown in Fig. 3 A, etch copper (Cu) layer 20.So, pedestal 24 just becomes mask, and only the following copper (Cu) of this pedestal 24 layer 20 stays (with reference to Fig. 3 C).And, use the liquid return method, the scolder on the pedestal 24 26 is shortened into sphere more than the hemisphere, make solder ball (with reference to Fig. 3 D).
By above operation, formed solder ball as outer electrode 5 (with reference to Fig. 5).Then, shown in Fig. 4 A and Fig. 4 B like that, carry out for the oxidation that prevents chromium (Cr) layer 16 grade, improve in the completed semiconductor device moisture-proof or for the processing of the purposes such as mechanical protection that reach the surface.
Shown in Fig. 4 A, on whole wafer 10, form photosensitive anti-flux layer 28 with cladding process.And, expose, develop and cure processing, remove among the anti-flux layer 28, applied the part of scolder 26 and near zone thereof.And, the anti-flux layer 28 that stays, as the oxidation barrier film, the diaphragm when becoming final semiconductor device also, or and then to become to improve moisture resistance be the diaphragm of purpose.Then, carry out the detection of electrical characteristic, if necessary then the print product label, make name etc.
Then, carry out scribing, shown in figure C, cutting off becomes each semiconductor device.Here, carry out the position of scribing, comparison diagram 4B and Fig. 4 C are just clear, are the positions of avoiding resin bed 14.And, owing to only wafer 10 is carried out scribing, so the problem can avoid cutting off a plurality of layers of the different material formation of do as one likes matter time.Carry out the scribing operation according to existing method.
And, if adopt formed semiconductor device, then because resin bed 14 has become stress-buffer layer 7 (with reference to Fig. 5), the stress that has caused so relaxed the differing from of thermal coefficient of expansion between circuit substrate (scheming not shown) and the semiconductor chip 1 (with reference to Fig. 5).
If adopt the manufacture method of the semiconductor device of above explanation, then almost finish whole operations in the wafer process process.In other words, also can form the operation of the outside terminal that is connected with base plate for packaging, become in the wafer process process and carried out, handle existing packaging process, be each semiconductor chip, and each semiconductor chip do not carried out leading wire bonding operation, outside terminal formation operation etc. respectively.And, when forming stress-buffer layer, do not need the substrate of the film of having made figure etc.Since these reasons, the high-quality semiconductor device so can obtain low-cost.
In this example, be the photosensitive polyimide resin though supposition is used as the resin of stress-buffer layer, in addition, also can use the non-photosensitive resin.And, in this example, also can be provided with the wiring layer more than two layers.If make ply, usually can increase bed thickness, and can reduce the cloth line resistance.Particularly, the one deck among the wiring is being made under the situation shape of chromium (Cr),, can reduce the cloth line resistance by making it combination because copper (Cu) or golden resistance ratio chromium (Cr) are low.Perhaps, also can on stress-buffer layer, form titanium layer, on this titanium layer, form nickel dam, or form the layer of forming by platinum and gold.Perhaps, also can make wiring with platinum and the two-layer of gold.
(the 2nd prerequisite technology)
Fig. 6 A～Fig. 7 C is the figure of manufacture method of the semiconductor device of explanation the 2nd prerequisite technology.Present technique is compared with the 1st prerequisite technology, becomes difference in the later operation of Fig. 3 A, and same to operation and the 1st prerequisite technology of Fig. 2 E.And, wafer 110 shown in Fig. 6 A, electrode 112, resin bed 114, chromium (Cr) layer 116, copper (Cu) layer 120, resist layer 122 and pedestal 124, same with the wafer 10 shown in Fig. 2 E, electrode 12, resin bed 14, chromium (Cr) layer 16, copper (Cu) layer 20, resist layer 22 and pedestal 24, because manufacture method is also same with the method shown in Figure 1A～Fig. 2 E, so explanation is omitted.
In present technique, as shown in Figure 6A,, electroplate thin scolder 126, and peel off resist layer 122 in the top of pedestal 124, make that appearance as Fig. 6 B.And then, be diaphragm with thin scolder 126, shown in Fig. 6 C, copper (Cu) layer 120 is carried out etching.
Then, shown in Fig. 7 A, on whole wafer 110, form anti-flux layer 128, and for example shown in Fig. 7 B, with exposing, develop and curing the anti-flux layer 128 that processing method is removed pedestal 124 zones.
And shown in Fig. 7 C, the thick scolder 129 thicker than thin scolder 126 electroplated in the top of the pedestal 124 that stays at thin scolder 126.This is carried out it with non-electrolytic plating method.Then, with the liquid method that bounces back, thick scolder 129 is made and the sphere more than the hemisphere similarly of the state shown in Fig. 3.And thick scolder 129 becomes the solder ball as outer electrode 5 (with reference to Fig. 5).After this operation, just same with the 1st above-mentioned prerequisite technology.
Adopt present technique, also can in the wafer process process, carry out most operation.In addition, in present technique, form thick scolder 129 with non-electrolytic plating method.And, can save pedestal 124, and directly form thick scolder 129 in the top of copper (Cu) layer 120.
(the 3rd prerequisite technology)
Fig. 8 A～Fig. 9 D is the figure of explanation about the manufacture method of the semiconductor device of the 3rd prerequisite technology.
And, with exposing, develop and curing processing method, remove the part of the resist layer 42 shown in Fig. 8 A.In detail, shown in Fig. 8 B, only stay the resist layer 42 of the top that is positioned at chromium (Cr) layer 36 that becomes wiring, and remove the resist layer 42 of other positions.
Then, copper (Cu) layer 40 is carried out etching and peels off resist layer 42, shown in Fig. 8 C, only stay copper (Cu) layer 40 in the top of chromium (Cr) layer 36.And, form the wiring that the two-layer structure by chromium (Cr) layer 36 and copper (Cu) layer 40 forms.
Secondly, shown in Fig. 8 D, apply photosensitive anti-solder flux and form anti-flux layer 44.
Shown in Fig. 9 A, show formation contact hole 44a at anti-flux layer 44.Contact hole 44a above resin bed 34, is formed on copper (Cu) layer 40 as the wiring list surface layer of two-layer structure.In addition, the formation of contact hole 44a is with exposing, develop and curing processing method and carry out.Perhaps, also can form contact hole 44a like this, on the assigned position limit limit, hole is set and print anti-solder flux.
Then, on contact hole 44a, print welding paste 46 (with reference to Fig. 9 B), make it to make the shape of projection.This welding paste 46 with the liquid method that bounces back, shown in Fig. 9 C, becomes solder ball.And, carry out scribing, and obtain each semiconductor device shown in Fig. 9 D.
In present technique, by saving the pedestal of solder ball, and use the method for printing of welding paste, thus make the formation facilitation of solder ball, simultaneously, also related reduction manufacturing process.
Also have, the wiring of semiconductor device of manufacturing is the two layers of wiring of chromium (Cr) and copper (Cu).Here, chromium (Cr) is good with the tack of the resin bed 34 that is made of polyimide resin, and the anti-crackle of copper (Cu) is good.Because anti-crackle is good, so can prevent the broken string that connects up or the damage of electrode 32 and active device.Perhaps, also can use two-layer or chromium, copper (Cu) and gold three layers of two-layer, the chromium of copper (Cu) and gold and gold to constitute connects up.
In present technique,, self-evidently also pedestal can be set though enumerated the example of no pedestal.
(the 4th prerequisite technology)
Figure 10 is the figure of manufacture method of the semiconductor device of explanation the 4th prerequisite technology.
This wafer that illustrates 130, electrode 132, resin bed 134, chromium (Cr) layer 136, copper (Cu) layer 140 and anti-flux layer 144, same with the wafer 30 shown in Fig. 9 A, electrode 32, resin bed 34, chromium (Cr) layer 36, copper (Cu) layer 40 and anti-flux layer 44, because manufacture method is same with Fig. 8 A～Fig. 9 A also, so illustrate and be omitted.
In present technique, in Fig. 9 B, be that coated with flux 146 is carried solder balls 148, to replace with welding paste 46 on the contact hole 144a that forms on the anti-flux layer 144.Then, carry out liquid retraction, detection, marking and scribing operation.
If the employing present technique is then carried preformed solder ball 148, be made into outer electrode 5 (with reference to Fig. 5).And, compare with the 1st and the 2nd prerequisite technology, can save pedestal 24,124.Also have, wiring 3 (with reference to Fig. 5) have become the two-layer structure of chromium (Cr) 136 and copper (Cu) layer 140.
In present technique,, self-evidently also pedestal can be set though enumerate the example of no pedestal.
(the 5th prerequisite technology)
Figure 11 A～Figure 12 C is the figure of manufacture method of the semiconductor device of explanation the 5th prerequisite technology.
At first, shown in Figure 11 A, on wafer 50 with electrode 52, adhesive glass plate 54.On glass plate 54, form the hole 54a corresponding with the electrode 52 of wafer 50, and coated with adhesive 56.
The thermal coefficient of expansion of this glass plate 54 becomes the value between the thermal coefficient of expansion of circuit substrate of the thermal coefficient of expansion of wafer 50 of semiconductor chip and assembling semiconductor device.Therefore, by the value of the order change thermal coefficient of expansion of the circuit substrate (scheme not shown) that wafer 50 is carried out semiconductor chip, glass plate 54 and assembling semiconductor device that scribing obtains, so dwindle and thermal stress also reduces in the difference of the thermal coefficient of expansion of connecting portion.Just, glass plate 54 is a stress-buffer layer.In addition, if having same thermal coefficient of expansion, also can replace glass plate 54 with potsherd.
And, if glass plate 54 is adhered on the wafer 50, then use O
2Plasma processing method is removed the adhesive 56 that enters among the 54a of hole, makes that appearance shown in Figure 11 B.
Secondly, shown in Figure 11 C, be exactly that whole wafer 50 is on glass plate 54, with sputtering method formation aluminium lamination 58.Then, when on the surface of hole 54a, forming film, seek the aluminium that protective ratio is easier to break.Secondly, shown in Figure 12 A, form resist layer 59, shown in Figure 12 B, with exposing, develop and curing the part that processing method is removed resist layer 59.The resist layer 59 that is removed is desirable for wiring figure forms part position in addition.
In Figure 12 B, up to the scope of the top of glass plate 54, keep resist layer 59 from the top of electrode 52.And, will above the electrode 52 and another electrode 52 above between be interrupted, make it discontinuous.
And, during etching aluminium lamination 58, shown in Figure 12 C, become the wiring zone stay aluminium lamination 58.That is,, form aluminium lamination 58 as wiring from the top of electrode 52 up to glass plate 54.And, formed aluminium lamination 58, make its electrode 52 not conducting ground mutually, become each bar wiring of each self-electrode 52.Perhaps, if need make a plurality of electrode 52 conductings, then also can be corresponding therewith, become the aluminium lamination 58 of wiring.In addition, as wiring, except that aluminium lamination 58, any material that can be applicable among all material of selecting in the 1st prerequisite technology is arranged.
Since with above operation, form wiring from electrode 52, on aluminium lamination 58, form solder ball as wiring, and wafer 50 is cut into each semiconductor device.These operations just can be carried out equally with above-mentioned the 1st prerequisite technology.
If the employing present technique, then glass plate 54 has hole 54a, and the formation of hole 54a is easy.And, do not need to being pre-formed the figure that resembles salient point or wiring and so on the glass plate 54.And in the formation operation of aluminium lamination 58 grades that become wiring, the metallic film of using in the wafer process process forms technology, and most operation is all finished with wafer process.
In addition, also can with the 1st prerequisite technology other stress absorbing layer be set equally further, for example polyimide resin etc. in the top of glass plate 54.Under these circumstances, because stress absorbing layer is set again, thereby the thermal coefficient of expansion of glass plate 54 also can be identical with silicon.
(the 6th prerequisite technology)
Figure 13 A～Figure 13 D is the figure of manufacture method of the semiconductor device of explanation the 6th prerequisite technology.In present technique, stress-buffer layer has been selected polyimide plate.Polyimides is because Young's modulus is low, so be to be fit to material as stress-buffer layer.Also have, also can use in addition, for example the composite plate of plastic plate or glass epoxy resin system etc.At this moment, if use and the base plate for packaging same material, it then is desirable not having difference on the thermal coefficient of expansion.Particularly present, mostly plastic base is used as base plate for packaging, so the stress-buffer layer plastic plate is effective.
At first, as shown in FIG. 13A, on the wafer 60 with electrode 62, bonding polyimide plate 64 is made for shown in Figure 13 B.Also have, on polyimide plate 64, application of adhesive 66 in advance.
Secondly, shown in Figure 13 C, on the zone corresponding, form contact hole 64a, shown in Figure 13 D, form aluminium lamination 68 with sputtering method with exciplex laser etc. with electrode 62.In addition, except that aluminium lamination 68, also can be applied in any material among all material of selecting in the 1st prerequisite technology.
And, owing to become the state same with Figure 11 D, so after, can carry out the later operation of Figure 12 A and make semiconductor device.
If the employing present technique does not form the polyimide plate 64 in hole owing to use, so do not need to have made the substrate of figure.Other effect and the above-mentioned the 1st～the 5th prerequisite technology are same.
In addition, as other technology, the machining of boring a hole in advance on stress-buffer layer etc. is provided with the hole, and then, the configuration technology of carrying out bonding grade on wafer also is fine.And except that machining, also can the hole be set with chemical method for etching or dry-etching method.In addition, forming under the situation in hole, with chemical method for etching or dry-etching method even on wafer, also can be undertaken by operation in advance before this.
(the 1st embodiment)
The present invention, because further above-mentioned technology has been developed in improvement, below, most preferred embodiment of the present invention is described with reference to the accompanying drawings.
Figure 14 A～Figure 14 D is the figure of expression the 1st embodiment of the present invention.
In the semiconductor device shown in Figure 14 A 150, form the resin bed 152 that constitutes by polyimides discontinuously.Resin bed 152 becomes stress-buffer layer.As stress-buffer layer,, also can be non-photoresist though the photosensitive polyimide resin is desirable.For example also can use the silicone modified polyimide resin, epoxy resin, silicone modified epoxy etc., (1 x 10 that the Young's modulus during curing is low
10Pa is following), work the material that relaxes stress.
And, on resin bed 152, formed recess 152a with taper.And owing to formed wiring 154 along the surface configuration of this recess 152a, aspect section shape, wiring 154 is crooked.In addition, in wiring 154, also formed solder ball 157.Such wiring 154 is configured on the resin bed 152 as stress-buffer layer, and, since crooked, so compare, become flexible easily with the situation of simple flat ground configuration.So, when being assembled to semiconductor device 150 on the circuit substrate, the stress that produce because of thermal coefficient of expansion is different with regard to easy absorption.From connecting up 154 parts that are subjected to displacement (bend grades) till solder ball 157, selecting the bigger material of strain rate is desirable as resin bed 152.This has selected material, even also be common being suitable in the following embodiments.
And then, above recess 152a, specifically be equivalent to the position of recess 152a, on the wiring zone that forms concavity, shown in Figure 14 A, it is desirable that elastomer 156 is set.If elastomer 156 is to be used for forming good as the material of the resin bed 152 of stress-buffer layer.By means of this elastomer 156, can further absorb the stress that wiring 154 is stretched.Make for example photoresist layer that forms outermost layer (protective layer), the function that has elastomer 156 concurrently is good.And elastomer 156 also can be corresponding with each recess 152a, is provided with separately respectively.
And 154 the broken string that prevents to connect up perhaps, prevents stress and destroys electrodes 158 etc. by wiring 154.In addition, electrode 158 and wiring 154 are all protected coated with outermost layer (protective layer) 155.
Secondly, in the semiconductor device shown in Figure 14 B 160, on the 1st resin bed 162 of formed the 1st wiring 164 from electrode 169 to the 1st resin beds 162, form the 2nd resin bed 166 and the 2nd wiring 168.The 1st wiring 164 is connected with electrode 169, and the 2nd wiring 168 and the 1st is connected up and 164 is connected, and at the 2nd formation solder ball 167 on 168 that connects up.Like this, if form multi-layer resinous layer and wiring, just can increase the degree of freedom of wires design.Also have, electrode 169 and the 1st wiring 164 and 168 all cover with outermost layer (protective layer) 165 and are protected.
And, also can will almost can ignore the elongated wiring of area, form have planar extension (width or size) planar.And, when resin bed is multilayer, just become easy dispersive stress.Also have, if will be set at GND (ground connection) current potential or supply voltage current potential with the wiring of planar formation, then easy control group, high frequency characteristics will be very superior.
Secondly, the semiconductor device 170 shown in Figure 14 C, the device that semiconductor device 150 and 160 is combined exactly.That is, on the 1st resin bed 172, form the 1st wiring 174, form the 2nd resin bed 176, make it have recess 176a in the top of the 1st wiring 174.And, be formed at the wiring of the 2nd on the 2nd resin bed 176 178, on section shape, have bending.In addition, in the 2nd wiring 178, formed solder ball 177.And electrode 179 and wiring 174 are all protected coated with outermost layer (protective layer) 175 with 178.If the employing present embodiment just can reach above-mentioned semiconductor device 150 and 160 effect of Combination.
Secondly, in the semiconductor device shown in Figure 14 D 180, the top of the stress-buffer layer 187 that forms in zone shown in broken lines forms wiring 184 from electrode 182, make and in flat shape, carry out bending, and in this wiring 184, formed the salient point 186 of solder ball etc.Even in the present embodiment, for above-mentioned semiconductor device 150 (with reference to Figure 14 A), because direction is opposite, wiring 184 is also crooked, so also very superior aspect the ability that absorbs stress.
In addition, also can be shown in Figure 14 A～Figure 14 C like that, the crooked wiring 184 in three-dimensional ground in the flat shape bending shown in Figure 14 D.So, just further improved and prevented the effect that breaks.But stress-buffer layer 187 must be present under the wiring 184.And electrode 182 and wiring 184 are protected coated with the unshowned outermost layer of figure (protective layer).
(the 2nd embodiment)
Secondly, the semiconductor device 190 shown in Figure 15 aspect connecting aluminum pad 192 and being located at the wiring 200 of solder ball 196 of stress-buffer layer 194 tops, has characteristics.Wiring 200 can be used in any material among the selected wiring material in the 1st prerequisite technology the.This wiring 200 has folding part 200a.Shown in Figure 14 D, folding part 200a is to have become the state in cavity (slit) among the wiring, and inserted the common wiring a plurality of folding part 200a of formation continuously.200a is on the stress absorption performance for this folding part, and is more superior than the wiring 184 of bending.By having this folding part 200a, in wiring 200 crackle taking place on the semiconductor chip, or has not had to aluminum pad 192 with to the damage of other active device, improve reliability as semiconductor device.And, because folding part 200a is arranged in the wiring, so it is insignificant to be used for the space of structure of stress absorption.Therefore, can the limit keep the miniaturization of semiconductor device, the degree of freedom of design is improved on the limit, makes it not break away from the CSP category.In addition, in the present embodiment,, also can design at thickness direction though folding part 200a is the example to in-plane.
In the embodiment or prerequisite technology of above explanation,,, for example there is not any problem with material with known connections such as au bumps even adopt other though be that example is narrated with the scolder as electrode yet.And outer electrode is the active region of semiconductor chip, and if beyond on the electrode, just where also can forms.
(the 3rd embodiment)
Figure 16～Figure 20 is the figure of expression the 3rd embodiment of the present invention.Figure 16 is the profile of the semiconductor device of expression present embodiment.This semiconductor device 300 have multilayer (4 layers) structure on semiconductor chip 302, and the surface is protected with anti-solder flux 350.In addition, in the present embodiment, also can use the material that illustrated in other embodiment and the prerequisite technology and manufacture method etc.
Figure 17 A and Figure 17 B are the figure of the 1st layer of expression.In detail, Figure 17 B is a plane graph, and Figure 17 A is the profile of the VII-VII line of Figure 17 B.On semiconductor chip 302, formed the electrode 304 that signal inputs or outputs.Near electrode 304, having formed the end is the stress-buffer layer 310 on inclined plane.Stress-buffer layer 310 is insulators, and specifically, polyimide resin is desirable.And, on stress-buffer layer 310, formed signal routing 312 from electrode 304.Signal routing 312, shown in Figure 17 B, with the end of electrode 304 opposite sides, the connecting portion 312a of island is arranged.And, resemble the mode that this connecting portion 312a is surrounded, form GND plane 316 non-contiguously.GND plane 316 is connected with the earthy electrode (scheming not shown) of semiconductor chip 302.
Figure 18 A and Figure 18 B are the figure of the 2nd layer of expression.In detail, Figure 18 B is a plane graph, and Figure 18 A is the VIII-VIII line profile of Figure 18 B.As shown in these figures, on above-mentioned the 1st layer, formed stress-buffer layer 320.But the middle body of connecting portion 312a that stress-buffer layer 320 will be avoided the 1st layer signal routing 312 forms.And, from the stress-buffer layer 320 of the 1st layer connecting portion 312a, form signal routing 322 up to the 2nd layer.Signal routing 322 has connecting portion 322a and another connecting portion 322b that is connected with connecting portion 312a.And, on stress-buffer layer 320, form not signal routing 324 with signal routing 322 conductings.Signal routing 324 has connecting portion 324a, 324b.And then, on stress-buffer layer 320, though formed another wiring 324 and 325, owing to do not have direct relation with the present invention, the Therefore, omited explanation.And, form GND plane 326, make its encirclement, and don't activation signal wiring 322,324 and connect up 324,325.GND plane 326, being situated between is connected with the earthy electrode of semiconductor chip 302 (scheming not shown) with the 1st layer GND plane 316.
Figure 19 A and Figure 19 B are the figure of the 3rd layer of expression.In detail, Figure 19 B is a plane graph, and Figure 19 A is the IX-IX line profile of Figure 19 B.As shown in these figures, on above-mentioned the 2nd layer, formed stress-buffer layer 330.But the middle body of connecting portion 322b that stress-buffer layer 330 will be avoided the 2nd layer signal routing 322 forms.And, up to stress-buffer layer 330, form signal routing 332 from the 2nd layer connecting portion 322b.Signal routing 332 has connecting portion 332a and another connecting portion 332b that is connected with the 2nd layer connecting portion 332b.And, on stress-buffer layer 330, form not signal routing 334 with signal routing 332 conductings.This signal routing 334 has connecting portion 334a, 334b.And, form GND plane 336, make its encirclement, and don't activation signal wiring 332 and signal routing 334.GND plane 326, Jie is connected with the earthy electrode of semiconductor chip 302 (scheming not shown) with the 2nd layer GND plane 326 with the 1st layer GND plane 316.
Figure 20 A and Figure 20 B are the figure of the 4th layer of expression.In detail, Figure 20 B is a plane graph, and Figure 20 A is the X-X line profile of Figure 20 B.As shown in these figures, on above-mentioned the 3rd layer, form stress-buffer layer 340.But stress-buffer layer 340 will be avoided the central portion of connecting portion 334b of the 3rd layer signal routing 334 and assign to form.And, on the 3rd layer connecting portion 334b, form connecting portion 342, on this connecting portion 342, form the pedestal 344 that constitutes by copper (Cu), on this pedestal 344, formed solder ball 348.Solder ball 348 becomes outer electrode.And, form GND plane 346, make its encirclement, and, do not contact connecting portion 342.GND plane 346, being situated between is connected with the earthy electrode of semiconductor chip 302 (scheming not shown) with the 3rd layer GND plane 336 with the 1st layer GND plane 316, the 2nd layer GND plane 326.
Secondly, the conducting state in the present embodiment is described.The electrode 304 that is formed on the semiconductor chip 302 is connected with the 1st layer signal routing 312, and this signal routing 312 is connected with the 2nd layer signal routing 322 again.This signal routing 322 is connected with the 3rd layer signal routing 332 by its connecting portion 322b.This signal routing 332 is connected with the 2nd layer signal routing 324 by its connecting portion 332b.This signal routing 324 is connected with the 3rd layer signal routing 334 by its connecting portion 324b.And, on the connecting portion 334b of this signal routing 334, be situated between with connecting portion 342 and pedestal 344, formed solder ball 348.
And, be formed on the optional position on the semiconductor chip as the solder ball 348 of outer electrode, be connected with the electrode 304 of optional position on the semiconductor chip that inputs or outputs signal.
Much less, outer electrode also can resemble said in other embodiment or the prerequisite technology be configured to rectangular.
And the 1st layer～the 4th layer GND plane 316,326,336 and 346 all is identical earthing potential.
And if adopt present embodiment, the then wiring between electrode 304 and the solder ball 348 by insulator, becomes the conductor that makes its encirclement earthing potential.Just, because inner conductor by insulator, surrounds the external conductor of earthing potential, so have the structure same with coaxial cable.Therefore, signal is difficult to be subjected to the influence of noise, can obtain desirable transmission circuit.And, for example if as the semiconductor device of CPU, then may be to surpass the such high speed operation of 1Ghz.
In addition, in order to reduce cambial cost, also can omit the one deck on the GND plane 316,346 that forms the 1st layer or the 4th layer.
(other embodiment)
The present invention can have various distortion, and is not limited to the foregoing description.For example, the foregoing description though the present invention is applied to semiconductor device, can be applied to the present invention in the electronic unit of various surface-mounted usefulness, and no matter be active parts or passive component.
To be expression be applied to illustration in the electronic unit of surface-mounted usefulness to the present invention to Figure 21.This electronic unit that illustrates 400 is in the both sides of chip part 402 electrode 404 to be set and to constitute, for example resistor, capacitor, coil, oscillator, filter, temperature sensor, thermistor, rheostat, potentiometer and fuse etc.On electrode 404, same with the foregoing description, be situated between with stress-buffer layer 406, form wiring 408.In this wiring 408, form salient point 410.
And also to be expression be applied to illustration in the electronic unit of surface-mounted usefulness to the present invention to Figure 22.The electrode 424 of this electronic unit 420 is formed on the surface of assembling side of chip part 422, and forms wiring 428 by stress-buffer layer 426.In this wiring 428, form salient point 430.
In addition, these electronic units 400 and 420 manufacture method, because of same with the foregoing description or prerequisite technology, the Therefore, omited explanation.And the effect that forms stress- buffer layer 406 and 426 is also same with the foregoing description or prerequisite technology.
Secondly, Figure 23 is illustrated in to use the illustration that forms protective layer on the semiconductor device of the present invention.This semiconductor device that illustrates 440, owing on the semiconductor device shown in Fig. 4 C, form protective layer 442, same with the semiconductor device shown in Fig. 4 C except that protective layer, the Therefore, omited explanation.
In semiconductor device 440, with the assembling one side opposing face, promptly formed protective layer 442 on the back side.So, can prevent that the back side is injured.
And then, can prevent that injured with the back side is the damage of the semiconductor chip self that causes of the crackle of starting point.
It is desirable to, before the semiconductor device 440 that cuts into as monolithic, protective layer 442 is formed into the back side of wafer.So, can form protective layer 442 simultaneously to a plurality of semiconductor devices 440.In detail, can after forming operation and be all over, metallic film on wafer, form protective layer 442.So, just can successfully carry out metallic film and form operation.
If like this, then since the surface of semiconductor device coated with the material except that silicone, thereby raising for example identifies performance.
Secondly, Figure 24 is illustrated in to use the illustration that radiator is installed on the semiconductor device of the present invention.This semiconductor device that illustrates 450 has been installed radiator 452 on the semiconductor device shown in Fig. 4 C, since same with the semiconductor device shown in Fig. 4 C except that radiator 452, so save explanation.
In semiconductor device 450, radiator 452 is situated between and is installed to and assembles a side opposing face with thermally conductive adhesive 454, promptly on the back side.So, thermal diffusivity has improved.Radiator 452 has a plurality of fin 456, and forms many with copper or copper alloy, aluminium nitride etc.In addition, in this example, do example,, also can obtain corresponding radiating effect even the simple tabular radiator (heating panel) that does not have fin is installed though enumerate the band fin.At this moment since be install simply tabular, so easily processing and can reduce cost.
In the foregoing description and prerequisite technology, though, in the semiconductor device side solder bump or au bump are set in advance as outside terminal, but as other example, also can be in semiconductor device one side, with the pedestal of for example copper etc. in the same old way as outside terminal, and without solder ball or au bump.In addition, at this moment, when semiconductor device assembles before, need in advance on the connecting portion (flange) of the base plate for packaging (motherboard) of assembling semiconductor device, scolder to be set.
And used in the above-described embodiments polyimide resin can be a black.By with the polyimide resin of black as stress-buffer layer, avoid semiconductor chip to be subjected to the malfunction of light time, can increase light resistance simultaneously, improve the reliability of semiconductor device.
In addition, in Figure 25, the circuit substrate 1000 of the electronic unit 1100 that has assembled the semiconductor device made with the method for the foregoing description etc. has been shown.And, as the electronic equipment that is equipped with this circuit substrate 1000, in Figure 26, shown notebook personal computer 1200.
Claims (2)
1. the manufacture method of a semiconductor device is characterized in that, has:
Preparation has formed the operation of the wafer of electrode;
Avoid at least a portion of above-mentioned electrode, the operation of the 1st stress-buffer layer is set on above-mentioned wafer;
From the top of above-mentioned electrode, form the operation of the 1st conducting portion up to above-mentioned the 1st stress-buffer layer;
In the top of above-mentioned the 1st stress-buffer layer that has formed above-mentioned the 1st conducting portion, form the operation of the 2nd stress-buffer layer; With
On above-mentioned the 2nd stress-buffer layer, the operation of the 2nd conducting portion that is connected with above-mentioned the 1st conducting portion is set;
In the top of above-mentioned the 2nd stress-buffer layer that has formed above-mentioned the 2nd conducting portion, form the operation of the 3rd stress-buffer layer;
On above-mentioned the 3rd stress-buffer layer, form the operation of the 3rd conducting portion;
Above above-mentioned the 1st stress-buffer layer, form the operation of the outer electrode that is connected with above-mentioned the 1st conducting portion; And
Above-mentioned wafer is cut into the operation of each small pieces,
Above-mentioned the 2nd conducting portion is formed wire, and the above-mentioned the 1st and the 3rd conducting portion is formed planar, it is had than the also big planar extension of above-mentioned the 2nd conducting portion.
2. semiconductor device is characterized in that having:
Semiconductor chip with electrode;
In the top of above-mentioned semiconductor chip, avoid at least a portion of above-mentioned electrode and the 1st stress-buffer layer that is provided with;
From 1st conducting portion of above-mentioned electrode up to the formation of the top of above-mentioned the 1st stress-buffer layer;
The 2nd stress-buffer layer that on above-mentioned the 1st stress-buffer layer, forms;
The 2nd conducting portion that on above-mentioned the 2nd stress-buffer layer, forms;
The 3rd stress-buffer layer that on the 2nd stress-buffer layer, forms;
The 3rd conducting portion that on above-mentioned the 3rd stress-buffer layer, forms; And
Be positioned at above-mentioned the 1st stress-buffer layer above the outer electrode that forms of above-mentioned the 1st conducting portion;
Make above-mentioned the 2nd conducting portion form wire, and that the above-mentioned the 1st and the 3rd conducting portion form is planar, so that have the expansion on the plane also bigger than above-mentioned the 2nd conducting portion.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33904596 | 1996-12-04 | ||
| JP339045/96 | 1996-12-04 | ||
| JP356880/96 | 1996-12-26 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB971920338A Division CN100380612C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device, method for manufacturing thereof, circuit board, and electronic equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1937191A CN1937191A (en) | 2007-03-28 |
| CN100474543C true CN100474543C (en) | 2009-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101517063A Expired - Fee Related CN100485896C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same |
| CN2007101379458A Expired - Fee Related CN101127336B (en) | 1996-12-04 | 1997-12-04 | Semiconductor device, manufacturing method thereof, circuit substrate and electric device |
| CNB2006101732479A Expired - Fee Related CN100440472C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same, circuit board, and electronic instrument |
| CNB200610151703XA Expired - Fee Related CN100474544C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same |
| CNA2006101018525A Pending CN1881553A (en) | 1996-12-04 | 1997-12-04 | Electronic component,semiconductor device and method of making the same, circuit board, and electronic instrument |
| CNA2009100044189A Pending CN101488490A (en) | 1996-12-04 | 1997-12-04 | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
| CNB2006101517025A Expired - Fee Related CN100474543C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same |
Family Applications Before (6)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101517063A Expired - Fee Related CN100485896C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same |
| CN2007101379458A Expired - Fee Related CN101127336B (en) | 1996-12-04 | 1997-12-04 | Semiconductor device, manufacturing method thereof, circuit substrate and electric device |
| CNB2006101732479A Expired - Fee Related CN100440472C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same, circuit board, and electronic instrument |
| CNB200610151703XA Expired - Fee Related CN100474544C (en) | 1996-12-04 | 1997-12-04 | Semiconductor device and method of making the same |
| CNA2006101018525A Pending CN1881553A (en) | 1996-12-04 | 1997-12-04 | Electronic component,semiconductor device and method of making the same, circuit board, and electronic instrument |
| CNA2009100044189A Pending CN101488490A (en) | 1996-12-04 | 1997-12-04 | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
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| CN (7) | CN100485896C (en) |
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| US8659153B2 (en) * | 2012-07-16 | 2014-02-25 | Micron Technology, Inc. | Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods |
| US9597752B2 (en) * | 2015-03-13 | 2017-03-21 | Mediatek Inc. | Composite solder ball, semiconductor package using the same, semiconductor device using the same and manufacturing method thereof |
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| US5111278A (en) * | 1991-03-27 | 1992-05-05 | Eichelberger Charles W | Three-dimensional multichip module systems |
| US5243221A (en) * | 1989-10-25 | 1993-09-07 | At&T Bell Laboratories | Aluminum metallization doped with iron and copper to prevent electromigration |
| CN1123468A (en) * | 1994-07-11 | 1996-05-29 | 国际商业机器公司 | Attaching heat sinks directly to chip carrier modules using flexible-epoxy |
| EP0734059A2 (en) * | 1995-03-24 | 1996-09-25 | Shinko Electric Industries Co. Ltd. | Chip sized semiconductor device and a process for making it |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2115947A1 (en) * | 1993-03-03 | 1994-09-04 | Gregory C. Smith | Wafer-like processing after sawing dmds |
-
1997
- 1997-12-04 CN CNB2006101517063A patent/CN100485896C/en not_active Expired - Fee Related
- 1997-12-04 CN CN2007101379458A patent/CN101127336B/en not_active Expired - Fee Related
- 1997-12-04 CN CNB2006101732479A patent/CN100440472C/en not_active Expired - Fee Related
- 1997-12-04 CN CNB200610151703XA patent/CN100474544C/en not_active Expired - Fee Related
- 1997-12-04 CN CNA2006101018525A patent/CN1881553A/en active Pending
- 1997-12-04 CN CNA2009100044189A patent/CN101488490A/en active Pending
- 1997-12-04 CN CNB2006101517025A patent/CN100474543C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5243221A (en) * | 1989-10-25 | 1993-09-07 | At&T Bell Laboratories | Aluminum metallization doped with iron and copper to prevent electromigration |
| US5111278A (en) * | 1991-03-27 | 1992-05-05 | Eichelberger Charles W | Three-dimensional multichip module systems |
| CN1123468A (en) * | 1994-07-11 | 1996-05-29 | 国际商业机器公司 | Attaching heat sinks directly to chip carrier modules using flexible-epoxy |
| EP0734059A2 (en) * | 1995-03-24 | 1996-09-25 | Shinko Electric Industries Co. Ltd. | Chip sized semiconductor device and a process for making it |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101127336B (en) | 2010-09-29 |
| CN1937191A (en) | 2007-03-28 |
| CN100440472C (en) | 2008-12-03 |
| CN100485896C (en) | 2009-05-06 |
| CN1881553A (en) | 2006-12-20 |
| CN101127336A (en) | 2008-02-20 |
| CN1937192A (en) | 2007-03-28 |
| CN1937193A (en) | 2007-03-28 |
| CN101488490A (en) | 2009-07-22 |
| CN1992188A (en) | 2007-07-04 |
| CN100474544C (en) | 2009-04-01 |
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