JP2000138875A - Television receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To magnify a video image according to a plurality of magnifications by allowing a magnification control means to conduct read stop control for a storage means, and synchronously outputs a coefficient used for filter processing of a spatial filter processing to the spatial filter means. SOLUTION: A magnification control means conducts read-stop control for a storage means, and synchronously outputs a coefficient used for filter processing of a spatial filter processing to the spatial filter means. In this television receiver, while the gate signal of a read clock is turned off, the read clock of a memory is stopped and read of one inter-line data is stopped. For example, when magnifying at a multiple of 4/3, a vertical magnification control circuit 204 gives a control signal to turned off a read gate to a 1st memory circuit 104 by a period, i.e., once every 4 lines. Thus, the 1st memory circuit 104 decides on the magnified position and a period for scanning magnification and outputs a prescribed signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television signal receiver, and more particularly to a television receiver having a circuit for enlarging and displaying an inputted television signal to an arbitrary size.

[0002]

2. Description of the Related Art With the spread of high-definition television having an aspect ratio of 16: 9, various studies have been made on compatibility with a conventional television such as the NTSC system. In particular, when displaying an image having a standard 4: 3 aspect ratio on a display having an aspect ratio of 16: 9, there are many problems such as burning of a phosphor due to a frame signal inserted in a portion having no image. I have a problem.

When a standard signal having an aspect ratio of 4: 3 is projected on a 16: 9 display, the circle becomes a horizontally long ellipse as shown in FIG. As shown in FIG. 3B, the video signal is compressed in the horizontal direction, and frame signals are inserted at both ends for display. However, in this display method, the 16: 9 wide display is not effectively used (that is, there is a portion where no video is displayed), and therefore, as shown in FIG. The display is enlarged vertically and the display is used effectively. FIG. 4 is a conceptual diagram of the prior art.
(A). In FIG. 4A, reference numeral 401 denotes NTSC
A signal input terminal, 402 is an output terminal of a video signal whose aspect ratio has been converted, 403 is an NTSC decoder that converts an NTSC signal into a luminance / color difference signal, and 404 is a non-interlace conversion circuit that converts it into a double-speed signal and sequentially scans it. ,
405 is a first memory circuit for converting the time axis, 406 is a second memory circuit for determining a video signal cutout position, 4
07 is a line operation circuit for performing an operation between upper and lower lines,
408 and 409 are first and second selection circuits.

First, when a 4: 3 image is displayed by inserting frame signals on both sides of the screen as shown in FIG. 3B, the first memory circuit 405 is used and the frequency is higher than the write clock. By providing a read clock, the time axis is compressed, and a video signal is supplied to the display through the a-side terminal of the second selection circuit 409. In addition, when the input video signal is an NTSC signal and corresponds to 16: 9 as shown in FIG. 3D (a circle is recorded as a vertically long ellipse), the first and the second are used. The display is performed as it is through the a side terminal of the first selection circuit 408 and the b side terminal of the second selection circuit 409 without passing through the memory circuit of FIG. Therefore, as shown in FIG. 3E, a 16: 9 display can display a video signal of an accurate shape. Further, in the case where the upper and lower portions are cut and enlarged and displayed as shown in FIG. 3C, the screen cutout position is determined using the second memory circuit 406 having a sufficiently large capacity, and the line operation circuit 407 The image is interpolated and enlarged in the vertical direction.

FIG. 4B shows the details of the line operation circuit 407. 4B, reference numeral 410 denotes an input terminal of a video signal from the second memory circuit 406, 411 denotes an output terminal, 412 denotes a one-line delay memory circuit, 413,
414 is a coefficient unit memory for multiplying the input signal by a coefficient, and 415 is an adder. FIG. 5 illustrates the interpolation processing of the line operation circuit 407.
This will be described in detail with reference to FIG. FIGS. 5A and 5B show the center of gravity of a signal when a scanning line is interpolated and enlarged, and the weight coefficient of each scanning line. Here, the coefficients for the case of 4/3 magnification are shown. When the signal is enlarged by a factor of 4/3, an enlarged signal can be generated by a relatively simple coefficient filtering process. FIG. 5C shows the input terminal 410.
And the same scanning line is read out repeatedly for every four lines. FIG. 5D shows the input terminal 41.
The value of the second coefficient circuit 414 multiplied by the scanning line of 0 is shown.
FIG. 5 (5) shows an output scanning line of the one-line delay memory 412. FIG. 5 (6) shows the coefficient value of the first coefficient unit 413. FIG. 5 (7) shows an output signal of the adder 415. In this manner, by switching the coefficient for each line to create a new scanning line, the expanded signal of the correct center of gravity shown in FIG. 5B can be obtained. As described above, according to the conventional technique, 1
It is designed to effectively display 4: 3 video signals on a 6: 9 display.

Another prior art is disclosed in Japanese Patent Laid-Open Publication No.
As shown in Japanese Patent No. 60583, a movie size signal as shown in FIG.
In some cases, the display method as shown in (c) is realized using a deflection circuit.

On the other hand, as a technique for compressing an input video signal in the horizontal direction and displaying it as shown in FIG. 3 (b), a PLL based on a write clock of the first memory circuit 405 is used.
There has been adopted a method of creating a read clock by using a clock. However, in this method, a loop for creating a write clock, a loop for creating a read clock, a loop for a deflection circuit of a display, and a multiple loop in a synchronous system exist, and a home VT is used.
When a signal having a large amount of jitter, such as R, is input, the jitter is largely displayed, which leads to deterioration of image quality.

[0008]

As described above, a system having a 16: 9 display using the prior art is described.
A method of displaying a standard signal having three aspect ratios has been described. In the above-mentioned conventional technology, the signal is expanded in the vertical direction and 1
Although a method of displaying the entire display at 6: 9 is adopted, there is a problem that an important part of the image is actually missing in some cases. Also, there are various kinds of signals of the movie size shown in FIG. 3 (f) having different sizes of video portions, and when these video signals are simply vertically enlarged, subtitles and video signals are not obtained. Important parts are cut off, or blanking parts at the top and bottom of the movie,
Often they still remain. In Japanese Patent Application Laid-Open No. 3-11891 described as the prior art, as a vertical enlargement mode, the values of the first and second coefficient units 413 and 414 are switched between two types of 4/3 times and 5/4 times. The upper and lower invisible video portions are reduced, but in this case, the roundness is not 100%.

Further, in the above-mentioned prior art, it is difficult to enlarge an image at a plurality of magnifications because the coefficients used for the line complementing operation are fixed.

Further, when the input signal is compressed and displayed as shown in FIG. 3B, it is expected that the performance with respect to jitter tends to deteriorate.

A first object of the present invention is to provide a television receiver capable of enlarging an image at a plurality of magnifications.

Another object of the present invention is to provide a television receiver capable of performing an enlarged display process while suppressing jitter.

[0013]

In order to achieve the first object, a television receiver according to the present invention comprises an enlarged screen display circuit for inputting a video signal and performing enlargement processing.
In a television receiver for displaying a video signal enlarged by the enlarged screen display circuit on a screen, the enlarged screen display circuit outputs a write clock and a read clock having a higher frequency than the write clock. Means, a video signal written by a write clock output from the synchronization processing means, and a storage means from which the video signal is read by the read clock; and a video signal read from the storage means, Spatial filter means for performing vertical and horizontal filter processing in accordance with the coefficient, and controlling a read stop cycle of the storage means, and generating coefficients used for the filter processing of the spatial filter means to the spatial filter means. Output enlargement control means, wherein the enlargement control means outputs A reading stop control means, it is characterized in that performed in synchronization with the output to the spatial filtering unit of said coefficient.

In order to achieve the second object,
A television receiver according to the present invention includes an enlarged screen display circuit that performs an enlargement process by inputting a video signal, and a television receiver that displays an image signal enlarged by the enlarged screen display circuit on a screen. The enlarged screen display circuit includes a write clock generating unit that generates a write clock synchronized with the video signal, a read clock signal generating unit that generates a read clock signal having a higher frequency than the write clock, Means for writing a video signal by a write clock from the means and reading the video signal by a read clock from the read clock generating means; and a vertical and horizontal direction for the video signal read from the storage means. Filter to obtain an enlarged video signal And a filter means, said read clock, said a write clock and asynchronous, and is characterized in being created independently of the said write clock.

[0015]

FIG. 1 shows an embodiment of the present invention.
In FIG. 1, reference numeral 101 denotes an input terminal of a sequentially scanned video signal, 102 denotes an output terminal, 103 denotes a clock input terminal, 109 denotes a synchronization signal input terminal, and 104 and 105 denote writing and reading with different clocks. The first that can be
The second memory circuit 106 is a spatial filter circuit for performing an operation in the vertical and horizontal directions to generate an interpolation signal.
7 is an enlargement control circuit for controlling the first and second memory circuits 104 and 105 and the spatial filter circuit 106;
Reference numeral 8 denotes a synchronization processing circuit that supplies a clock and the like to each of the circuits. In FIG. 1, a video signal of progressive scanning input from an input terminal 101 is expanded in a vertical direction by the first memory circuit 104 and in a horizontal direction by the second memory circuit 105. The enlargement is performed by reading the same line a plurality of times and the same pixel a plurality of times. In this way, the signals enlarged in the vertical and horizontal directions are filtered by the spatial filter 106 and output as smooth video signals.

An embodiment of the configuration shown in FIG. 1 will be described in detail with reference to FIG. In FIG. 2, 201 is a vertical filter circuit that creates a new scanning line from two scanning lines, 202 is a horizontal filter circuit that creates a new pixel from two pixels, 203 is a frame signal insertion circuit that inserts another video signal, A vertical enlargement control circuit 204 controls the first and second memory circuits 104 and 105, the vertical filter circuit 201, and the frame signal insertion circuit 203 in accordance with an enlargement magnification.
The horizontal enlargement control circuit 206 controls the memory circuit 105, the horizontal filter circuit 202, and the frame signal insertion circuit 203 according to the enlargement magnification, and generates a stable first clock having substantially the same frequency as the clock from the input terminal 103. A first clock generation circuit 207 generates a new second clock having a frequency of about 4/3 times the frequency of the first clock, and supplies a second clock to the second memory circuit 105. The circuit and others are the same as those in the embodiment of FIG.

Here, for the sake of simplicity, a case where the input signal is enlarged to 4/3 times will be described.

The first memory circuit 104 determines a vertical position to be enlarged in the input video signal, stops reading from the memory at a line cycle corresponding to the magnification, and uses the video signal containing jitter to It plays the role of converting to a stable video signal. FIG. 6 shows a principle diagram of a method of enlarging a scanning line in a vertical direction, that is, a scanning line. The operation of the first memory circuit 104 is shown in FIGS. FIG.
Is a side view of the television screen, and the scanning lines are indicated by circles. FIG. 6A shows the position of the vertical synchronizing signal of the input signal. FIG. 6B shows the positions of the scanning lines of the video signal input from the input terminal 101. When the screen is to be enlarged from the scanning line d, the write reset signal of the first memory circuit 104 is set to the position shown in FIG. 6 (3) by the vertical enlargement control circuit 204 as shown in FIG. . Therefore, the write address of the first memory circuit 104 becomes zero at the position of the scanning line d, and writing is sequentially performed from here.

FIG. 6 (5) shows the gate signal of the read clock. While this gate signal is off,
The read clock of the memory stops, and the reading of data for one line stops. To enlarge by 4/3 times,
A control signal for turning off the read gate is supplied from the vertical enlargement control circuit 204 to the first memory circuit 104 once every four lines. In this way, the enlargement position and the scan line enlargement cycle are determined in the first memory circuit 104, and the signal shown in FIG. 6 (6) is output from the first memory circuit 104. Further, since the first memory circuit 104 uses the stable first clock from the first clock generation circuit 206 as a read clock, the output video signal itself from the memory does not include jitter. .

The second memory circuit 105 converts the time axis and reproduces data while the first memory circuit 104 stops reading. FIG. 7 shows an example of a detailed configuration of the second memory circuit 105 and an operation principle thereof. FIG. 7A shows the details of the second memory circuit 105, and reference numeral 701 denotes the first memory circuit 10.
4, an input terminal 702; an output terminal; 703, an input terminal for a write clock from the first clock generation circuit 206; 704, an input terminal for a read clock from the second clock generation circuit 207; 705, 7
06 is a write reset signal, read reset signal input terminal, 707 and 708 are write enable signal input terminals, 709 is an output control signal input terminal,
710 and 711 are memories of one line capacity, respectively.
2 is a selection circuit. The operation of the circuit in FIG. 7A will be described with reference to FIGS. FIG. 7 (2)
Is an output signal from the first memory circuit 104, and data is missing once in four lines to enlarge to 4/3. FIG. 7C shows a write reset signal and a read reset signal which are input from the input terminals 705 and 706 and reset the internal memories 710 and 711. With these two reset signals, the write address and the read address are reset to zero. FIG. 7 (4),
(7) is a write control signal for the internal memories 710 and 711. When input data is lacking, control is performed so as not to write to either memory. FIG. 7 (5) shows a read clock, and a cross mark indicates that the read clock is supplied. The read clock has a frequency approximately 4/3 times that of the write clock. This read clock is supplied from the second clock generation circuit 207 to P
It is created and supplied using an LL circuit. Therefore,
The data is compressed and read out, and the data is retained while the clock is stopped. The internal memory 710,
As shown in FIGS. 7 (6) and (8), the data read from 711 is the same data read again from the line where the input signal is missing. When the selection circuit 712 is switched in accordance with the output control signal shown in FIG. 7 (9), the signal compressed in the horizontal direction is output with the scanning line arrangement shown in FIG. 6 (7). As described above, an example of the internal configuration of the second memory circuit 105 has been described in detail with reference to FIG. 7, but the configuration of the second memory circuit 105 is not limited thereto. For example, by displacing the positional relationship between the write reset and the read reset, it is also possible to configure a single line memory.

At this stage, the video signal is compressed in the horizontal direction, and becomes a video expanded by writing twice on three lines in the vertical direction. However, in order to smoothly obtain a video signal enlarged in the vertical direction, it is necessary to perform a filtering process in the vertical direction. FIG. 8 shows an example of a detailed configuration of the vertical filter circuit 201.

In FIG. 8, reference numeral 801 denotes an input terminal of a signal from the second memory circuit 105; 802, an output terminal;
Numeral 03 denotes an input terminal of a mixing coefficient according to the magnification from the vertical magnification control circuit 204, 806 denotes an input terminal of a write control signal, 804 denotes a one-line delay memory, and 805 mixes input / output signals of the one-line delay memory. This is a mixer that synthesizes according to coefficients. The input signal from the input terminal 801 is shown in FIG. The signal shown in FIG. 6 (5) becomes a write control signal for the one-line delay memory 804, and writing is stopped once for four lines. As a result, the output signal from the one-line delay memory 804 is as shown in FIG. The mixing coefficient is created by the vertical enlargement control circuit 204. When the mixing coefficient is 4/3 times as in this example, the coefficient is set at a 4-line cycle in the same manner as the reading stop cycle of the first memory circuit 104. Go around once. Assuming that the coefficient of the input signal of the one-line delay memory 804 is α and the coefficient of the output signal is β, when the input and output signals of the one-line delay memory 804 are equal, α =
0, β = 1 (α + β = 1), and FIG.
By giving the coefficient as shown in (9), a scanning line having the same center of gravity of the image can be obtained.

The output signal of the vertical filter circuit 201 is time-compressed in the horizontal direction and filtered in the vertical direction to become a video signal which is smoothly enlarged. Therefore, the image at this point is vertically elongated and distorted. To remove this distortion, the second memory circuit 10
5 and the horizontal filter circuit 202 to perform horizontal enlargement. In FIG. 7, the operation of the second memory circuit 105 has been described assuming that horizontal enlargement is not performed. However, here, the operation will be described in more detail assuming that horizontal enlargement is also performed.

FIG. 9 is a detailed explanatory diagram of the operation of the second memory circuit 105 at the time of horizontal enlargement. FIG. 9 (1)
Is an example of a video signal input from the input terminal 701 in FIG. 7A, and is divided into a blanking period and a video period. FIG. 9B shows a write reset signal, and FIG.
Is a write clock. The write clock is generated from the stable first clock from the first clock generation circuit. The stop position and the stop period of the write clock are changed depending on the enlargement position so that the video signal to be enlarged is correctly written in the memory. For example, when enlarging from point a in FIG.
The write clock is stopped from the blanking end position to point a. Therefore, when the signals stored in the memory are sequentially read by the write clock, the signal at point a is output immediately after blanking.

FIGS. 9 (5) and 9 (6) show a read reset and a read clock. The read clock is the second
Of the write clock output from the clock generation circuit 207 of FIG. The read clock is temporarily gated according to the magnification, and the clock stops. FIG.
In (7), the clock stops once every four times, and the portion to be enlarged is enlarged as shown in FIG. 9 (8). However,
This enlargement is to write twice in several pixels once.
It is not a smooth enlargement. Also, during the blanking period, the read clock is not gated,
Blanking data is not expanded.

The horizontal filter circuit 202 is provided with the second
Has a role of filtering and smoothing the signal expanded in the horizontal direction by the memory circuit 105 of FIG. FIG. 10A shows an example of a detailed configuration of the horizontal filter circuit 202. In FIG. 10A, reference numeral 1001 denotes an input terminal of a signal from the vertical filter circuit 201;
2 is an output terminal, 1003 is the horizontal enlargement control circuit 205
, 1004 and 1006 are delay circuits for one pixel, 1005 is a selection circuit, and 1007 is an expansion terminal from the horizontal expansion control circuit 205 according to the expansion coefficient.
This is a mixing circuit that mixes a signal from the input terminal 1001 and a signal from the delay circuit 1006 to create a new pixel.

In the description of the enlargement in the vertical direction, an example of enlargement by 4/3 is shown, but here, as a more complicated example,
FIG. 10 is used for the case of 7 / 5-fold enlargement with reference to FIG.
The operation of (1) will be described. When the image signal is enlarged by a factor of 7/5, the video signal is written twice by the second memory circuit 105 at a ratio of 2 pixels to 7 pixels, and is input to the input terminal 1001 after increasing the number of pixels. FIG. 11C shows the input video signal. Note that FIGS.
The original center of gravity of a pixel when the image is enlarged by a factor of / 5 and the center of gravity and coefficient of a new pixel formed from two pixels are shown. Selector 1005 to create this new center of gravity pixel
Switches between the current pixel and the signal delayed by one pixel by the control signal shown in FIG. FIG. 11 (6) shows the selector 1
This is the output signal of the delay circuit 1006 switched by 005 and further delayed by one pixel.

At this time, as shown in FIG.
As shown in (2), two or more new pixels may exist between the centers of gravity of the original two pixels. In such a case, a pixel having a correct center of gravity cannot be obtained simply by calculating the original pixel and a pixel delayed by one pixel.

In order to produce a pixel having a correct center of gravity, the current signal shown in FIG. 11 (3) is replaced with a signal shown in FIG. 11 (4) which is delayed by one pixel according to the control signal shown in FIG. 11 (5). A signal shown in FIG. 11 (6) is newly created,
The signals of FIGS. 11 (3) and (6) are input to the mixer 1007, and a pixel having a correct center of gravity, that is, FIG. 11 (7) is created.
Generally, when the magnification is (M / N) times (M and N are natural numbers), if n ≧ (M−1) / N ≧ (n−1) and (n is a natural number), There will be n new pixel centroids between the two pixels. Therefore, in the case of 7/5 times, it is necessary to interpolate two new pixels between two pixels in some cases, and a circuit for obtaining a delay output as shown in the configuration of FIG. , Are getting the right pixels.

FIG. 10B shows the horizontal filter circuit 20.
2 shows another example of the detailed configuration of FIG.

In FIG. 10B, reference numeral 1008 denotes a gate circuit; 1009, a clock input terminal;
This is the same as the example of (1). In FIG. 10B, the gate circuit 1008 stops the clock from the input terminal 1009 in accordance with the control signal from the input terminal 1003, holds the pixel, and performs processing equivalent to the circuit in FIG. I do. 11 (8) is a gate signal for stopping the clock, FIG. 11 (9) is a gated clock, FIG.
1 (10) is an output signal of the delay circuit 1004.
Therefore, by inputting the output signals of FIGS. 11 (3) and (10) to the mixer 1007, it is possible to create a pixel having a correct center of gravity. In the circuit having the configuration shown in FIG. 10B, n is controlled by a control signal from the input terminal 1003.
= 2 or more, and arbitrary horizontal enlargement can be performed.

While an example of the configuration of the horizontal filter circuit 202 has been described above, the configuration of the horizontal filter is not limited to this. Basically, the horizontal filter mixes with a delay amount suitable for clock stop according to the enlargement ratio. Any configuration that obtains an output is sufficient.

In the above description, the vertical expansion is 4
/ 3 times has been described as an example of horizontal enlargement of 7/5 times. Next, the configurations of the mixing circuit and the enlargement control circuit for realizing another arbitrary magnification will be described in detail. Table 1
The coefficient of the mixing circuit for realizing an enlargement of 1 to 2 times
Table 2 shows an approximation using 8 bits.

[0034]

[Table 1]

[0035]

[Table 2]

For example, if the magnification is defined as M / N (N is 8 or less and M is a natural number of 15 or less), 23 kinds of magnifications can be set. In Table 1, 10 types are shown. If the number of bits of the control signals α and β of the mixer 805 is, for example, 8 bits, the enlargement magnification is M / N ≒ 256 / L (0
≦ L ≦ 255; L is an integer), so that α (1) to α (15) have values as shown in Table 1. Magnification magnification approximate to Table 2 and α that can be represented by 8 bits
The value of (n) is shown. The period of α (n) is given by M, and the value of α (n) can be represented by the following equation (1).

Α (0) = 0 α (1) = (256−L) / 256 α (n) = f {α (n−1) + α (1)} Equation (1) where f (x) is a function that takes the decimal part of x, 0 ≦ n ≦ M−
By synchronizing the control of the memory circuits 104 and 105 with the mixing coefficient represented by the integer expression (1) that is 1,
Control of 23 combinations becomes possible. In the case of enlarging a movie size signal and displaying it on a system with a wide display, a magnification of up to 2 times or 4 times
It is sufficient to have a mixing coefficient of about 8 bits from the bit, but any enlargement magnification can be set by increasing the constants M and N and the number of bits of the mixing coefficient.

Referring to FIGS. 15 (1), (2) and FIG.
An example of a mixer 805 and a circuit for generating a mixing coefficient is shown. FIG.
5 (1) and (2), 1501 and 1502 are input terminals of the mixer 805, 1503 is an output terminal,
4 is an input terminal of the mixing coefficient α, 1505, 1506, 15
09 is a first, second and third coefficient multipliers, 1507 and 1510
Is a first and a second adder, and 1508 is a subtractor. FIG.
Assuming that signals from the input terminals 1501 and 1502 are A and B, respectively, in the mixer of FIG. 5 (1), the mixed output C is expressed by equation (2), and in the mixer of FIG. be able to.

C = αA + (1−α) B Equation (2) C = α (AB) + B Equation (3) As shown in FIGS. 15A and 15B, the mixer 805 is used.
Can be realized with a relatively simple configuration only by giving the mixing coefficient α.

FIG. 16 shows a circuit for generating the mixing coefficient α. In FIG. 16, reference numeral 1601 denotes a reset signal input terminal;
602 is a clock input terminal for updating the mixing coefficient α, and 1603 is the first and second memory circuits 104, 1
An output terminal 1604 for a control signal for controlling writing and reading of the data 05, an output terminal 1604 for the mixing coefficient α,
5 is an enlargement ratio setting circuit that determines a constant L determined by the enlargement ratio M / N and the enlargement ratio, 1606 is an M frequency dividing counter,
7 is an adder, and 1608 is a latch circuit. When the M / N is determined, the enlargement ratio setting circuit 1605 determines that the M / N is 2
L of 56 / L is set, and K of (256-L) / 256 is calculated and supplied to the adder 1607. The clock from the input terminal 1602 is 1 in the case of vertical enlargement.
This is a clock of the line cycle, and in the case of horizontal enlargement, it is a clock in pixel units. The output signal of the adder 1607 is latched and updated by the latch circuit 1608, and is output as a mixing coefficient α. The mixing coefficient α is reset by the counter 1606 every M cycles and returns to the initial value.
The counter 1606 is reset every vertical cycle according to the enlargement start position. FIG. 16 shows an example of a circuit for setting the mixing coefficient α and the control timing of the memory. If such a circuit is used, α shown in Table 1 is used.
(N) can be set, and a system in which the magnification can be arbitrarily selected can be configured.

In the embodiment described above, since the vertical enlargement by the first memory 103 and the time compression and the horizontal enlargement by the second memory 104 can be independently controlled, the input video signal is distorted. Even if you have
It can be corrected. That is, even if a signal obtained by converting a high-definition television signal into a standard signal (NTSC or the like), for example, a signal input as shown in FIG. It is possible to return to a signal of the correct shape as in e).

If such a high-definition television signal converted to a standard signal is displayed as it is on a wide display having an aspect ratio of 16: 9, it returns to a video signal having no distortion. In this embodiment, the distortion caused by the frequency conversion and the correction of 12/11 times in the horizontal direction to be performed by the high-definition television receiver can be performed at one time. There is an effect that can be obtained.

Even when the aspect ratio of the display device is 4: 3, the vertical and horizontal enlargement factors are independently adjusted to correct the signal distortion due to the difference in the aspect ratio of the display device. Is possible.

Next, stabilization of a video signal, which is a second object of the present invention, will be described with reference to FIG. In FIG. 12, reference numeral 1201 denotes an input terminal of a video signal; 1202, a video processing circuit for performing digitization, sequential scanning, and the like of the video signal; 1203, a display; 1204, a synchronization processing circuit for performing synchronization processing and the like on the input video signal; Is a deflection circuit for driving the display, and the others are FIGS.
This is the same as the embodiment. In a conventional clock generation method for a digital television or the like, a synchronization circuit 1204 for creating a write clock for the first memory circuit 103,
To generate a read clock for the memory circuit 104 of FIG.
Clock generation circuit 212, the display 1203
And a circuit having three types of PLL loops. Therefore, when these are cascaded, if there is a large jitter in the input signal, the ability to follow the jitter is poor, and the jitter is displayed with emphasis. In the present invention, as shown in FIG. 12, since the first clock generation circuit 211 is constituted by an independent clock generation circuit using a crystal oscillator or the like, a jitter is given to a circuit having two loops at the subsequent stage. Absent. That is, the amount of jitter does not increase more than the jitter component originally generated in the synchronization processing circuit 1204.

The clock generation circuit 211 shown in FIG. 12 has, for example, 28.6 which is eight times the frequency of the color subcarrier 3.58 MHz.
This is an oscillation circuit using a stable clock having an oscillation frequency of 3 MHz, that is, a crystal oscillator or the like. The frequency is very close to the clock generated by the synchronization processing circuit 1204, but synchronization is not obtained. Therefore, if a simple independent clock is used, the input video signal and the first memory circuit 10
3, the amount of shift gradually increases, and if the shift is by the memory capacity, the continuity of the video signal is broken. FIG. 13 shows an example of the configuration of the memory circuit 103 and its peripheral circuits for preventing the failure of the memory. In FIG. 13, reference numeral 1301 denotes an input terminal of a video signal;
1302 is an output terminal, 1303 and 1304 are vertical synchronization signals and clocks supplied from the synchronization processing circuit 1204, 1305 is a field memory, 1306 and 1307
Is a counter, 1308 and 1309 are decoders, 1310 is a delay circuit, and others are the same as those in FIG.

In FIG. 13, the field memory 1
The write clock 305 is a clock from the input terminal 1303 synchronized with the video signal, and the write clock is also the clock of the counter 1306. The reading clock of the field memory 1305 is
This is a stable clock generated by the clock generation circuit 211, and this clock is also supplied to the counter 1307. The count values of the counters 1306 and 1307 are decoded by the decoders 1308 and 1309, and write reset and read reset of the field memory 1305 are performed. In the case of a normal signal, a deviation amount of a stable clock is about two lines in one field even in a video signal having a large jitter. Therefore, if a memory having a sufficient capacity such as a field memory is used and the delay circuit 1310 or the like is used for the write reset and the read reset so as to have a time difference of about two lines or more, the video signal can be reduced. Can be taken during the vertical retrace interval. Further, in the embodiment shown in FIG. 13, both the write counter 1306 and the read counter 1307 have a delay of several lines while maintaining the phase of the vertical synchronizing signal supplied from the input terminal 1304. , The memory can be prevented from being broken due to a frequency difference between the write clock and the read clock.

However, in the method shown in FIG. 13, since the reading counter 1307 is reset irrespective of the reading clock supplied from the clock generating circuit 211, the count value of the counter 1307 is decoded. The horizontal synchronizing signal for the display created in this manner does not maintain its periodicity at the time of reset. That is,
It is necessary to improve the followability of the deflection circuit of the display to the horizontal synchronization signal so that the video signal is not disturbed.

As described above, by using the circuits having the configurations shown in FIGS. 12 and 13, it is possible to supply a high-quality video signal even to an input signal containing much jitter.

The clock generation circuit 2 has been described so far.
The frequency of the clock generated in 11 has been extremely close to the clock generated in the synchronization processing circuit 1204. That is, the oscillation frequency of the crystal oscillator is 8 fsc = 28.6363, which is eight times the frequency of the color subcarrier fsc = 3.579545 MHz.
6 MHz. As described above, when the oscillation frequency of the stable clock of the first clock generation circuit 211 is 8 fsc, the frequency of one line is necessarily about 31.5 kHz, which is the double speed horizontal frequency of NTSC. Originally, a television system having a wide display as in the present invention is considered in accordance with the spread of high-definition television. Therefore, the system must be capable of displaying high-definition television. Normally, when displaying high-definition television, the display is designed to be capable of supporting two modes, that is, two types of horizontal deflection frequency of 31.5 kHz and 33.75 kHz, and corresponding to the input signal of high-definition television. I have. Here, the first clock generation circuit 2
If the oscillation frequency of the 11 stable clocks is set to about 30.7125 MHz, the horizontal frequency for 910 pixels is approximately 33.75 kHz, which matches the horizontal frequency of high-definition television, There is no need to support mode. In this case, the reading clock of the first memory circuit 204 is faster than the writing clock, so that at least a memory capacity of about 40 lines is required. Further, when such a conversion of the horizontal scanning frequency is performed, the number of scanning lines increases from 525 to almost 562. That is, this is equivalent to a reduction in the interval between the scanning lines, and the displayed picture is displayed by being crushed in the vertical direction.
The ratio of this distortion is (525 / 562.5) = 0.93. Therefore, in order to always drive the display at the horizontal synchronization frequency of a high-definition television, it is necessary to enlarge the display vertically (562.5 / 525) times. For example, if the vertical enlargement is performed about (16/15) times, a video signal without distortion can be displayed on a display of a high-definition television. Therefore, the deflection circuit can be configured to support only a single frequency while maintaining the same function, and simplification of convergence and simplification of the high-voltage circuit can be realized, which is effective in reducing the cost of the system.

As described above, according to this embodiment,
When a video signal having an aspect ratio of 4: 3 is input, the input video signal is stored in the second memory circuit 205
After time compression, the magnification can be arbitrarily increased.

Further, according to this embodiment, since the vertical filter circuit 201 and the horizontal filter circuit 202, and the vertical enlargement control circuit 209 and the horizontal enlargement control circuit 210 are independent, the vertical enlargement ratio and The horizontal magnification can be arbitrarily and independently determined.

In the present embodiment, the second memory circuit 205 expands the data after performing horizontal time compression. If the time axis compression is not performed before the horizontal enlargement, it is necessary to reduce the horizontal when the enlargement ratio is 4/3 or less and to enlarge when the enlargement ratio is 4/3 or more. At this time, since the vertical direction is always enlarged, the control circuit becomes complicated. When time compression is performed before the enlargement as in this embodiment, the enlargement in the horizontal direction is controlled by the same control circuit when the enlargement ratio is 4/3 times or less or 4/3 times or more. Can simplify the system.

FIG. 14 shows another embodiment of the present invention. Each element in FIG. 14 is the same as in the embodiment of FIG. In the embodiment of FIG. 2, the write clock and the read clock of the first memory circuit 204 are different, and in particular, the read clock uses a stable clock. However, if the write clock and the read clock are different,
As shown in the above-described embodiment, it is necessary to forcibly reset to correct the deviation between writing and reading. For this reason, discontinuity occurs in the synchronization signal, which may cause screen blur. In the present embodiment, the write clock and the read clock of the first memory 204 are the same to prevent discontinuity of the synchronous circuit. The clock generation circuit 1
Reference numeral 401 denotes a clock having a frequency about 4/3 times higher than that of the first clock, which is generated by using a PLL circuit. No discontinuity occurs in the synchronization signal. Other operations of this embodiment are exactly the same as those of the embodiment of FIG. According to the present embodiment, it is possible to display an enlarged video signal without synchronization blur on a 16: 9 display.

[0054]

According to the present invention, a plurality of magnifications (for example, 7
/ 6 times, 5/4 times, 4/3 times, etc.). Further, by stabilizing the clock, it is possible to supply a video signal with less jitter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing details of the embodiment of FIG. 1;

FIG. 3 is a diagram showing a display example of a video signal on a display device having an aspect ratio of 16: 9, 4: 3.

FIG. 4 is a block diagram showing a conventional enlargement method.

FIG. 5 is a diagram illustrating the principle of vertical enlargement.

FIG. 6 is a principle diagram of vertical enlargement according to the present invention.

FIG. 7 is a diagram showing an example of a horizontal compression circuit according to the present invention.

FIG. 8 is a block diagram showing a vertical filter unit according to the present invention.

FIG. 9 is a diagram showing a method of controlling the horizontal enlargement memory of the present invention.

FIG. 10 is a block diagram of a horizontal filter unit according to the present invention.

FIG. 11 is a principle diagram of a horizontal filter of the present invention.

FIG. 12 is a block diagram of the present invention including a synchronization circuit.

FIG. 13 is a block diagram showing a method of controlling a field memory according to the present invention.

FIG. 14 is a block diagram showing another embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of a mixer of the present invention.

FIG. 16 is a block diagram showing a configuration of a coefficient generation circuit according to the present invention.

[Explanation of symbols]

101: video signal input terminal, 103: synchronization signal input terminal, 104, 105: first and second memory circuits, 10
6 ... Spatial filter circuit, 107 ... Enlargement control circuit, 108
... Synchronization processing circuit, 201 ... Vertical filter circuit, 202 ...
Horizontal filter circuit, 203: frame insertion circuit, 204: vertical enlargement control circuit, horizontal enlargement control circuit, 206, 207: first and second clock generation circuits, 710, 711, 804
... 1H delay memory, 805, 1007 ... Mixer, 120
2. Video processing circuit 1203 Display 1204
... Synchronization processing circuit, 1205 ... Deflection circuit, 1305 ... Field memory, 1306, 1307 ... Counter, 130
8, 1309... Decoder, 1504, 1505, 150
8: coefficient unit, 1506, 1509: adder, 1507 ...
Subtracter, 1605: enlargement ratio setting circuit, 1606: counter, 1607: adder, 1608: latch circuit.

[Procedure amendment]

[Submission date] December 15, 1999 (1999.12.
15)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Hirahata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Hitachi Media Works, Ltd. (72) Inventor Haruki Takada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Hitachi, Ltd.Video Media Research Laboratories (72) Inventor Mitsuo Konno 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Video Media Lab. Hitachi Image Information System Co., Ltd. (72) Inventor Kazuhiro Kaizaki 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the AV Equipment Division of Hitachi, Ltd. (72) Takaaki Matino 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture (72) Atsushi Haratani, AV Equipment Division, Hitachi, Ltd. 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. AV Equipment Division

Claims (15)

[Claims] 1. A television receiver comprising an enlarged screen display circuit for inputting a video signal and performing an enlargement process, wherein the television receiver displays an image signal enlarged by the enlarged screen display circuit on a screen. Controlling the storage means for storing the video signal, a spatial filter means for performing vertical and horizontal filtering on the video signal read from the storage means, and controlling the storage means and the spatial filter means A television receiver, wherein the enlargement control unit performs control of the storage unit and control of the spatial filter unit in synchronization with each other. 2. A television receiver comprising an enlarged screen display circuit for inputting a video signal and performing an enlargement process, wherein the television receiver displays an image signal enlarged by the enlarged screen display circuit on a screen. A synchronous processing means for outputting a write clock and a read clock having a higher frequency than the write clock; and the video signal is written by the write clock output from the synchronous processing means, and the video signal is written by the read clock. A storage unit from which a signal is read, a spatial filter unit for performing vertical and horizontal filtering on a video signal read from the storage unit in accordance with an input coefficient, and controlling a read stop cycle of the storage unit Together with generating coefficients to be used in the pre-filter processing and outputting the coefficients to the spatial filter means A television receiver, comprising: an enlargement control unit, wherein the enlargement control unit synchronously performs a read stop control of the storage unit and an output of the coefficient to the spatial filter unit. 3. A television receiver comprising an enlarged screen display circuit for inputting a video signal and performing an enlargement process, wherein the television receiver displays an image signal enlarged by the enlarged screen display circuit on a screen. A synchronous processing means for outputting a write clock and a read clock having a higher frequency than the write clock; and the video signal is written by the write clock output from the synchronous processing means, and the video signal is written by the read clock. A storage unit from which a signal is read, a spatial filter unit for performing a vertical and horizontal filtering process on a video signal read from the storage unit in accordance with an input coefficient, and a periodic unit using a settable magnification. Calculating the coefficients used for the filtering process and calculating the spatial filtering means. And a magnification control means for controlling a read stop cycle of the storage means in synchronization with the arithmetic processing. 4. The television receiver according to claim 1, wherein said video signal is a video signal which is sequentially scanned. 5. The enlargement control means controls a read stop cycle of the storage means and generates a coefficient used for a filtering process of the spatial filter means in accordance with a set enlargement magnification. Item 3. A television receiver according to item 2. 6. The television receiver according to claim 2, wherein said storage means includes first and second storage means.
A first clock generating means for generating a first clock having a frequency substantially equal to a reference clock synchronized with an input video signal, and using the first clock. Third clock generating means for generating a second clock having a frequency approximately 4/3 times that of the first clock, wherein the reference clock is used as a write clock for the first memory circuit, and a read clock is used as the read clock. A television receiver, wherein the second clock is used as the second clock, the second clock is used as a write clock of the second memory circuit, and the third clock is used as a read clock. 7. The television receiver according to claim 2, wherein said storage means includes first and second storage means.
Wherein the synchronization processing means has reference clock generation means for generating a reference clock synchronized with the input video signal, and further comprises a first clock having a frequency substantially equal to the frequency of the reference clock. A first clock generating means which is generated independently of the reference clock generating means, and a second clock having a frequency approximately 4/3 times higher than the first clock is generated by using the first clock. A second clock generating means, wherein the reference clock is used as a write clock for the first memory circuit, the first clock is used as a read clock, and the first clock is used as a write clock for the second memory circuit. , Wherein the second clock is used as a read clock. 8. The television receiver according to claim 7, wherein said first clock generating means generates a clock having a frequency such that a horizontal frequency is substantially equal to a horizontal frequency of a high-definition TV signal. A television receiver characterized in that a high-definition TV signal can be displayed on a display. 9. A television receiver configured to write a video signal to a storage means by a write clock, read the video signal from the storage means by a read clock having a higher frequency than the write clock signal, and perform an enlargement process. 3. The television receiver according to claim 1, wherein the write clock is created in synchronization with an input video signal, and the read clock is created independently of the write clock. 10. A television receiver, comprising: an enlarged screen display circuit for inputting a video signal and performing an enlargement process, wherein the television receiver displays an image signal enlarged by the enlarged screen display circuit on a screen. Is a write clock generating means for generating a write clock synchronized with the video signal,
Read clock signal generating means for generating a read clock signal having a higher frequency than the write clock; and a video signal is written by the write clock from the write clock generating means, and the video signal is written by the read clock from the read clock generator. A storage unit from which the signal is read, and a spatial filter unit that obtains an enlarged video signal by performing a filtering process in a vertical direction and a horizontal direction on the video signal read from the storage unit. A television receiver, wherein the television receiver is created asynchronously with the write clock and independently of the write clock. 11. The read clock generating means is constructed using a crystal oscillator.
A television receiver according to item 1. 12. A video signal read from a memory at a speed higher than a writing speed is filtered in a horizontal and vertical direction using given coefficients to obtain an enlarged video signal. A television receiver comprising an enlarged screen display circuit and displaying a video signal enlarged by the enlarged screen display circuit on a screen, wherein the enlarged screen display circuit periodically performs arithmetic processing using a settable enlargement magnification. A television receiver having a calculation means for calculating a coefficient used for the filter processing. 13. The television receiver according to claim 12, wherein said arithmetic means performs arithmetic processing of said coefficient in one horizontal line cycle when performing vertical filter processing. 14. The television receiver according to claim 12, wherein said arithmetic means performs arithmetic processing of said coefficient in one dot cycle when performing horizontal filtering. 15. The television receiver according to claim 12, wherein said arithmetic means outputs a control signal for controlling reading of said memory in synchronization with said coefficient arithmetic processing.