JP2000138843A - Horizontal afc processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a horizontal AFC processing circuit that can prevent the occurrence of image distortions on an upper part of a screen in a nonstandard mode. SOLUTION: A phase comparator 12, that is gated by a gate signal denoting a position of a horizontal synchronizing pulse from a horizontal count-down circuit 18, compares a phase of an AFC reference signal with the phase of an external horizontal synchronizing signal. However, in the nonstandard mode where vertical synchronization is not taken, no gate signal is received even for a macro vision signal period, but the gate operation is conducted to quickly pull-in the horizontal synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal AFC processing circuit for generating an internal horizontal timing signal synchronized with an externally input horizontal synchronizing signal, and more particularly to processing for a macro vision signal included in the horizontal synchronizing signal.

[0002]

2. Description of the Related Art A horizontal AFC is used as a circuit for processing a horizontal synchronizing signal of a video signal used in a television receiver or the like.
Circuits are known. The horizontal AFC circuit includes a phase comparator, a voltage controlled oscillator, a horizontal countdown circuit, and a PLL (Phase Locked Loop) circuit including a low-pass filter. (A horizontal synchronizing signal) which is internally controlled.

Here, a video signal recorded on a video tape may include a macrovision signal for preventing illegal copying. This macro vision signal is inserted between the horizontal synchronizing signal period in which the horizontal synchronizing pulse exists and the video signal period. For the horizontal AFC circuit,
Acts as noise. That is, the macrovision signal has a large amplitude change, which may be erroneously detected as a horizontal synchronizing pulse, and the horizontal timing signal may be synchronized with this.

Conventionally, in a predetermined horizontal period (macrovision signal period) in which a macrovision signal exists,
Gate the detection of an external horizontal sync pulse so that the horizontal AFC operation is performed only during the horizontal sync signal period,
Prevents adverse effects from macrovision signals.

In a television receiver, a vertical synchronization signal from the outside is detected to perform vertical synchronization. NT
In the SC video signal, one field is 262.5H.
(H is one horizontal line) and is constant. Therefore, in order to avoid the influence of noise, the vertical synchronization signal is set to 262.5H.
When it is detected in a cycle, the number of horizontal lines is counted by an internal vertical countdown circuit, and a vertical timing signal (an internal vertical synchronization signal for controlling a vertical drive or the like) is generated. Such a mode is called a standard mode. On the other hand, when an external vertical synchronizing signal is not detected at a period of 262.5H, the only option is to detect an input vertical synchronizing signal and operate in synchronization with the detected vertical synchronizing signal. Such a mode is called a non-standard mode. For example, at the time of special reproduction such as fast forward or rewind of a home VTR or the like, a pseudo vertical synchronizing signal is generated.

[0006]

As described above, the horizontal A
In the FC circuit, during the macrovision signal period, a gate is provided so as not to detect the horizontal synchronization pulse, thereby suppressing the adverse effect of the macrovision signal.

However, during special playback of a VTR,
There is a demand to pull in the horizontal sync signal as soon as possible after the vertical sync signal. If the pull-in of the horizontal sync signal is delayed, a phase error remains even after entering the video signal period, and the image at the top of the TV screen is distorted. Occurs.

In the macro vision signal period,
Lowering the gain in the horizontal AFC circuit has been used to suppress the adverse effects. However, in this case as well, the draw-in of the horizontal synchronizing signal is delayed, and the problem that the upper part of the screen is distorted similarly occurs.

The present invention has been made in view of the above problems, and has as its object to provide a horizontal AFC processing circuit that can prevent image distortion at the upper portion of a screen in a non-standard mode.

[0010]

The present invention compares the phase of a horizontal synchronization signal input from the outside with the internal horizontal timing signal, and synchronizes the internal horizontal timing signal with the external horizontal synchronization signal. A horizontal AFC circuit for performing an AFC operation to generate a vertical timing signal according to its own count result in a standard mode and a vertical timing signal according to a vertical synchronization signal input from the outside in a non-standard mode. When the timing generation circuit and the vertical countdown circuit are operating in the standard mode, the gain of the AFC operation in the macrovision signal period in which the macrovision signal is present in the horizontal synchronization signal is suppressed as compared with the other periods, When the vertical countdown system is operating in non-standard mode, the macro And cancels the gain suppression of AFC operation ® tone signal period.

In the standard mode in which the vertical synchronization is established, the horizontal AFC operation is suppressed, and the adverse effect on the horizontal synchronization due to the macrovision signal is eliminated. On the other hand, in a non-standard mode in which vertical synchronization is not established, there is a demand to quickly acquire a synchronization signal. Therefore, the horizontal AFC operation is not suppressed even during the macrovision signal period, and the pull-in of the horizontal synchronization signal is accelerated.
As a result, the horizontal synchronizing signal can be pulled in by the video signal period, and the occurrence of distortion at the top of the screen can be effectively prevented.

As a means for suppressing the horizontal AFC operation, there is a method in which a gate is operated so as to perform the AFC operation only for a predetermined period in which a horizontal synchronization pulse is presumed to be present. Can also be adopted.
As a result, at the time of special reproduction of a home VTR or the like, it is possible to speed up the pull-in of the horizontal synchronizing signal and prevent the occurrence of distortion at the top of the screen.

Further, the present invention is characterized in that the gain of the AFC circuit is increased in other horizontal periods in several horizontal periods after the end of the macro vision signal period.

There are several horizontal periods between the macro vision signal period and the video signal period. In this few horizontal periods, there is no macro vision signal, and the horizontal synchronization pulse can be detected reliably. Therefore, by increasing the gain of the AFC circuit during this period, it is possible to increase the probability that the horizontal synchronization signal can be pulled in before the video signal period. Therefore,
The distortion at the top of the screen can be prevented.

[0015]

Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a horizontal synchronization signal processing circuit according to this embodiment. The horizontal synchronizing signal “a” obtained by, for example, reproducing a home VTR is input to the phase comparator 12. The horizontal synchronizing signal a is a signal which is at the H level for a predetermined period every horizontal period as shown in FIG. The phase comparator 12 includes an AFC reference signal c and a horizontal synchronization signal a supplied from a horizontal countdown circuit 18 described later.
And outputs a signal regarding the phase difference.
The AFC reference signal c is, as shown in FIG. 2 (b), a signal which goes to the L level during the H level period (horizontal synchronization pulse) of the horizontal synchronization signal a.
When two horizontal periods have elapsed, the level returns to the H level. The phase comparator 12 compares the horizontal synchronization signal a with the AFC reference signal c to obtain signals d1 and d2 shown in FIGS. The signal d1 is a signal which is at the H level only during a period T1 from the rise of the horizontal synchronization pulse to the fall of the AFC signal, and the signal d2 is an H level during the period T2 from the fall of the AFC signal to the rise of the horizontal synchronization pulse. This is the signal. Therefore, T1 = T2 in a state where the AFC reference signal falls just in the middle of the H level period of the horizontal synchronization pulse.

The signals d1 and d2 about the phase difference output from the phase comparator 12 are low-pass filters (LP
F) and is integrated there. That is, the LPF 14 is charged while the signal d1 is at the H level, and the signal d1 is charged.
The LPF 14 is discharged while the signal 2 is at the H level. Therefore,
When T1 = T2, the output from the LPF 14 becomes 0, and A
When the FC reference signal deviates from the horizontal synchronization signal a, a voltage signal according to the deviation is output from the LPF 14.

The output signal of the LPF 14 is supplied to a voltage controlled oscillator (VCO) 16, and the oscillation frequency of the VCO 16 is controlled. Therefore, the oscillation frequency of the VCO 16 is equal to the horizontal synchronization signal a detected by the phase comparator 12 and the AFC
It is controlled by the phase difference of the reference signal c.

The output of the VCO 16 is supplied to a horizontal countdown circuit 18 where it is counted. The horizontal countdown circuit 18 generates an AFC reference signal c in response to the countup of one horizontal period set in advance, and supplies this to the phase comparator 12. For this reason, the phase comparator 12, the LPF 14, the VCO 16 and the horizontal
A loop (PLL) circuit is formed, and AFC
The VCO 16 is controlled so that the reference signal c is synchronized with the horizontal synchronization signal a. This PLL is called a horizontal AFC circuit.

The horizontal countdown circuit 18 includes a VCO 1
A plurality of timing signals are generated based on the count result of the signals from the control signal generator 6. That is, the horizontal countdown circuit 18 supplies a signal indicating one horizontal period to the horizontal deflection circuit 20. The horizontal deflection circuit 20 generates a horizontal deflection current of the CRT 22 and supplies the current to a horizontal deflection coil of the CRT 22. Thus, horizontal scanning is performed on the CRT 22.

The horizontal countdown circuit 18 generates a 2fH clock (fH indicates a horizontal synchronization signal frequency) based on the count result, and supplies the clock to the vertical countdown circuit 24. The vertical countdown circuit 24
The 2fH clock is counted and a plurality of timing signals are generated. That is, the vertical countdown circuit 24
A signal is obtained for one vertical period, and this is
To supply. The vertical deflection circuit 26 generates a vertical deflection current and supplies the current to a vertical deflection coil of the CRT 22. Thus, the CRT 22 performs vertical scanning.

The horizontal countdown circuit 18 generates a gate signal b for a period in which a horizontal synchronization pulse is estimated to be obtained, and supplies the gate signal b to the horizontal synchronization detection circuit 28, as shown in FIG. I do. The horizontal synchronization detection circuit 28 is supplied with a horizontal synchronization signal a, and the horizontal synchronization detection circuit 28 determines whether or not a horizontal synchronization pulse exists during the period specified by the gate signal b. And
If there is a horizontal synchronization pulse, it is determined that the state is a synchronous state, and if not, it is determined that the state is an asynchronous state. Then, a gate control signal as to whether or not a synchronization state is provided is supplied to the phase comparator 12. Note that the horizontal synchronization detection circuit 28 determines the synchronization state when a horizontal synchronization pulse is detected within a period specified by the gate signal b, for example, continuously for a plurality of times (for example, four times), and the horizontal synchronization detection circuit 28 detects the horizontal state even within one period. When a synchronous pulse cannot be detected, it is determined to be in an asynchronous state.

The phase comparator 12 is also supplied with a gate signal b from the horizontal countdown circuit 18. If the synchronization state is determined by the gate control signal f from the horizontal synchronization detection circuit 28, the gate signal b is used. The phase comparison between the horizontal synchronizing signal a and the AFC reference signal is performed only during the specified period, and when it is determined that the signal is out of synchronization, the phase comparison is performed irrespective of the gate signal b.

That is, the horizontal synchronizing signal a input from the outside contains noise. Therefore, in the synchronous state, by performing the phase comparison only during the period specified by the gate signal b, adverse effects due to noise are prevented.

The vertical countdown circuit 24 generates a forced switching signal e for a period during which the macro vision signal is present, and supplies the signal to the phase comparator 12. That is, the macrovision signal needs to be inserted during a period that does not affect the synchronization or the video signal, and as shown in FIG. 3, after the vertical synchronization signal period and the equivalent pulse period, and before the video signal starts. And the period is predetermined. Therefore, the vertical countdown circuit 24 generates a compulsory switching signal e for a period during which the macro vision signal exists based on the count result.

This forced switching signal e is supplied to the phase comparator 12. Based on the forced switching signal e, the phase comparator 12 performs the phase comparison only during the period specified by the gate signal b even in the asynchronous state.

This is a macrovision signal which is a signal which repeats a considerably large change of H level and L level.
This is because the possibility of erroneously detecting this as a horizontal synchronization pulse is considerably high. Therefore, by forcibly applying a gate during the period in which the macrovision signal exists, the adverse effect of noise based on the macrovision signal can be eliminated.

Here, it is also preferable to lower the gain of the AFC operation based on the output of the phase comparator 12 during the period when the macro vision signal exists. For example, VC
The response to the input voltage at O16 can be reduced,
The time constant of the LPF 14 can be changed or the phase comparator 1
The gain can be adjusted by changing the level of the output from 2. This can also reduce the adverse effect of the macrovision signal on horizontal synchronization detection.

Further, in the present embodiment, a vertical synchronization detecting circuit 30 is provided. This vertical synchronization detection circuit 30
Compares a vertical gate signal for vertical synchronization signal detection supplied from the vertical countdown circuit 24 with an externally input vertical synchronization signal. Here, the vertical gate signal indicates a period in which the vertical synchronization signal estimated from the count result of the vertical countdown circuit 24 should be located, and the vertical synchronization detection circuit 30 determines the period specified by the vertical gate signal. It is determined whether or not there is a vertical synchronization signal in the data.

If the vertical synchronizing signal is detected within the period specified by the vertical gate signal, the circuit is in a synchronized state,
According to the count result of the vertical countdown circuit 24,
The vertical deflection circuit 26 operates. This is called a standard mode. On the other hand, if the vertical synchronization signal is not detected during the period specified by the vertical gate signal, the circuit is in an asynchronous state, and the vertical deflection circuit 26 cannot operate according to the count result of the vertical countdown circuit 24. Therefore, in the asynchronous state, the vertical synchronization detection circuit 30 detects a vertical synchronization signal supplied from the outside, and outputs the signal to the vertical deflection circuit 26.
To supply. The vertical deflection circuit 26 operates based on an external vertical synchronization signal supplied from the vertical synchronization detection circuit 30. This is called non-standard mode. Here, the vertical countdown circuit 24 and the vertical synchronization detection circuit 30
Constitute a vertical timing generation circuit. Note that when a vertical synchronization signal is detected a plurality of times (eight times) in succession, the synchronization state is determined, and the mode shifts to the standard mode. It is preferable to shift to the mode.

The vertical synchronization detection circuit 30 generates a mode signal indicating whether it is operating in the standard mode or the non-standard mode, and supplies this mode signal to the forced switching signal control circuit 32. Then, the forcible switching signal control circuit 32 supplies the forcible switching signal e supplied from the vertical countdown circuit 24 to the phase comparator 12 according to the mode signal.
On and off.

That is, the forced switching signal control circuit 32
Supplies the forced switching signal e to the phase comparator 12 as it is when it is determined in the standard mode by the mode signal, but does not supply the forced switching signal e when it is determined in the non-standard mode. As a result, the forced switching signal e is not supplied to the phase comparator 12 in the non-standard mode. Therefore, in the state where horizontal synchronization is not established and in the non-standard mode, the phase comparator 12 cannot be gated by the gate signal b.

Therefore, in the non-standard mode, the phase comparator 12 compares the phase of the horizontal synchronization signal a with the AFC reference signal even during the period in which the macro vision signal exists. In the non-standard mode, a pseudo vertical synchronization signal or the like is input, and the vertical synchronization signal is considerably shifted. Therefore, even during the period in which the macrovision signal is present, the horizontal synchronization pulse can be detected, and the horizontal synchronization signal can be quickly drawn.

Note that the compulsory switching signal e is a signal that goes to the L level during the period in which the macro vision signal exists. Therefore, if the mode signal is a signal which becomes H level in the standard mode and L level in the non-standard mode, the forced switching signal control circuit 32 can be formed by an OR gate. In this case, it is also preferable to set the gain of the horizontal AFC circuit low during the period in which the macrovision signal exists.

Further, in the present embodiment, as shown in FIG. 3, in the vertical countdown circuit 24, a gain control signal g indicating several horizontal scanning periods from the end of the period in which the macrovision signal exists to the start of the video signal. Occurs. Then, the gain control signal g is supplied to the phase comparator 12. The phase comparator 12 increases the gain of the horizontal AFC circuit based on the gain control signal g.

Thus, the oscillation of the VCO 16 in the horizontal AFC circuit can be made to follow the horizontal synchronization pulse detected during this period at high speed. Therefore, horizontal synchronization can be achieved before the image period starts, and the occurrence of disturbance at the upper part of the screen can be effectively prevented.

The configuration for increasing the gain of the horizontal AFC circuit using the gain control signal g is effective also in a circuit that does not turn on / off the forcible switching signal e. In this case, during the macro vision signal period, the horizontal AF
It is preferable to lower the gain of the C circuit.

[0038]

As described above, according to the present invention,
It is possible to prevent the image from being bent at the top of the screen in the nonstandard mode.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a horizontal AFC processing circuit.

FIG. 2 is a waveform diagram of various signals.

FIG. 3 is a waveform diagram of another signal.

[Explanation of symbols]

12 phase comparator, 14 LPF, 16 VCO, 18
Horizontal countdown circuit, 20 horizontal deflection circuit, 22
CRT, 24 vertical countdown circuit, 26 vertical deflection circuit, 28 horizontal synchronization detection circuit, 30 vertical synchronization detection circuit, 32 forced switching signal control circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Osamu Tabata 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term in Sanyo Electric Co., Ltd. (reference) 5C020 AA16 AA32 CA07 5J106 AA02 AA03 BB04 CC01 CC21 CC38 CC41 CC52 DD17 EE01 GG04 KK03

Claims (2)

[Claims] 1. A horizontal AFC circuit for performing an AFC operation for comparing the phase of a horizontal synchronization signal input from the outside with the internal horizontal timing signal and synchronizing the internal horizontal timing signal with the external horizontal synchronization signal. A vertical timing generation circuit that generates a vertical timing signal according to its own count result in the standard mode, and generates a vertical timing signal according to a vertical synchronization signal input from the outside in the non-standard mode, When the vertical countdown circuit is operating in the standard mode, the AFC operation in the macrovision signal period in which the macrovision signal is present in the horizontal synchronization signal is suppressed in comparison with other periods, and the vertical countdown system is non-standard. When operating in the macro mode, the AFC Horizontal AFC processing circuit and cancels the inhibition of the work. 2. A horizontal AFC circuit for performing an AFC operation for comparing the phase of a horizontal synchronization signal input from the outside with the internal horizontal timing signal and synchronizing the internal horizontal timing signal with the external horizontal synchronization signal. A vertical timing generation circuit that generates a vertical timing signal according to its own count result in the standard mode, and generates a vertical timing signal according to a vertical synchronization signal input from the outside in the non-standard mode, A horizontal AFC processing circuit characterized in that the gain of the AFC circuit is increased in other horizontal periods during several horizontal periods after the end of the macrovision signal period.