JP2000133695A - Manufacture of thin-film multi-layered substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a thin-film multi-layered substrate which can be made high in accuracy and reliability by preventing erroneous positional recognition of an alignment mark. SOLUTION: In the method for manufacturing a thin-film multi-layered substrate formed by electrically connecting laminated pattern layers 18 together by via posts 26 via an insulating layer 30, an alignment mark base 21 larger in planar dimensions than an alignment mark of a predetermined planar shape is formed when the patterns 18 are formed, alignment marks 20 of a predetermined planar shape are formed on the alignment mark base 21 in the form of posts when the via posts 26 are formed to the patterns 18, an insulating layer 30 is formed so that the via posts 26 and post-shaped alignment marks 20 are buried in the layer, and then subjected to a flattening process so that end faces of the via posts and alignment marks are exposed to a surface of the insulating layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a thin film multilayer substrate, and more particularly to a method for forming an alignment mark which enables high-precision alignment when a wiring pattern is formed in multiple layers. is there.

[0002]

2. Description of the Related Art A thin film multilayer substrate is formed by laminating wiring patterns in multiple layers with an insulating layer interposed therebetween and electrically connecting the patterns between the layers with vias. At the time of manufacturing, the patterns are formed by laminating the patterns in order from the lower layer, and at that time, the patterns must be formed while being aligned with each other. For this reason, in the production of a thin-film multilayer substrate, an alignment mark for alignment is formed at the same time when a pattern is formed, and the alignment mark is aligned as a reference for patterning.

FIG. 6 shows a conventional method for forming a wiring pattern on the surface of a substrate 10 using an alignment mark. FIG. 6A shows the pattern 18 of the first layer on the surface of the substrate 10.
And a state in which the alignment mark 20 is formed. The pattern 18 and the alignment mark 20 are
Is formed as a conductive layer by raising a plating metal in a predetermined pattern. FIG. 6B shows a state in which the surface of the base material 10 is covered with the resist 22 and exposed and developed with the alignment mark 20 as a reference.

FIG. 6C shows a via post 2 formed by electrolytic plating.
6 and the alignment mark 2
This is a state in which 0 is raised. The reason why the alignment mark 20 is formed to be raised in a post shape is to use the raised alignment mark 20 for positioning in the next layer. FIG. 6D shows the seed layer 12.
After etching, pattern 18, via post 26,
With the insulating material coated so that the alignment mark 20 is buried, the insulating layer 30 is thereby formed.

[0005]

By the way, the insulating layer 30
A resin material such as polyimide is used as the material. However, if the resin material is coated with a liquid resin and then cured, the resin material shrinks, and the surface of the insulating layer 30 becomes uneven. This is because the thickness of the resin material covered varies depending on the presence or absence of the pattern 18 and the via posts 26, and shrinks more at a portion where the resin material is thickly covered. In order to eliminate the irregularities, as shown in FIG. 7A, the surface of the insulating layer 30 is covered with a stopper metal 32 and then ground so that the surface becomes a flat surface (FIG. 7B). Next, the stopper metal 32a remaining on the surface of the insulating layer 30 is removed by etching (FIG. 7C). It is possible to confirm that the end faces of the via post 26 and the alignment mark 20 are exposed from the insulating layer 30 by the stopper metal 32.

Next, the second layer pattern can be formed in the same manner as the first layer by applying a conductive film on the surface of the insulating layer 30 and patterning. Since the alignment mark 20 formed on the first layer is formed in accurate alignment with the pattern 18, the alignment mark 20 is used as a reference position for forming the pattern of the second layer. The two-layer pattern can be accurately aligned with the first-layer pattern. By the way, in the conventional manufacturing method, as shown in FIG. 7C, when the insulating material is formed, the resin material shrinks to form a step near the alignment mark 20 due to the sink of the resin material. There's a problem.

FIG. 8 is an enlarged view showing the vicinity of the alignment mark 20, and shows that the upper portion of the alignment mark 20 is ground, and the resin material of the insulating layer 30 is formed in a step shape around the upper portion. Since the alignment with the alignment mark 20 is performed by irradiating a laser beam from above the alignment mark 20 and performing scanning, if there is a step portion near the alignment mark 20, the step portion is formed when the laser beam is scanned. In some cases, the intensity of the reflected light increases at the edge of the mark, and the edge of the step portion may be erroneously recognized as the position of the alignment mark 20. The thin-film multilayer substrate has extremely high-density patterns and requires extremely high precision in manufacturing. Misidentification of the alignment mark 20 causes a positional shift in such pattern formation, resulting in a product defect. In addition, when wiring layers are formed in multiple layers, it is necessary to perform accurate alignment in all the wiring layers. To be able to perform accurate alignment using the alignment mark as a reference position is extremely important in the production of a thin film multilayer substrate. It has important meaning.

According to the present invention, in the manufacturing process of such a thin film multilayer substrate, it is possible to form a pattern with high precision by preventing a positional shift of a pattern between layers, and to reliably form a highly reliable thin film multilayer substrate. It is an object of the present invention to provide a method for manufacturing a thin-film multilayer substrate that can be obtained.

[0009]

To achieve the above object, the present invention comprises the following arrangement. That is, a via post is erected on a pattern, an alignment mark for positioning is formed in a post shape, the pattern, the via post and the alignment mark are covered with an insulating layer so as to be buried, and the surface of the insulating layer is stoppered. After covering with a metal, a flattening process is performed to expose the surface of the alignment mark from the insulating layer so that the end face of the alignment mark can be identified and a pattern can be formed. Also, the alignment mark is formed in a post shape on an alignment mark base having a large plane dimension, and the flattening process is performed. Further, when forming the pattern, an alignment mark serving as a reference position for patterning in the layer is formed, and an alignment mark is formed in a post shape on the via post and the alignment mark base with reference to the alignment mark. It is characterized by the following. Also, a via post is erected on the pattern, an alignment mark for positioning is formed in a post shape, and the pattern, the via post and the alignment mark are covered with an insulating layer so as to be buried, and the surface of the insulating layer is stoppered. The method of manufacturing a thin-film multilayer substrate, wherein after coating with a metal, a flattening process is performed to expose the surface of the alignment mark from the insulating layer so that the end face of the alignment mark can be identified and a pattern can be formed, When the surface is covered with a stopper metal, a portion covering the alignment mark and an insulating layer in the vicinity thereof are provided so as to be exposed, and the flattening process is performed.

[0010]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 1 to 3 show one embodiment of a method for manufacturing a thin-film multilayer substrate according to the present invention, and show steps up to forming a first-layer wiring pattern on a base material 10. FIG. 1A shows a base material 10 of a thin film multilayer substrate.
First, a seed layer 12 used as a current-carrying layer at the time of electrolytic plating is provided on the surface of the substrate 10 (FIG. 1).
(b)). The seed layer 12 is formed by sputtering a conductive metal such as titanium or copper. The seed layer 12 only needs to be able to secure electrical conductivity, and does not need to be formed so thick.

FIG. 1C shows a state in which a plating resist 14 for forming a pattern is applied to the surface of the seed layer 12. FIG. 1D shows a state in which the resist 14 is exposed and developed to form a resist pattern 14a. In the figure, 1
6a is a portion for forming a wiring pattern, 17a, 17
“b” indicates a portion for forming an alignment mark. 17a
Is used as an alignment mark used when forming a via post in alignment with the pattern formed in the first layer, and 17b forms the base of the alignment mark used in the alignment in the second layer It is for. 17a is formed to have the same size as the alignment mark, whereas 17b is formed to be larger than the alignment mark.

After forming the resist pattern 14a, electrolytic plating is performed using the seed layer 12 as a current-carrying layer, and a pattern 18 and alignment marks 20 are formed on the surface of the seed layer 12.
The alignment mark base 21 is formed by raising the plating metal (FIG. 1E). FIG. 1F shows that the resist pattern 14a formed on the surface of the seed layer 12 is removed, and the pattern 18, the alignment mark 20,
This shows a state where the alignment base 21 is formed. Alignment mark 20 and alignment mark base 2
1 is arranged in a predetermined arrangement. The more these marks are provided, the more the detection position accuracy can be improved.

FIG. 2 shows a step of forming a via 26 for electrically connecting the pattern 18 of the first layer and the pattern of the second layer. FIG. 2A shows the pattern 18 and the alignment mark 2.
In this state, a resist 22 is applied to the surface of the seed layer 12 on which 0 is formed. The resist 22 is formed thicker than the resist 14 used when forming the pattern 18 and the like. FIG. 2B shows a state in which the resist 22 is exposed and developed to form a resist pattern 24 for forming a via. Resist 2
When exposing No. 2, the alignment mark 20 formed earlier is used as a reference position. Since the position of the alignment mark 20 is accurately defined with respect to the pattern 18, a via can be formed accurately by exposing the alignment mark 20 to the reference position. 24a
Is a concave portion for forming a via post, and 24b is a concave portion for forming an alignment mark 20 on an alignment mark base 21.

FIG. 2C shows a state in which the resist pattern 24 is removed after electrolytic plating is performed using the resist pattern 24 as a plating mask and the seed layer 12 as a conductive layer.
By raising the plating metal by electrolytic plating, the via posts 26 are formed on the pattern 18, and the alignment marks 20 are formed on the alignment mark base 21 by stacking. The alignment marks 20 formed by stacking are used for alignment of the second layer. Therefore, the alignment mark 20 formed on the alignment mark base 21 needs to be formed to a required size for alignment.

FIG. 3 shows a step of forming an insulating layer next. FIG. 3A shows a step of etching the seed layer 12 to make the pattern 18 and the alignment mark base 21 electrically independent. Since the seed layer 12 is only about 1/10 thicker than the pattern 18 and the alignment mark base 21, the pattern 18 and the alignment mark base 2 can be formed without using a resist or the like.
1 can be etched.

FIG. 3B shows that after the seed layer 12 is etched, an insulating material such as polyimide is coated.
This shows a state where 0 is formed. When the insulating material is coated and cured, the surface of the insulating layer 30 becomes uneven according to the coating thickness of the resin material. In other words, the surface of the insulating layer 30 protrudes in a portion where the via post 26 and the alignment mark 20 are formed, and in a portion where the pattern 18 is not formed, the resin material has a large degree of shrinkage. Become. FIG. 3C shows a state in which a stopper metal 32 is applied to the surface of the insulating layer 30. The stopper metal 32 is formed unevenly following the unevenness on the surface of the insulating layer 30.

FIG. 3D shows an insulating layer 30 formed on the uneven surface.
Is a state in which the surface is ground and flattened. Insulating layer 3
The grinding process of 0 is stopped when the stopper metal 32 remains in the thinly formed portion on the surface of the insulating layer 30. 32a is a stopper metal remaining on the surface of the insulating layer 30. A characteristic configuration of the present embodiment is that when the alignment mark 20 formed in a post shape on the alignment mark base 21 is ground, the insulating layer 30 around the alignment mark 20 is flush with the alignment mark 20 over a predetermined range. And no step is formed near the alignment mark 20.

FIG. 3E shows a state in which the stopper metal 32 is removed by etching, and the end face of the via post 26 is exposed on the upper surface of the insulating layer 30 and the alignment mark 20 is exposed. Thus, the first
A layer is formed. FIG. 4 shows an enlarged portion near the alignment mark 20. The alignment mark 20 is formed by exposing the surface and the end face of the insulating layer 30 to the same height, and no step is formed near the alignment mark 20. Accordingly, when the laser beam is scanned to detect the alignment mark 20, the alignment mark 20 is not erroneously recognized by the step formed near the alignment mark 20, and the alignment mark 20 is accurately recognized. Patterning becomes possible.

The second layer is formed by a process similar to the above-described method in which a seed layer is formed on the surface of the insulating layer 30 in FIG. 3E, a resist pattern is formed, and a pattern and an alignment mark are formed. Can be. Pattern 18
When forming an alignment mark, it is the same as forming an alignment mark for alignment in the layer and simultaneously forming an alignment base for forming an alignment mark for the third layer. By forming alignment marks for each layer and laminating the patterns in this way, it is possible to form each layer pattern with extremely high precision alignment, thereby providing a highly accurate and highly reliable thin film multilayer substrate. Can be obtained.

FIG. 5 shows another embodiment in which a thin-film multilayer substrate is formed so as not to mistakenly recognize an alignment mark during scanning with laser light. In this embodiment, when the surface of the insulating layer 30 is covered with the stopper metal 32 in the conventional manufacturing process of the thin film multilayer substrate shown in FIG. (FIG. 5A). In the conventional method, the portion where the alignment mark 20 is formed is covered with the stopper metal 32. Therefore, the stopper metal 32 remains in the vicinity of the alignment mark 20 during the planarization process. On the other hand, in the present embodiment, since the portion where the alignment mark 20 is formed is not covered with the stopper metal 32, the stopper metal 32 does not remain near the alignment mark 20 during the flattening process.

FIG. 5B shows an insulating layer 30 formed on an uneven surface.
Shows a state in which the surface of FIG. The stopper metal 32 partially remains on the surface of the insulating layer 30 due to the planarization process.
The portion near 0 is ground to a flat surface. FIG. 5C shows a state in which the stopper metal 32 has been removed by etching.
Thus, the insulating layer 3 near the alignment mark 20
By grinding 0 flat, it is possible to prevent misalignment of the alignment mark 20 during scanning with laser light.

In the vicinity of the portion where the alignment mark 20 is to be formed, as shown in FIG.
Has a raised shape following the shape of the alignment mark 20. Therefore, a step may be left in the vicinity of the alignment mark 20 depending on the grinding amount at the time of the flattening process. However, since the alignment mark is usually arranged at the outer edge of the workpiece, the grinding process of the flattening process is performed. In this case, it is not difficult to grind the portion in the vicinity of the alignment mark 20 flat together with the fact that the outer edge portion is more ground. According to the method of the present embodiment, there is an advantage that the recognition of the alignment mark 20 can be prevented by controlling the region where the insulating layer 30 is covered with the stopper metal 32.

[0023]

According to the method of manufacturing a thin-film multilayer substrate according to the present invention, as described above, the insulating layer is planarized so that the step portion of the insulating layer is formed near the exposed surface of the alignment mark. Can be prevented, and erroneous recognition of the alignment mark position can be prevented. This makes it possible to accurately align and pattern based on the alignment mark,
It is possible to manufacture a highly accurate and highly reliable thin film multilayer substrate.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing a step of forming a pattern on a base material using a thin-film multilayer substrate.

FIG. 2 is an explanatory view showing a step of forming a via post and an alignment mark.

FIG. 3 is an explanatory view showing a step of forming an insulating layer and performing a planarization process.

FIG. 4 is an enlarged sectional view showing a portion near an alignment mark.

FIG. 5 is an explanatory view showing a manufacturing process of another embodiment of the method for manufacturing a thin-film multilayer substrate.

FIG. 6 is an explanatory view showing a conventional manufacturing process of a thin film multilayer substrate.

FIG. 7 is an explanatory view showing a conventional manufacturing process of a thin film multilayer substrate.

FIG. 8 is an enlarged cross-sectional view showing a portion near a conventional alignment mark.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 base material 12 seed layer 14 resist 14 a resist pattern 18 pattern 20 alignment mark 21 alignment mark base 22 resist 24 resist pattern 26 via post 30 insulating layer

Claims (3)

[Claims] 1. A via post is erected on a pattern, an alignment mark for positioning is formed in a post shape, and the pattern, the via post and the alignment mark are covered with an insulating layer so as to be buried. After the surface is covered with a stopper metal, a flattening process is performed to expose a surface of the alignment mark from the insulating layer, thereby identifying an end face of the alignment mark and forming a pattern, thereby forming a pattern. A method for manufacturing a thin film multilayer substrate, comprising: forming an alignment mark in a post shape on an alignment mark base having a larger planar dimension than an alignment mark; and performing the flattening process. 2. When forming the pattern, an alignment mark serving as a reference position for patterning in the layer is formed, and a post-shaped alignment mark is formed on the via post and the alignment mark base with reference to the alignment mark. The method for manufacturing a thin-film multilayer substrate according to claim 1, wherein: 3. A via post is erected on a pattern, an alignment mark for positioning is formed in a post shape, and the pattern, the via post and the alignment mark are covered with an insulating layer so as to be buried. After the surface is covered with a stopper metal, a flattening process is performed to expose a surface of the alignment mark from the insulating layer, thereby identifying an end face of the alignment mark and forming a pattern, thereby forming a pattern. A method for manufacturing a thin-film multilayer substrate, comprising: when covering the surface of an insulating layer with a stopper metal, providing a portion to cover the alignment mark and an insulating layer in the vicinity thereof so as to be exposed, and performing the flattening process.