JP2000132264A - Electronic equipment using cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent malfunction from generating when a CPU sleeps. SOLUTION: When a CPU 1 enters in a sleep mode and an internal clock is stopped, a clock detection circuit 3 being hardware detects this matter. A gate circuit 5 interrupts an I/O signal from the CPU 1 based on a detection output signal of the clock detection circuit. Thus, loads such as a ventilating fan 7, a motor 11 and a 24 VDC power source 9 are turned to an off state. When the sleep mode is released and the internal clock of the CPU resumes its operation, the I/O signal becomes passable through the gate circuit 5 again because a detection output of the clock detection circuit is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device using a CPU, and more particularly to an electronic device such as a copying machine, a facsimile, a printer, and the like.

[0002]

2. Description of the Related Art Conventionally, a power switch (SW) of an electronic device.
A mechanical switch (SW) for turning on and off an AC input has been used. In the case of an electronic device having such a mechanical switch, the power consumption when the power switch is off is 0 W because no AC is input.

[0003] In recent years, devices having software switches have increased as mechanical switches.
In an electronic device using a software switch as a power switch, when the power is turned off, the device does not seem to operate, but in an outlet-in state (the power plug is connected to the outlet), the CPU operates around the operation unit, and Read the signal from the switch and start up the entire device.

In the case of a device having such a software switch, even when the power is off, a specific DC power supply unit and a controller unit are operating, so that about several watts of power is consumed when the power is off. At present, power saving is required even when the power is turned off. Therefore, when the power supply is turned off, the power is suppressed by lowering the switching frequency of the DC power supply. In the controller unit, the power is suppressed by shifting the CPU to the sleep mode.

[0005]

When the CPU is set to the sleep mode, the I / O of the CPU is controlled by software.
After the / O is disabled, the mode is shifted to the sleep mode. This is to prevent the internal clock from stopping when the CPU enters the sleep mode and the setting state of the register of the I / O port being left as it is. For example, when the CPU controls the load via the I / O port, it is intended to prevent a situation in which the sleep mode is entered with the data for turning on the load set.

However, when the I / O port is shifted to the sleep mode without disabling the I / O port due to a software problem or the like, the load is kept on.

SUMMARY OF THE INVENTION It is an object of the present invention to prevent the occurrence of a problem associated with the transition of the CPU to the sleep mode in an electronic device using the CPU.

[0008]

An electronic device according to the present invention has a function of stopping an internal clock in a sleep mode.
In an electronic device using a PU, based on a clock detection circuit that detects by hardware that the internal clock has been stopped by the sleep mode, and based on a signal indicating that the internal clock has been stopped from the clock detection circuit, Control means for disabling a predetermined load.

Here, "disable the load" means to keep the load in an inactive state. For example, an exhaust fan, a lamp, a motor, a clutch, a solenoid, a specific D
This corresponds to turning off the C power supply and the like.

As described above, the stop of the internal clock is reliably detected by the hardware, and the predetermined load is disabled so that the power consumption of the load can be reduced to 0 irrespective of the software control. it can.

The control means preferably releases the inoperable state of the load when the sleep mode is released and the internal clock of the CPU resumes its operation.

More specifically, the control means selectively supplies an I / O signal from the CPU to the driver in accordance with an output of the clock detection circuit and a driver for driving the load. It can be constituted by a gate.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a CPU-related configuration of a copying machine as an electronic apparatus according to the present invention. In the figure, reference numeral 1 denotes a microcomputer (CPU) having a built-in I / O and digital / analog conversion unit, an internal timer, and the like. In this example, the microcomputer operates based on a reference clock generated internally by a 10 MHz oscillator 12. I do. Reference numeral 2 denotes a frequency dividing counter, which divides an internal clock of the CPU 1 and converts it into a clock of 1 kHz. Reference numeral 3 denotes a clock detection circuit which detects an operation state of the 1 kHz clock. That is, the clock detection circuit 3 is a circuit that generates an H level signal when the internal clock is operating, and generates an L level signal when the internal clock is not operating. This detailed internal configuration example will be described later. 5
Is a gate circuit for conducting / cutting off an I / O signal output from the CPU 1 in accordance with the output of the clock detection circuit 3. Reference numeral 6 denotes a driver receiving the output of the gate circuit 5. This driver 6 controls loads 7 to 11. Here, the load 7 is an exhaust fan, the load 8 is a document lamp, the load 9 is a DC power supply (24 V), the load 10 is a clutch and a solenoid, and the load 11 is a motor. Reference numeral 4 denotes an operation unit operated by the user.

When a software switch (hereinafter, software SW) on the operation unit 4 is pressed, a signal is input to the CPU 1, and in response, the CPU 1 outputs a 24V start signal to the DC power supply. This activates the device.

When in the outlet-in state and the software SW is off, the CPU 1 is shifted to the sleep mode in order to suppress power consumption. First, the I / O data register (inside the CPU 1) is reset, and the I / O port is disabled. Thereafter, the internal clock is stopped by writing data indicating sleep to a sleep mode register (also in the CPU 1). The above operation is performed by software.

In the normal state of the device, as described above, C
Prior to the transition of PU1 to the sleep mode, all of its I / O ports are disabled by software.
There is a possibility that the device will shift to the sleep mode without resetting the data register of O. Therefore, in the present embodiment, the following means are provided.

When the sleep mode is entered and the internal clock is stopped, the input of the clock detection circuit 3 stops moving, so that the clock detection circuit 3 outputs an L-level signal to the gate circuit 5. As a result, all the gates in the gate circuit 5 are turned off, and all of the loads 7 to 11 are forcibly turned off.

FIG. 2 is a circuit diagram showing an example of the internal configuration of the clock detection circuit 3. The clock detection circuit 3 includes transistors Q1 to Q6, resistors R1 to R12, a capacitor C
1 and C2 as shown in the figure.

The operation of this circuit will be described with reference to the signal waveform diagrams of FIGS. FIG. 3 shows signal waveforms at points a to d when the internal clock of the CPU 1 is active. FIG. 4 shows signal waveforms at points a to d when the internal clock of the CPU 1 is stopped.

While the 1 kHz clock from the frequency dividing counter 2 is being input to the input a (FIG. 3, waveform a), the transistor Q1 repeats on / off (waveform b in FIG. 3). Accordingly, the transistor Q2 is repeatedly turned on / off, and the potential level of the capacitor C2 is maintained at a level at which the transistor Q3 is not turned on (waveform c in FIG. 3). As a result, the transistor Q4 is turned off and the transistor Q5 is turned on, and the transistor Q6 at the last stage is kept off. Therefore, as long as the clock is on, the clock detection circuit 3 keeps generating the H level output (waveform d in FIG. 3).

Since capacitor C1 is connected in series between the collector of transistor Q1 and the base of transistor Q2, capacitor C1 does not pass DC components. Therefore, if the input of the clock detection circuit 3 is fixed at L level or H level and does not change (waveform a in FIG. 4),
The base potential of the transistor Q2 becomes 0 (waveform b in FIG. 4). Therefore, the transistor Q2 remains off (waveform c in FIG. 3). At this time, the potential at point c in FIG.
The level at which the transistor Q3 turns on (here, 1.5
V). As a result, the transistor Q4 is turned on, Q5 is turned off, and Q6 is turned on, and the clock detection circuit 3 maintains the L level output (the waveform d in FIG. 3).

It should be noted that, unlike the 24V DC power supply 9 shown in FIG. 1, the 5V power supply in FIG. 2 is also active during sleep.

With the above configuration, even if the sleep mode is entered before the I / O data register is rewritten due to a software defect or the like, the clock detection circuit 3
Monitors the internal clock, and forcibly turns off (cuts off) the gate circuit 5 when the clock stops, thereby preventing problems such as keeping the load operating.

Although the preferred embodiment of the present invention has been described above, various modifications and changes are possible. For example,
In the above description, application to a copying machine has been described. However, the present invention can be applied to any electronic device in which a problem associated with shifting to the sleep mode as described above may occur.
Further, the specific configuration of the clock detection circuit illustrated in FIG. 2 is only an example, and any other circuit configuration having the same function and effect can be used.

[0026]

According to the present invention, even if the CPU enters the sleep mode without disabling the load for some reason, the stop of the clock is detected by the hardware and the predetermined load is forced. By temporarily disabling the operation, it is possible to prevent a problem that occurs with the transition to the sleep mode.

[0027]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration related to a CPU of a copying machine as an electronic apparatus of the present invention.

FIG. 2 is a circuit diagram showing an example of an internal configuration of the clock detection circuit shown in FIG.

3 is a waveform diagram showing signal waveforms at points a to d in the circuit diagram of FIG. 2 when an internal clock of the CPU of FIG. 1 is active.

4 is a waveform chart showing signal waveforms at points a to d in the circuit diagram of FIG. 2 when the internal clock of the CPU of FIG. 1 is stopped.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... frequency division counter, 3 ... clock detection circuit, 4 ... operation part, 5 ... gate circuit, 6 ... driver, 7 ...
Exhaust fan, 8 ... Original lamp, 9 ... DC power supply (24
V) 10 ... clutch, solenoid, 11 ... motor.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Masatoshi Tanabe 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term within Canon Inc. (reference) 5B021 AA01 AA05 MM00 5B062 AA05 DD10 HH01 HH06 5B079 AA04 BA12 BB01 BC01 DD02 DD03 DD17 DD20

Claims (3)

[Claims] 1. An electronic device using a CPU for stopping an internal clock in a sleep mode, comprising: a clock detection circuit for detecting by hardware that the internal clock is stopped in a sleep mode; An electronic device using a CPU, comprising: control means for disabling a predetermined load based on a signal indicating that the clock is stopped. 2. The control unit according to claim 1, wherein when the sleep mode is released and the internal clock of the CPU resumes its operation, the control unit releases the inoperable state of the load.
Electronic equipment using the described CPU. 3. The control means comprises: a driver for driving the load; and a driver for driving the load.
3. An electronic apparatus using a CPU according to claim 1, comprising a gate for selectively supplying an I / O signal from U to said driver.