JPH08205400A - Power supply circuit for electronic apparatus - Google Patents

Power supply circuit for electronic apparatus

Info

Publication number
JPH08205400A
JPH08205400A JP7028669A JP2866995A JPH08205400A JP H08205400 A JPH08205400 A JP H08205400A JP 7028669 A JP7028669 A JP 7028669A JP 2866995 A JP2866995 A JP 2866995A JP H08205400 A JPH08205400 A JP H08205400A
Authority
JP
Japan
Prior art keywords
power supply
thyristor
converter
power
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7028669A
Other languages
Japanese (ja)
Other versions
JP3488757B2 (en
Inventor
Masayuki Fujisawa
政幸 藤澤
Fumio Tokukasa
文男 徳嵩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hioki EE Corp
Original Assignee
Hioki EE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hioki EE Corp filed Critical Hioki EE Corp
Priority to JP02866995A priority Critical patent/JP3488757B2/en
Publication of JPH08205400A publication Critical patent/JPH08205400A/en
Application granted granted Critical
Publication of JP3488757B2 publication Critical patent/JP3488757B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Direct Current Feeding And Distribution (AREA)
  • Control Of Voltage And Current In General (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PURPOSE: To stop the operation of a CPU under a state of auto-power-off and to prevent the consumption of a battery by providing a thyristor which receives a power off signal of level H outputted from the CPU and turns on, and supplying this on-current from the collector of a provided transistor through a resistor. CONSTITUTION: A system-power-voltage forming function is inactivated, by providing a control circuit containing a thyristor Q3 which is turned off by a power off signal outputted by a CPU 4 and a transistor Q1 which supplies on-current to this through a collector resistor R3, and applying the anode side voltage of the thyristor Q3 dropped to level L from level H by a voltage drop generated in the collector resistor R3. Consequently, it becomes possible to obtain a power off state easily and to maintain the state surely, without the need of a power device for a CPU's exclusive use.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は電子機器類の電源供給
回路に係り、更に詳しく言えば、特に電池を電源に用い
た機器において、電力供給を開始してから所定時間経過
すると自動的に電源を断つオートパワーオフ機能を備え
た電源供給回路に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for electronic devices, and more particularly, to a device using a battery as a power source, in which power is automatically supplied when a predetermined time elapses after power supply is started. The present invention relates to a power supply circuit having an automatic power-off function for turning off the power.

【0002】[0002]

【従来例】図2に従来装置の一般的な例を示す。同図に
おいて、電源スイッチSをONに入れると電池1の電圧
はFET2のソース側に加わり、ゲート側には抵抗
R1を介してバイアス電圧が加わるからFET2はON
となる。よって、電池電圧VはDC−DCコンバータ
3の端子Vinと定電圧回路5に加わる。
2. Description of the Related Art FIG. 2 shows a general example of a conventional device. In the figure, when the power switch S is turned on, the voltage V B of the battery 1 is applied to the source side of the FET 2 and the bias voltage is applied to the gate side via the resistor R 1, so that the FET 2 is turned on.
Becomes Therefore, the battery voltage V B is applied to the terminal Vin of the DC-DC converter 3 and the constant voltage circuit 5.

【0003】DC−DCコンバータ3は端子Vinに電
源が供給され、かつ端子OFFがHレベルになっていれ
ば能動状態(Active)となり、電池電圧Vから
一定レベルのシステム電源電圧Vccを形成して端子V
oから出力する。この電圧Vccは装置内の他のユニッ
トに加えられる。また、定電圧回路5にて一定レベルに
された電源電圧+VccはCPU4に加えられ、CPU
4は動作を開始する。
[0003] DC-DC converter 3 has a power supply terminal Vin is supplied, and terminal OFF is active state (Active) next if the H level, to form a certain level of the system power supply voltage Vcc from the battery voltage V B Terminal V
Output from o. This voltage Vcc is applied to other units in the device. Further, the power supply voltage + Vcc, which is set to a constant level by the constant voltage circuit 5, is applied to the CPU 4,
4 starts operation.

【0004】この場合、CPU4の出力ポートOUTは
例えばその内部で接地側に接続され、Lレベルにされて
いるのでトランジスタQ2はOFFになっている。他
方、トランジスタQ1はONになっており、端子OFF
に加わる電圧は例えばDC−DCコンバータ3の内部で
図示しない基準電圧と比較されるようになっている。
In this case, the output port OUT of the CPU 4 is internally connected to the ground side, for example, and is set to the L level, so that the transistor Q2 is turned off. On the other hand, the transistor Q1 is on and the terminal is off.
The voltage applied to is compared with a reference voltage (not shown) inside the DC-DC converter 3, for example.

【0005】この電圧が基準電圧を上回っていれば、D
C−DCコンバータ3はシステム電源電圧を形成するよ
うになっているので、端子OFFに加わる電圧は上記基
準電圧を超えるHレベルとなるようにトランジスタQ1
の動作点が設定されている。
If this voltage exceeds the reference voltage, D
Since the C-DC converter 3 is adapted to form the system power supply voltage, the transistor Q1 is controlled so that the voltage applied to the terminal OFF becomes the H level exceeding the reference voltage.
The operating point of is set.

【0006】ここで、例えば図示しない操作キーにより
オートパワーオフが設定されていると、その情報はCP
U4に入力される。CPU4は定電圧回路5から電源電
圧Vccが供給されてから所定時間例えば5分経過する
と、出力ポートを接地側から所定の電圧路に切り換え接
続し、Hレベルのパワーオフ信号を送出する。
Here, for example, when the auto power off is set by an operation key (not shown), the information is CP
Input to U4. When a predetermined time, for example, 5 minutes has elapsed after the power supply voltage Vcc was supplied from the constant voltage circuit 5, the CPU 4 switches the output port from the ground side to a predetermined voltage path and connects it, and sends out an H level power-off signal.

【0007】これにより、トランジスタQ2はONとな
り、電池電源からトランジスタQ1,Q2を通って接地
側へ比較的大きい電流が流れる。この電流にて抵抗R3
に発生する電圧降下により端子OFFの電圧は急速に低
下する。この場合、端子OFFの電圧が上記基準電圧を
下回るLレベルになると、DC−DCコンバータ3はシ
ステム電源電圧の形成機能を停止させるようになってい
る。したがって、端子Voの出力電圧Vccはゼロとな
り、スイッチSの切り忘れなどによる電池の消耗が軽減
される。
As a result, the transistor Q2 is turned on, and a relatively large current flows from the battery power source to the ground side through the transistors Q1 and Q2. Resistor R3 at this current
Due to the voltage drop that occurs at the terminal, the voltage at the terminal OFF rapidly decreases. In this case, when the voltage at the terminal OFF becomes L level, which is lower than the reference voltage, the DC-DC converter 3 stops the function of forming the system power supply voltage. Therefore, the output voltage Vcc of the terminal Vo becomes zero, and battery consumption due to forgetting to turn off the switch S or the like is reduced.

【0008】[0008]

【発明が解決しようとする課題】上記従来装置は構成が
比較的簡単であるという長所がある。ところで、オート
パワーオフの動作に入ると、DC−DCコンバータ3は
その機能を停止するから、その電力消費はほとんどない
が、CPU4は定電圧回路5から電源供給を受けてHレ
ベルのパワーオフ信号を出し続けるため、ある程度の電
力が消費される。
The above-mentioned conventional device has the advantage that the structure is relatively simple. By the way, when the operation of the auto power off is started, the DC-DC converter 3 stops its function, so that there is almost no power consumption, but the CPU 4 receives the power supply from the constant voltage circuit 5 and the power off signal of H level. Power is consumed to keep the power on.

【0009】あるいは、例えばソフトウェアによって低
消費電力動作モードへ移行し、省電力化することも可能
であるが、いずれにしてもCPU専用の電源が必要であ
り、また、低電力モードとなってもCPUは少なからず
電力を消費するため、好ましくない。
Alternatively, for example, it is possible to shift to a low power consumption operation mode by software to save power, but in any case, a power source dedicated to the CPU is required, and even in the low power mode. The CPU consumes a considerable amount of power, which is not preferable.

【0010】この発明は上記の事情を考慮してなされた
もので、その目的は、オートパワーオフの状態において
はCPUの動作も完全に停止させ、電池の消耗をほとん
どなくすことができるようにした電源供給回路を提供す
ることにある。
The present invention has been made in consideration of the above circumstances, and an object thereof is to completely stop the operation of the CPU in the state of the auto power off so that the consumption of the battery can be almost eliminated. It is to provide a power supply circuit.

【0011】[0011]

【課題を解決するための手段】上記の課題を解決するた
め、この発明においては例えばCPUから発せられるH
レベルのパワーオフ信号を受けてONとなるサイリスタ
を備え、同サイリスタのON電流を従来装置と同様に配
設されたトランジスタQ1のコレクタから抵抗R3を介
して供給されるようにしている。
In order to solve the above-mentioned problems, in the present invention, H issued from, for example, a CPU
A thyristor which is turned on upon receiving a level power-off signal is provided, and the ON current of the thyristor is supplied from the collector of the transistor Q1 arranged similarly to the conventional device through the resistor R3.

【0012】[0012]

【作用】サイリスタはCPUからHレベルのパワーオフ
信号をゲートに受けるとONとなり、そのアノード側は
ON電流にて抵抗R3に発生する電圧降下によりLレベ
ルになる。よってサイリスタのアノード側をDC−DC
コンバータのOFF端子に接続しておけば、同コンバー
タ内のシステム電源電圧形成回路は機能が停止し、その
出力電圧Vccはゼロとなる。
The thyristor is turned on when the gate receives the H-level power-off signal from the CPU, and the anode side thereof becomes the L-level due to the voltage drop generated in the resistor R3 by the ON current. Therefore, the anode side of the thyristor is DC-DC
If it is connected to the OFF terminal of the converter, the system power supply voltage forming circuit in the converter stops functioning and its output voltage Vcc becomes zero.

【0013】この場合、CPUも電源電圧Vccが供給
されなくなって機能を停止しパワーオフ信号は消滅する
が、サイリスタはゲート信号がなくなってもトランジス
タQ1を介して電流が供給されるのでON動作を続け、
確実にパワーオフの状態が維持される。
In this case, the power supply voltage Vcc of the CPU also stops being supplied and the power-off signal disappears, but the thyristor is turned on because the current is supplied through the transistor Q1 even when the gate signal is lost. continue,
The power off state is reliably maintained.

【0014】[0014]

【実施例】この発明の実施例が示されている図1を参照
すると、従来装置のトランジスタQ2がこの発明ではサ
イリスタQ3に置き換えられている。また、CPU4に
はDC−DCコンバータ3から直接電源電圧Vccが供
給されるようになっており、それに伴って従来の定電圧
回路がこの発明では不要のため省かれているが、その他
の構成は従来装置と同様になっている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, which illustrates an embodiment of the present invention, the transistor Q2 of the prior art is replaced by a thyristor Q3 in the present invention. Further, the power supply voltage Vcc is directly supplied to the CPU 4 from the DC-DC converter 3, and accordingly, the conventional constant voltage circuit is omitted in the present invention because it is unnecessary, but other configurations are It is similar to the conventional device.

【0015】さて、電源スイッチSをONに入れ、続い
てオートパワーオフを設定したとする。FET2がON
となり、電池電源VがトランジスタQ1とDC−DC
コンバータ3に加わって両者はそれぞれONになる。D
C−DCコンバータ3は電池電源Vからシステム電源
電圧Vccを形成して出力し、CPU4は電源電圧Vc
cの供給を受けてONとなり定められた動作を行う。
Now, it is assumed that the power switch S is turned on and then auto power off is set. FET2 is ON
And the battery power source V B is connected to the transistor Q1 and DC-DC.
Both are added to the converter 3 and turned on. D
C-DC converter 3 outputs to form a system power supply voltage Vcc from the battery power source V B, CPU 4 is the power supply voltage Vc
Upon receiving the supply of c, it is turned on and the predetermined operation is performed.

【0016】この時点ではCPU4の出力ポートOUT
は例えばその内部で接地側に接続されており、サイリス
タQ3はゲート電流が流れないのでOFFになってい
る。またトランジスタQ1はONになっているが、流れ
る電流が小さいので抵抗R3の電圧降下も少なく、DC
−DCコンバータ3の端子OFFにはコレクタ電圧とほ
ぼ等しいHレベルの電圧が加わっている。
At this time, the output port OUT of the CPU 4
Is internally connected to the ground side, and the thyristor Q3 is turned off because no gate current flows. Although the transistor Q1 is on, the current flowing is small, so the voltage drop across the resistor R3 is small, and the DC
A voltage of H level, which is almost equal to the collector voltage, is applied to the terminal OFF of the DC converter 3.

【0017】ここで所定の時間が経過すると、CPU4
は出力ポートOUTをその内部でHレベルの電圧端子に
切り換え接続する。この電圧はパワーオフ信号として出
力ポートOUTからサイリスタQ3のゲートに加えら
れ、ゲート電流が流れてサイリスタQ3はONとなる。
When a predetermined time has passed, the CPU 4
Connects the output port OUT to the voltage terminal of H level inside thereof. This voltage is applied as a power-off signal to the gate of the thyristor Q3 from the output port OUT, a gate current flows, and the thyristor Q3 is turned on.

【0018】これにより、電池電圧路からトランジスタ
Q1と抵抗R3を経てサイリスタQ3のアノードからカ
ソードへ電流が流れ、抵抗R3に発生する電圧降下のた
め端子OFFに加わる電圧がLレベルに低下する。DC
−DCコンバータ3においては、この端子電圧が図示し
ない基準電圧を下回るとシステム電源電圧の形成機能が
停止させられ、端子Voの出力電圧Vccはゼロに低下
してパワーオフの状態になる。
As a result, a current flows from the battery voltage path through the transistor Q1 and the resistor R3 to the cathode of the thyristor Q3, and the voltage drop across the resistor R3 causes the voltage applied to the terminal OFF to drop to the L level. DC
In the -DC converter 3, when the terminal voltage becomes lower than the reference voltage (not shown), the function of forming the system power supply voltage is stopped, and the output voltage Vcc at the terminal Vo drops to zero and the power is turned off.

【0019】端子Voの出力がゼロになると、CPU4
は電源電圧の供給が断たれて動作を停止し、出力ポート
OUTから送出していたHレベルのパワーオフ信号もゼ
ロとなる。この場合、サイリスタQ3はいったんONに
なると、CPU4からのパワーオフ信号が消滅してもO
N動作を継続するから、電源スイッチSがON側に入っ
ていてもパワーオフの状態は確実に維持される。
When the output of the terminal Vo becomes zero, the CPU 4
The power supply voltage is cut off to stop the operation, and the H-level power-off signal sent from the output port OUT becomes zero. In this case, once the thyristor Q3 is turned on, the power is turned off even if the power off signal from the CPU 4 disappears.
Since the N operation is continued, the power-off state is reliably maintained even if the power switch S is on the ON side.

【0020】[0020]

【効果】以上、説明したようにこの発明によると、CP
U専用の電源装置などを特に必要とすることなく、容易
にパワーオフ状態が得られ、かつ、その状態を確実に維
持することができる。
As described above, according to the present invention, the CP
The power-off state can be easily obtained and the state can be reliably maintained without requiring a power supply device dedicated to U or the like.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明が適用された電源供給回路の電気的構
成を示すブロック線図。
FIG. 1 is a block diagram showing an electrical configuration of a power supply circuit to which the present invention is applied.

【図2】従来装置の電気的構成を示すブロック線図。FIG. 2 is a block diagram showing an electrical configuration of a conventional device.

【符号の説明】[Explanation of symbols]

1 電池 3 DC−DCコンバータ 4 CPU Q1 トランジスタ Q3 サイリスタ R2 ベース抵抗 R3 コレクタ抵抗 R4 分圧抵抗 R5 分圧抵抗 S 電源スイッチ V 電池電源 Vcc システム電源電圧1 battery 3 DC-DC converter 4 CPU Q1 transistor Q3 thyristor R2 base resistor R3 collector resistor R4 of voltage dividing resistors R5 divider resistor S power switch V B cell power supply Vcc system power supply voltage

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 電池電源から負荷へ電力を供給するとと
もに、所定時間経過後は上記負荷への電力供給を自動的
に停止する電子機器類の電源供給回路において、電源ス
イッチのON操作により上記電池電源を受けて作動し、
該電池電源から一定レベルのシステム電源電圧を形成し
て上記負荷へ供給するDC−DCコンバータと、上記電
池電源を受けて作動し、上記DC−DCコンバータへH
レベルの電圧信号を与えて同DC−DCコンバータのシ
ステム電源電圧形成機能を能動化させ、もしくはLレベ
ルの電圧信号を与えてそのシステム電源電圧形成機能を
非能動化させる半導体素子を含む制御回路と、上記シス
テム電源電圧を受けて作動し、所定時間に達する以前は
上記制御回路へLレベルの電圧信号を発して同制御回路
から上記DC−DCコンバータ(端子OFF)へHレベ
ルの電圧信号を送出させるとともに、所定時間に達した
時点で上記制御回路へHレベルの電圧信号を発し、同制
御回路から上記DC−DCコンバータ(端子OFF)へ
Lレベルの電圧信号を送出させるCPUとを備えている
ことを特徴とする電子機器類の電源供給回路。
1. In a power supply circuit of an electronic device, which supplies power from a battery power source to a load and automatically stops power supply to the load after a lapse of a predetermined time, the battery is turned on by operating a power switch. It operates by receiving power,
A DC-DC converter that forms a certain level of system power supply voltage from the battery power supply and supplies it to the load, and a DC-DC converter that operates by receiving the battery power and outputs H to the DC-DC converter.
A control circuit including a semiconductor element for applying a level voltage signal to activate the system power supply voltage forming function of the DC-DC converter, or for supplying an L level voltage signal to deactivate the system power supply voltage forming function. , Operates by receiving the system power supply voltage, and outputs an L level voltage signal to the control circuit before the predetermined time is reached, and sends an H level voltage signal from the control circuit to the DC-DC converter (terminal OFF). And a CPU for issuing an H level voltage signal to the control circuit when a predetermined time is reached and sending an L level voltage signal from the control circuit to the DC-DC converter (terminal OFF). A power supply circuit for electronic devices characterized by the above.
【請求項2】 上記制御回路はトランジスタとサイリス
タとを含み、該トランジスタのエミッタは上記電池電源
路に接続され、そのベースはベース抵抗を経て電源スイ
ッチのON操作により接地されるとともに、コレクタは
コレクタ抵抗を介して上記サイリスタのアノードと上記
DC−DCコンバータ(端子OFF)に共通接続されて
なり、上記サイリスタのカソードは接地され、そのゲー
トは分圧抵抗を経て上記CPUの電圧信号出力ポート
(OUT)に接続された請求項1に記載の電子機器類の
電源供給回路。
2. The control circuit includes a transistor and a thyristor, the emitter of the transistor is connected to the battery power path, the base is grounded through a base resistance by turning on the power switch, and the collector is the collector. The anode of the thyristor is commonly connected to the DC-DC converter (terminal OFF) via a resistor, the cathode of the thyristor is grounded, and the gate of the thyristor is connected to the voltage signal output port (OUT) of the CPU through a voltage dividing resistor. ) Is connected to the power supply circuit for electronic devices according to claim 1.
【請求項3】 上記制御回路において、上記サイリスタ
のゲートに上記CPUの出力ポート(OUT)からLレ
ベルの電圧信号が加わった場合は同サイリスタは非動作
状態(オフ)となり、そのアノードと上記DC−DCコ
ンバータ(端子OFF)との共通接続箇所は上記トラン
ジスタのコレクタ電圧とほぼ等しいHレベルの電圧とな
る請求項1に記載の電子機器類の電源供給回路。
3. In the control circuit, when an L-level voltage signal is applied to the gate of the thyristor from the output port (OUT) of the CPU, the thyristor becomes inactive (OFF), its anode and the DC The power supply circuit for electronic devices according to claim 1, wherein a common connection point with the DC converter (terminal OFF) has an H level voltage substantially equal to the collector voltage of the transistor.
【請求項4】 上記制御回路において、上記サイリスタ
のゲートに上記CPUの出力ポート(OUT)からHレ
ベルの電圧信号が加わった場合は同サイリスタが動作状
態(オン)となり、そのアノードと上記DC−DCコン
バータ(端子OFF)との共通接続箇所は、同サイリス
タに流れるオン電流にて上記コレクタ抵抗に発生する電
圧降下によりLレベルの電圧となる請求項1に記載の電
子機器類の電源供給回路。
4. In the control circuit, when an H-level voltage signal is applied to the gate of the thyristor from the output port (OUT) of the CPU, the thyristor is in an operating state (ON), its anode and the DC- The power supply circuit for electronic devices according to claim 1, wherein a common connection point with the DC converter (terminal OFF) becomes an L level voltage due to a voltage drop generated in the collector resistance due to an ON current flowing in the thyristor.
JP02866995A 1995-01-25 1995-01-25 Power supply circuit for electronic equipment Expired - Fee Related JP3488757B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003067060A (en) * 2001-08-27 2003-03-07 Mitsumi Electric Co Ltd Power control circuit and electronic device
US6900788B2 (en) 1998-02-09 2005-05-31 Seiko Epson Corporation Electrooptical apparatus and driving method therefor, liquid crystal display apparatus and driving method therefor, electrooptical apparatus and driving circuit therefor, and electronic equipment
JP2008236900A (en) * 2007-03-20 2008-10-02 Toshiba Corp Electrical device
JP2023080723A (en) * 2021-11-30 2023-06-09 株式会社ミヤワキ Power supply control circuit
JP2023080724A (en) * 2021-11-30 2023-06-09 株式会社ミヤワキ Power supply control circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6900788B2 (en) 1998-02-09 2005-05-31 Seiko Epson Corporation Electrooptical apparatus and driving method therefor, liquid crystal display apparatus and driving method therefor, electrooptical apparatus and driving circuit therefor, and electronic equipment
JP2003067060A (en) * 2001-08-27 2003-03-07 Mitsumi Electric Co Ltd Power control circuit and electronic device
JP2008236900A (en) * 2007-03-20 2008-10-02 Toshiba Corp Electrical device
JP2023080723A (en) * 2021-11-30 2023-06-09 株式会社ミヤワキ Power supply control circuit
JP2023080724A (en) * 2021-11-30 2023-06-09 株式会社ミヤワキ Power supply control circuit

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