JP2000124460A - Characteristic improvement method in manufacture process of non-single crystalline semiconductor thin film element - Google Patents

Characteristic improvement method in manufacture process of non-single crystalline semiconductor thin film element

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Publication number
JP2000124460A
JP2000124460A JP10294111A JP29411198A JP2000124460A JP 2000124460 A JP2000124460 A JP 2000124460A JP 10294111 A JP10294111 A JP 10294111A JP 29411198 A JP29411198 A JP 29411198A JP 2000124460 A JP2000124460 A JP 2000124460A
Authority
JP
Japan
Prior art keywords
film
thin film
water
semiconductor thin
deposited
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10294111A
Other languages
Japanese (ja)
Inventor
Kazumichi Omura
八通 大村
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Individual
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Individual
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Filing date
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Priority to JP10294111A priority Critical patent/JP2000124460A/en
Publication of JP2000124460A publication Critical patent/JP2000124460A/en
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Abstract

PROBLEM TO BE SOLVED: To compensate for combination defect of a non-single crystalline semiconductor thin film and restrain characteristic deterioration of the element, by a method which is easy and excellent in cost performance in a manufacturing process of an element (such as a thin film field effect transistor, an optical conduction element and a photoelectromotive element) based on a structure wherein a non-single crystalline semiconductor thin film is deposited on a substrate. SOLUTION: After a gate electrode 28 is formed by vacuum deposition or sputtering on a supporting substrate 26, an i-type amorphous silicon film 30 is deposited by thermal CVD of 650 deg.C of silane and in this stage, the structure body is immersed in high pressure water of 110 deg.C for 15 hours. Then, an insulation film 32, a source metallic film 34 and a drain metallic film 36 are deposited by vacuum deposition or sputtering and a source and a drain are formed by sputtering.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は、薄膜電界効果ト
ランジスタ・光伝導素子・光起電力素子などの半導体薄
膜素子の製造プロセスに係わり、さらに詳しくは、基板
の上に堆積した非単結晶半導体薄膜の結合欠陥に起因す
る特性劣化を改善する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor thin film device such as a thin film field effect transistor, a photoconductive device, and a photovoltaic device, and more particularly, to a non-single-crystal semiconductor thin film deposited on a substrate. A method for improving the characteristic deterioration caused by the bonding defect of the above.

【0002】[0002]

【従来の技術】薄膜電界効果トランジスタ(以下、TF
Tと略す。)・光伝導素子・光起電力素子などの半導体
薄膜素子は典型的には、ガラス・金属・単結晶半導体な
どの基板上に非単結晶半導体薄膜を堆積した構造を主体
としている。この非単結晶半導体薄膜は、プラズマCV
D・熱CVD・スパッタ法などで作成される。この薄膜
の材料としては、シリコン膜が代表的であるが、目的に
応じてゲルマニウム膜・窒化シリコン膜・酸化シリコン
膜・シリコンオキシナイトラド膜・炭化シリコン膜・シ
リコンゲルマニウム合金膜なども用いられる。TFT・
光伝導素子・光起電力素子などの素子については多くの
文献に詳しく解説されているので、以下では、この発明
に係わる部分のみを抽出して説明する。
2. Description of the Related Art A thin film field effect transistor (hereinafter referred to as TF)
Abbreviated as T. 2.) Semiconductor thin-film devices such as photoconductive devices and photovoltaic devices typically have a structure in which a non-single-crystal semiconductor thin film is deposited on a substrate such as glass, metal, or single-crystal semiconductor. This non-single-crystal semiconductor thin film has a plasma CV
D, thermal CVD, sputtering, etc. As a material of the thin film, a silicon film is typical, but a germanium film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, a silicon germanium alloy film, etc. may be used according to the purpose. TFT ・
Elements such as a photoconductive element and a photovoltaic element have been described in detail in many documents, and therefore, only the portions related to the present invention will be described below.

【0003】[0003]

【発明が解決しようとする課題】プラズマCVD・熱C
VD・スパッタ法などで基板上に堆積される非単結晶半
導体薄膜の内部および界面には、シリコン原子の結合欠
陥が多く存在する。(プラズマCVD・熱CVD・スパ
ッタ法の順で欠陥が多い。)シリコン原子の結合欠陥は
意図しないギャップ内準位を生じさせる。このギャップ
内準位は、電荷の発生・キャリア再結合に密接に関係し
ており、TFT・光伝導素子・光起電力素子などの素子
特性を大きく左右する最大の因子である。また結合欠陥
が多いと、構造上の歪みを生じるという問題を引き起こ
す他、欠陥部分が非常に活性であるため不純物を吸着し
やすく、これが欠陥準位の発生原因となる。これらの問
題点は、例えばTFTにおいてオフ時のリーク電流によ
るオン/オフ比の低下を招き、光起電力素子においては
発電効率の低下を招く。
SUMMARY OF THE INVENTION Plasma CVD / Heat C
Many non-single-crystal semiconductor thin films deposited on a substrate by a VD / sputtering method or the like have a large number of silicon atom bond defects inside and at the interface. (There are many defects in the order of plasma CVD / thermal CVD / sputtering.) Bonding defects of silicon atoms cause unintended levels in the gap. The in-gap level is closely related to charge generation and carrier recombination, and is the largest factor that greatly affects device characteristics such as a TFT, a photoconductive device, and a photovoltaic device. Further, if there are many bonding defects, a problem of causing structural distortion is caused. In addition, since the defective portion is very active, impurities are easily adsorbed, which causes a defect level. These problems cause, for example, a decrease in the on / off ratio due to a leak current when the TFT is off, and a decrease in the power generation efficiency in the photovoltaic element.

【0004】上述した非単結晶半導体薄膜内の結合欠陥
に起因する素子特性の劣化を改善するためには、膜内の
結合欠陥を補償する必要がある。この目的のため、従
来、以下に詳述する水素プラズマ法および水素イオン注
入法が提案されている。
[0004] In order to improve the deterioration of the device characteristics due to the above-mentioned coupling defect in the non-single-crystal semiconductor thin film, it is necessary to compensate for the coupling defect in the film. For this purpose, conventionally, a hydrogen plasma method and a hydrogen ion implantation method described in detail below have been proposed.

【0005】前者の水素プラズマ法は、非単結晶半導体
薄膜をチャンパー内の水素あるいは重水素のDCプラズ
マに暴露する方法である。(詳しくは、”POST-HYDROGE
NATION OF CVD DEPOSITED a-Si FILMS” N. Sol et al.
J. Non-Crystal. Solids Vol. 35 & 36 p291, 1980 参
照。)しかし、この方法では前記チャンバーの器壁に付
着した汚染物質や器壁材料がスパッタされて非単結晶半
導体薄膜に付着し、この付着物が非単結晶半導体薄膜の
内部または界面に欠陥準位を形成するという問題点があ
る。また、プラズマを定義するパラメータが多すぎるた
め、この方法で適切に欠陥を補償することは容易ではな
い。
The former hydrogen plasma method is a method in which a non-single-crystal semiconductor thin film is exposed to DC plasma of hydrogen or deuterium in a champer. (For details, see “POST-HYDROGE
NATION OF CVD DEPOSITED a-Si FILMS ”N. Sol et al.
See J. Non-Crystal. Solids Vol. 35 & 36 p291, 1980. However, in this method, the contaminants and the material of the vessel wall adhering to the chamber wall of the chamber are sputtered and adhere to the non-single-crystal semiconductor thin film, and the adhered substance becomes a defect level inside or at the interface of the non-single-crystal semiconductor thin film. Is formed. Also, it is not easy to properly compensate for defects by this method because there are too many parameters defining the plasma.

【0006】後者の水素イオン注入法は、水素イオンを
高電圧で加速して非単結晶半導体薄膜にたたき込む方法
である。(詳しくは、”HYDOROGEN IMPLANTATION INTO
CVDAMORPHOUS SILICON ” T. Suzuki et al. J. J. App
l. Phys. Vol. 19 Supplement p91, 1980 参照。)こ
の方法では水素イオン注入の際に新たな結合欠陥が生じ
るため、この結合欠陥を熱処理で回復させる必要があ
る。しかし、このような水素イオン注入後の熱処理は、
結合欠陥を補償していた水素イオンが分離・逸脱しない
温度にて行う必要があるため、結合欠陥を完全に回復さ
せることは非常に難しい。
The latter hydrogen ion implantation method is a method in which hydrogen ions are accelerated at a high voltage to strike a non-single-crystal semiconductor thin film. (See “HYDOROGEN IMPLANTATION INTO
CVDAMORPHOUS SILICON ”T. Suzuki et al. JJ App
l See Phys. Vol. 19 Supplement p91, 1980. In this method, new bonding defects are generated at the time of hydrogen ion implantation, and it is necessary to recover the bonding defects by heat treatment. However, such heat treatment after hydrogen ion implantation
Since it is necessary to perform the bonding at a temperature at which hydrogen ions that compensated for the bonding defect do not separate or deviate, it is very difficult to completely recover the bonding defect.

【0007】この発明は上述した従来の課題に鑑みてな
されたもので、非単結晶半導体薄膜の内部や界面に不純
物を取り込んだり、結合に欠陥を発生させたりすること
がなく、簡易でかつコストパフォーマンスに優れた方法
で、非単結晶半導体薄膜の内部や界面に生じた結合欠陥
を補償することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and does not take impurities into the inside or the interface of the non-single-crystal semiconductor thin film and does not cause a defect in bonding. It is an object of the present invention to compensate for a bonding defect generated inside or at an interface of a non-single-crystal semiconductor thin film by a method excellent in performance.

【0008】[0008]

【課題を解決するための手段】前記課題を解決するため
のこの発明の請求項1に記載の特性改善方法は、基板上
に非単結晶半導体薄膜を堆積した構造を主体とする素子
の製造プロセスにおいて、非単結晶半導体薄膜を堆積し
た基板を110℃以上の水中に1時間以上保持すること
を特徴とする。水はわずかであるが、電離しており、温
度が上昇するにつれてイオン濃度は急激に増加する。こ
の水素イオンは非単結晶半導体薄膜に浸透・拡散し、シ
リコン原子の欠陥結合に作用してこれを補償する。ま
た、水素イオン濃度および水素イオンの薄膜内拡散速度
はともに、高温で増加するのでこの効果は高温で処理す
るほど効果的である。
According to a first aspect of the present invention, there is provided a method of manufacturing a device having a structure in which a non-single-crystal semiconductor thin film is deposited on a substrate. Wherein the substrate on which the non-single-crystal semiconductor thin film is deposited is kept in water at 110 ° C. or higher for 1 hour or more. Although the water is slight, it is ionized, and the ion concentration increases rapidly with increasing temperature. The hydrogen ions permeate and diffuse into the non-single-crystal semiconductor thin film, and act on defect bonds of silicon atoms to compensate for the defects. Further, since both the hydrogen ion concentration and the diffusion rate of hydrogen ions in the thin film increase at a high temperature, this effect is more effective as the treatment is performed at a higher temperature.

【0009】この発明の請求項2に記載の特性改善方法
は、請求項1に記載の水中を、重水中としたことを特徴
とする。重水も軽水と同様にわずかに電離しており、軽
水の水素イオンと同様に欠陥結合を補償する。また、処
理温度が高いほど効果的である。
A characteristic improving method according to a second aspect of the present invention is characterized in that the water according to the first aspect is heavy water. Heavy water is also slightly ionized, similar to light water, and compensates for defect bonding, similar to light water hydrogen ions. The higher the processing temperature, the more effective.

【0010】この発明の請求項3に記載の特性改善方法
は、請求項1に記載の水中を、軽水と重水の混合水中と
したことを特徴とする。処理しようとする非単結晶半導
体薄膜の材料や膜厚などによっては、軽水と重水の混合
水を用いることが有効である。
According to a third aspect of the present invention, there is provided a method for improving characteristics, wherein the water according to the first aspect is a mixture of light water and heavy water. Depending on the material and thickness of the non-single-crystal semiconductor thin film to be treated, it is effective to use mixed water of light water and heavy water.

【0011】請求項1ないし請求項3に記載の特性改善
方法は、シリコン膜・ゲルマニウム膜・窒化シリコン膜
・酸化シリコン膜・シリコンオキシナイトラド膜・炭化
シリコン膜・シリコンゲルマニウム合金膜のいずれかの
非単結晶半導体薄膜に効果的に適用できる。
According to a first aspect of the present invention, there is provided a method for improving characteristics of any one of a silicon film, a germanium film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, a silicon carbide film, and a silicon germanium alloy film. It can be effectively applied to a non-single-crystal semiconductor thin film.

【0012】この発明の方法では、軽水または重水、あ
るいはこれらの混合水中の処理温度および処理時間を、
110℃および1時間と設定している。この条件は、1
10℃以下、あるいは110℃で1時間以下の水煮処理
では、所期の効果が全く見られない事実に基づいて設定
された。このような110℃程度の温度では、水のイオ
ン化の程度がきわめて小さく、結合欠陥を補償する水素
量が少ないためと考えられる。
In the method of the present invention, the treatment temperature and treatment time in light water or heavy water, or a mixed water thereof,
110 ° C. and 1 hour are set. This condition is 1
In water treatment at 10 ° C. or less, or at 110 ° C. for 1 hour or less, the temperature was set based on the fact that the desired effect was not seen at all. It is considered that at such a temperature of about 110 ° C., the degree of ionization of water is extremely small, and the amount of hydrogen for compensating for bond defects is small.

【0013】[0013]

【発明の実施の形態】この発明の方法では、薄膜電界効
果トランジスタ・光伝導素子・光起電力素子などの半導
体薄膜素子の製造プロセスの適当な段階において、基板
の上に堆積した非単結晶半導体薄膜の結合欠陥に起因す
る特性劣化を改善するため、非単結晶半導体薄膜を堆積
した基板を水煮処理して、結合欠陥の補償を行う。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a method of the present invention, a non-single-crystal semiconductor deposited on a substrate at an appropriate stage of a manufacturing process of a semiconductor thin film device such as a thin film field effect transistor, a photoconductive device, and a photovoltaic device. In order to improve the characteristic deterioration due to the bonding defect of the thin film, the substrate on which the non-single-crystal semiconductor thin film is deposited is subjected to a boiling treatment to compensate for the bonding defect.

【0014】前記水煮処理は、例えば図4に概略を示す
ような構造の水煮装置10を用いて実施する。この装置
10は、高温高圧に耐えうるステンレス鋼容器12の上
部に圧力計14、温度計16、高温高圧水を攪拌するた
めのプロペラ18、および、試料を装着・保持するため
の金具20が取り付けられている。容器12の側面を囲
う外部ヒータ22および温度制御装置24にて、容器1
2内の高圧水の温度が制御される。
The boiling process is performed using a boiling device 10 having a structure as schematically shown in FIG. 4, for example. In this apparatus 10, a pressure gauge 14, a thermometer 16, a propeller 18 for stirring high-temperature and high-pressure water, and a metal fitting 20 for mounting and holding a sample are mounted on a stainless steel container 12 capable of withstanding high temperature and high pressure. Have been. The external heater 22 and the temperature control device 24 surrounding the side of the container 12
The temperature of the high-pressure water in 2 is controlled.

【0015】[実施例1]非単結晶半導体薄膜素子とし
てのボトムゲート型TETの構造例を図1に示してい
る。支持基板26の上に、真空蒸着あるいはスパッタ法
によりゲート電極28を形成した後、シランの650℃
の熱CVDによりi型アモルファスシリコン膜30を堆
積する。この段階でこの構造体を図4の水煮装置10に
入れて温度を110℃に保ち15時間の水煮処理を行
う。その後、この構造体に絶縁膜32、ソース金属膜3
4およびドレイン金属膜36を真空蒸着あるいはスパッ
タ法により堆積し、パターニングによってソース、ドレ
インを形成する。なお、図1では、オーム性接触のため
のn+型アモルファスシリコン膜や、各種エッチングに
必要な絶縁膜については省略してある。
Embodiment 1 FIG. 1 shows a structural example of a bottom gate type TET as a non-single-crystal semiconductor thin film element. After forming the gate electrode 28 on the support substrate 26 by vacuum evaporation or sputtering, 650 ° C.
An i-type amorphous silicon film 30 is deposited by thermal CVD. At this stage, the structure is put into the water boiling apparatus 10 shown in FIG. 4, and the temperature is kept at 110 ° C., and the water is boiled for 15 hours. Then, the insulating film 32 and the source metal film 3
4 and a drain metal film 36 are deposited by vacuum evaporation or sputtering, and a source and a drain are formed by patterning. In FIG. 1, an n + type amorphous silicon film for ohmic contact and an insulating film necessary for various etchings are omitted.

【0016】前記要領で作成したTFTの性能評価のた
め、上述した110℃で15時間の水煮処理を含むプロ
セスにて作成したTFTと、181℃(10気圧に相
当)で2時間の水煮処理を含むプロセスにて作成したT
FTと、水煮処理を含まないプロセスにて作成したT
FTのそれぞれのゲート電圧/ドレイン電流特性を低
電圧駆動(10V)で比較試験した(いずれもチャンネ
ル寸法比はW/L=15である)。その結果を図5に示
す。図中の一点鎖線はTFTの特性、実線はTFT
の特性、点線はTFTの特性をそれぞれ示している。
水煮処理を行ったTFTとTFTは、同処理を行わ
なかったTFTに比べて、リーク電流が低減されるこ
とがわかる。とくに、TFTより高温の水煮処理を行
ったTFTの方がリーク電流の減少が著しいことがわ
かる。
In order to evaluate the performance of the TFT prepared as described above, the TFT prepared by the above-described process including the water boiling treatment at 110 ° C. for 15 hours was combined with the TFT prepared at 181 ° C. (corresponding to 10 atm) for 2 hours. T created in the process including processing
FT and T created by a process that does not include boiled water
The gate voltage / drain current characteristics of each of the FTs were compared and tested with low-voltage driving (10 V) (in each case, the channel size ratio was W / L = 15). The result is shown in FIG. The dashed line in the figure indicates the characteristics of the TFT, and the solid line indicates the TFT.
And the dotted line show the characteristics of the TFT, respectively.
It can be seen that the leakage current of the TFT subjected to the water boiling treatment and the TFT is reduced as compared with the TFT not subjected to the treatment. In particular, it can be seen that the TFT subjected to the high-temperature boiled treatment has a more remarkable decrease in leak current than the TFT.

【0017】なお、図2にはゲート電極を素子の頂上に
堆積したトップゲート型TFTの概略的な側面断面図を
示している。このタイプのTFTの製造プロセスにおい
ても、この発明を適用すれば、前記と同様な効果が得ら
れる。
FIG. 2 is a schematic side sectional view of a top gate type TFT in which a gate electrode is deposited on the top of the device. If the present invention is applied to the manufacturing process of this type of TFT, the same effects as described above can be obtained.

【0018】[実施例2]非単結晶半導体薄膜素子とし
ての光起電力素子の構造例を図3に示している。透明伝
導膜ITO層38を上面に有する支持透明ガラス基板4
0の上に、p+型アモルファスシリコン膜42、i型ア
モルファスシリコン膜44、n型アモルファスシリコン
膜46を下から順に熱CVDによって堆積する。この段
階でこの構造体を図4の水煮装置10に入れて温度を1
50℃に保ち5時間の水煮処理を行う。その後、この構
造体の頂上にアルミニウム電極48(n側)を形成す
る。
Embodiment 2 FIG. 3 shows a structural example of a photovoltaic element as a non-single-crystal semiconductor thin film element. Supporting transparent glass substrate 4 having a transparent conductive film ITO layer 38 on the upper surface
On p. 0, ap + type amorphous silicon film 42, an i type amorphous silicon film 44, and an n type amorphous silicon film 46 are sequentially deposited from the bottom by thermal CVD. At this stage, the structure is put into the water boiling apparatus 10 shown in FIG.
The mixture is kept at 50 ° C. and boiled for 5 hours. Thereafter, an aluminum electrode 48 (n side) is formed on the top of the structure.

【0019】前記要領で作成した光起電力素子の性能評
価のため、発電効率を調べた。その結果、AM1.5,
100mW/cm2 の疑似太陽光照射下で最大出力7m
W/cm2 の電力が取り出せた。また、水煮処理を18
1℃(10気圧)で2時間行い作成した素子も、同じく
7mW/cm2 の出力を得る。水煮処理を行わない素子
では最大出力が5mW/cm2 であるため、上述したい
ずれの条件下でも、発電効率が4割改善される。
To evaluate the performance of the photovoltaic element prepared as described above, the power generation efficiency was examined. As a result, AM1.5,
Maximum output 7m in artificial sunlight irradiation of a 100 mW / cm 2
Power of W / cm 2 was obtained. In addition, 18
An element produced at 1 ° C. (10 atm) for 2 hours also obtains an output of 7 mW / cm 2 . Since the maximum output is 5 mW / cm 2 in the element not subjected to the water boiling treatment, the power generation efficiency is improved by 40% under any of the above-mentioned conditions.

【0020】[実施例3]実施例1で説明したTFTの
作成プロセスにおける水煮処理を、重水または軽水と重
水各50%の混合水を用いて行う。これらの処理はとも
に、120℃(2気圧)で20時間行う。
[Embodiment 3] The water boiling process in the process of manufacturing the TFT described in Embodiment 1 is performed using heavy water or a mixed water of 50% each of light water and heavy water. Both of these treatments are performed at 120 ° C. (2 atm) for 20 hours.

【0021】前記要領で作成したTFTの性能評価のた
め、重水を用いた水煮処理を含むプロセスにて作成した
TFTと、水と重水の混合水を用いた水煮処理を含む
プロセスにて作成したTFTと、水煮処理を含まない
プロセスにて作成したTFTのそれぞれのゲート電圧
/ドレイン電流特性を低電圧駆動(10V)で比較試験
した。その結果を図6に示す。図中の一点鎖線はTFT
の特性、実線はTFTの特性、点線はTFTの特
性をそれぞれ示している。水煮処理を行ったTFTと
TFTは、同処理を行わなかったTFTに比べて、
リーク電流が低減されることがわかる。また、重水を用
いた水煮処理を行ったTFTに比べて、軽水と重水の
混合水を用いた水煮処理を行ったTFTの方がリーク
電流の減少が著しいことがわかる。これらの結果から、
目的に応じて、重水または軽水と重水の混合水を用いる
ことも有効である。
In order to evaluate the performance of the TFT prepared as described above, a TFT prepared by a process including a boiling process using heavy water and a TFT prepared by a process including a boiling process using a mixed water of heavy water. The gate voltage / drain current characteristics of the TFT thus fabricated and a TFT fabricated by a process not including the water-boiling treatment were compared by low-voltage driving (10 V). FIG. 6 shows the result. The dashed line in the figure is the TFT
, The solid line indicates the TFT characteristics, and the dotted line indicates the TFT characteristics. The TFT subjected to the water-boiled treatment and the TFT are compared with the TFT not subjected to the treatment.
It can be seen that the leakage current is reduced. In addition, it can be seen that the leakage current is significantly reduced in the TFT subjected to the water boiling treatment using the mixed water of the light water and the heavy water as compared with the TFT subjected to the water boiling treatment using the heavy water. From these results,
Depending on the purpose, it is also effective to use heavy water or a mixture of light water and heavy water.

【0022】[実施例4]実施例2で説明した光起電力
素子のi型アモルファスシリコン膜44を、スパッタ法
にて堆積する。また、実施例2の水煮処理を、150℃
の重水を用いて5時間行う。
Embodiment 4 The i-type amorphous silicon film 44 of the photovoltaic element described in Embodiment 2 is deposited by sputtering. In addition, the water boiling treatment of Example 2 was performed at 150 ° C.
5 hours using heavy water.

【0023】前記要領で作成した光起電力素子の性能評
価のため、実施例2と同様に発電効率を調べた。実施例
2と同様の疑似太陽光下での光電出力は、処理の有・無
の場合でそれぞれ5mW/cm2 および3mW/cm2
である。よって、発電効率が7割弱改善される。
In order to evaluate the performance of the photovoltaic element prepared as described above, the power generation efficiency was examined in the same manner as in Example 2. Photoelectric output under the same solar simulator as in Example 2, respectively in the case of organic-free processing 5 mW / cm 2 and 3 mW / cm 2
It is. Therefore, the power generation efficiency is improved by less than 70%.

【0024】[補足説明]図4の水煮装置10での処理
にあたっては、攪拌用プロペラ18で高温水を良く攪拌
し、試料温度を高く保つ必要がある。水煮装置10の容
器12にリーク口を設けて、そのリーク口から蒸気が噴
出するように構成しておけば、高圧水の内部に泡が発生
し攪拌に寄与する。
[Supplementary Explanation] In the treatment in the water boiling apparatus 10 shown in FIG. 4, it is necessary to stir the high-temperature water with the stirring propeller 18 to keep the sample temperature high. If a leak port is provided in the container 12 of the water boiler 10 and steam is ejected from the leak port, bubbles are generated inside the high-pressure water and contribute to stirring.

【0025】図1に例示したTFTや、図3に例示した
光起電力素子の製造プロセスにおいて、この発明の方法
を適用する場合、非単結晶半導体薄膜の表面に電極を形
成する前の段階で水煮処理を行うことが望ましい。電極
の形成後に水煮処理を行うと、その電極によって水素あ
るいは重水素の供給が妨げられ、さらにその電極が損傷
を受ける。なお、この発明の水煮処理の後工程で電極を
形成する場合、この工程で400℃もの高温を伴わぬ限
り、この発明による特性改善効果は損なわれない。
When the method of the present invention is applied to the manufacturing process of the TFT illustrated in FIG. 1 and the photovoltaic device illustrated in FIG. 3, before the electrodes are formed on the surface of the non-single-crystal semiconductor thin film. It is desirable to perform boiling treatment. If the boil treatment is performed after the formation of the electrode, the supply of hydrogen or deuterium is prevented by the electrode, and the electrode is further damaged. When an electrode is formed in a step after the water boiling treatment of the present invention, the characteristic improving effect of the present invention is not impaired unless a high temperature as high as 400 ° C. is involved in this step.

【0026】650℃以上の熱CVDあるいは基板を6
50℃以上に保ったプラズマCVDやスパッタ法におい
ては、生成される非単結晶半導体薄膜がアモルファス状
ではなく微細結晶が多数発生している場合がある。この
ような場合では微細結晶の表面や界面に、アモルファス
非単結晶半導体薄膜のギャップ内準位に相当する表面準
位や界面準位が多数生じている。この発明の方法は、こ
のような場合でも適用できることは勿論である。微細結
晶の粒度や濃度などでこれら準位の濃度が決まり、従っ
てこの発明を適用した場合の効果が異なるのは言うまで
もない。
Thermal CVD at 650.degree.
In a plasma CVD or sputtering method kept at 50 ° C. or higher, a non-single-crystal semiconductor thin film may not be amorphous but may have many fine crystals. In such a case, many surface levels and interface levels corresponding to the levels in the gap of the amorphous non-single-crystal semiconductor thin film are generated on the surface and the interface of the fine crystal. The method of the present invention can be applied to such a case. It goes without saying that the concentration of these levels is determined by the particle size and concentration of the fine crystals, and therefore the effect when the present invention is applied is different.

【0027】[0027]

【発明の効果】以上説明したように、この発明の特性改
善方法は、非単結晶半導体薄膜を堆積した基板を高温の
水中に一定時間以上浸漬するという、きわめて簡単な方
法であり、この方法により非単結晶半導体薄膜の内部や
界面に電離イオンを浸透・拡散させて、結合欠陥を効果
的に補償することができる。その結果、TFTのオフ時
のリーク電流を低減し、太陽電池の発電効率を向上させ
ることができるなど、この種の素子の特性向上に大いに
寄与する。
As described above, the method for improving characteristics according to the present invention is a very simple method of immersing a substrate on which a non-single-crystal semiconductor thin film is deposited in high-temperature water for a certain period of time or more. Bonding defects can be effectively compensated by penetrating and diffusing ionized ions into the inside and the interface of the non-single-crystal semiconductor thin film. As a result, the leakage current when the TFT is off can be reduced, and the power generation efficiency of the solar cell can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】この発明の実施例のボトムゲート型薄膜電界効
果トランジスタを示す概略的な側面断面図である。
FIG. 1 is a schematic side sectional view showing a bottom gate type thin film field effect transistor according to an embodiment of the present invention.

【図2】この発明の実施例のトップゲート型薄膜電界効
果トランジスタを示す概略的な側面断面図である。
FIG. 2 is a schematic side sectional view showing a top gate thin film field effect transistor according to an embodiment of the present invention.

【図3】この発明の実施例の光起電力素子の概略的な側
面断面図である。
FIG. 3 is a schematic side sectional view of a photovoltaic device according to an embodiment of the present invention.

【図4】この発明の実施例の水煮装置を示す概略的な側
面断面図である。
FIG. 4 is a schematic side sectional view showing a water boiling apparatus according to an embodiment of the present invention.

【図5】この発明の実施例の軽水を用いた水煮処理を含
むプロセスで作成された薄膜電界効果トランジスタのゲ
ート電圧/ドレイン電流特性を示すグラフである。
FIG. 5 is a graph showing a gate voltage / drain current characteristic of a thin film field effect transistor formed by a process including a boiling process using light water according to an embodiment of the present invention.

【図6】この発明の実施例の重水および軽水と重水の混
合水を用いた水煮処理を含むプロセスで作成された薄膜
電界効果トランジスタのゲート電圧/ドレイン電流特性
を示すグラフである。
FIG. 6 is a graph showing gate voltage / drain current characteristics of a thin-film field-effect transistor formed by a process including a boiling process using heavy water and a mixture of heavy water and heavy water according to an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 水煮装置 12 ステンレス鋼容器 14 圧力計 16 温度計 18 高圧水攪拌プロペラ 20 試料保持金具 24 温度制御装置 22 外部ヒータ 26 支持基板 28 ゲート電極 30 i型アモルファスシリコン膜 32 絶縁膜 34 ソース金属膜 36 ドレイン金属膜 40 支持透明ガラス基板 38 透明電極ITO 42 p+型アモルファスシリコン膜 44 i型アモルファスシリコン膜 46 n型アモルファスシリコン膜 48 アルミニウム電極 DESCRIPTION OF SYMBOLS 10 Water boiler 12 Stainless steel container 14 Pressure gauge 16 Thermometer 18 High pressure water stirring propeller 20 Sample holding fixture 24 Temperature controller 22 External heater 26 Support substrate 28 Gate electrode 30 i-type amorphous silicon film 32 Insulating film 34 Source metal film 36 Drain metal film 40 Supporting transparent glass substrate 38 Transparent electrode ITO 42 p + type amorphous silicon film 44 i-type amorphous silicon film 46 n-type amorphous silicon film 48 aluminum electrode

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 基板上に非単結晶半導体薄膜を堆積した
構造を主体とする素子の製造プロセスにおいて、非単結
晶半導体薄膜を堆積した基板を110℃以上の水中に1
時間以上保持することを特徴とする特性改善方法。
In a device manufacturing process mainly comprising a structure in which a non-single-crystal semiconductor thin film is deposited on a substrate, the substrate on which the non-single-crystal semiconductor thin film is deposited is placed in water at 110 ° C. or higher.
A characteristic improvement method characterized by holding for a time or longer.
【請求項2】 請求項1に記載の水中を、重水中とした
ことを特徴とする請求項1に記載の特性改善方法。
2. The method for improving characteristics according to claim 1, wherein the water according to claim 1 is heavy water.
【請求項3】 請求項1に記載の水中を、軽水と重水の
混合水中としたことを特徴とする請求項1に記載の特性
改善方法。
3. The method for improving characteristics according to claim 1, wherein the water according to claim 1 is a mixed water of light water and heavy water.
【請求項4】 請求項1ないし請求項3に記載の特性改
善方法において、当該非単結晶半導体薄膜が、シリコン
膜・ゲルマニウム膜・窒化シリコン膜・酸化シリコン膜
・シリコンオキシナイトラド膜・炭化シリコン膜・シリ
コンゲルマニウム合金膜のいずれかであることを特徴と
する。
4. The method for improving characteristics according to claim 1, wherein the non-single-crystal semiconductor thin film is a silicon film, a germanium film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or silicon carbide. Film or a silicon germanium alloy film.
JP10294111A 1998-10-15 1998-10-15 Characteristic improvement method in manufacture process of non-single crystalline semiconductor thin film element Pending JP2000124460A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10294111A JP2000124460A (en) 1998-10-15 1998-10-15 Characteristic improvement method in manufacture process of non-single crystalline semiconductor thin film element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10294111A JP2000124460A (en) 1998-10-15 1998-10-15 Characteristic improvement method in manufacture process of non-single crystalline semiconductor thin film element

Publications (1)

Publication Number Publication Date
JP2000124460A true JP2000124460A (en) 2000-04-28

Family

ID=17803442

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000124460A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073545A (en) * 2005-09-02 2007-03-22 Tsukuba Semi Technology:Kk Method for improving crystallinity of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007073545A (en) * 2005-09-02 2007-03-22 Tsukuba Semi Technology:Kk Method for improving crystallinity of semiconductor device

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