JP2000122630A - Display data generation circuit of cord refreshing method display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce decline of an accessing performance to an image memory at the time of image plane refreshing by using a single port DRAM as the image memory. SOLUTION: This display data generation circuit using a single port DRAM as an image memory 3 is equipped with a cord memory 8 for storing display data of one image plane of a display region, a flag resistor 5 for determining whether the content of the image memory 3 in the display region is changed or not, and a cord memory controller 10 for monitoring the flag resistor 5 and for judging whether the access to the image memory 3 is to be executed or not. The cord memory controller 10 executes the access to the image memory 3, only when the content of the image memory 3 is changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer display system and, more particularly, to a computer display system in which arbitrary image data desired to be displayed on a screen is written into an image memory and the image data is stored in a CRT
The present invention relates to a display data generation circuit having a function of converting display data suitable for a display device such as an LCD or an LCD panel and displaying the display data.

[0002]

2. Description of the Related Art As a conventional display data generation circuit of this kind, Japanese Patent Application Laid-Open No. Hei 5-341747 (hereinafter referred to as "prior art 1") discloses a single port memory as an image memory instead of a dual port memory. The technical idea regarding the "display control device" used is disclosed. That is, the prior art 1 is a display control device characterized by using a circuit for emulating a coprocessor instead of a drawing coprocessor and a single port memory as an image memory.

More specifically, in the prior art 1, as a method of emulating a drawing coprocessor, only a coprocessor register is provided, and various parameters for designating drawing processing contents are set in the coprocessor register. When a parameter for drawing is set, an interrupt request for specifying a drawing process based on the set parameter is generated, and the CPU executes the drawing process. Also,
The prior art 1 aims at realizing a large-capacity memory at a relatively low price by using a single-port memory as an image memory.

[0004]

However, according to the prior art 1 described above, when a single-port DRAM is used as an image memory, access to the image memory for image refresh is restricted, and image data from the CPU is limited. There is a problem that the memory access performance is deteriorated.

It is therefore an object of the present invention to provide a low-cost and high-performance display system using a single-port DRAM as an image memory.

Another object of the present invention is to provide a display system capable of reducing deterioration of access performance to an image memory at the time of image refresh by using a single port DRAM as an image memory.

[0007]

The present invention proposes the following means in order to solve the above problems.

That is, according to the present invention, a single port D
An image memory employing a RAM, a code memory for storing display data for one screen of a display area, a flag register for determining whether or not the contents of the image memory in the display area have been changed, and the flag register And a code memory controller for monitoring whether to access the image memory or not, and accessing the image memory only when the content of the image memory is changed. The display data generation circuit of the code refresh type display system described above is obtained.

[0009]

By adopting such a configuration, in a code refresh type display system, even if a single-port DRAM is used as an image memory, if there is no change in the contents of the image memory, a screen refresh is performed. Access to the code memory and not to the image memory. Since the access to the image memory by the screen refresh is limited only when the data in the display area is rewritten, the deterioration of the access performance to the image memory can be reduced. Therefore, a high-performance display circuit using a single-port DRAM as an image memory can be realized.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

Referring to FIG. 1, a display data generating circuit of a code refresh type display system according to an embodiment of the present invention will be described.

The illustrated code refresh type display system has a resolution of 640 dots in width × 400 dots in height and one character is 8 dots in width × 16 dots in height, uses a code refresh method, and has 16 bits of code data and 8 attribute data. It is assumed to be represented by three bytes of bits.

The display data generating circuit shown in FIG. 1 comprises a system bus interface circuit 1, an image memory controller 2, an image memory 3, a line buffer 4, a flag register 5, a display controller 6, and a code memory controller 7. A code memory 8, a multiplexer (MPX) 9, a font memory controller 10,
It has a font memory 11, a display data conversion circuit 12, and a display device 13.

The system bus interface circuit 1 comprises:
Decode and execute access to various display circuits on the system bus. Further, the system bus interface circuit 1 converts commands for internal modules, such as setting of registers necessary for the display circuit or access to the image memory 3.

The image memory controller 2 converts and decodes a command decoded by the system bus interface circuit 1 into a read access or a write access to the actual image memory 3. The image memory controller 2
Also controls the refresh of the image memory 3. further,
The image memory controller 2 receives the display refresh request from the code memory controller 7 and writes the designated data in the image memory 3 to the line buffer 4.

The image memory 3 is a single-port readable and writable memory, and stores code data and attribute data required for the code refresh method.

The line buffer 4 buffers one line of image data (code data and attribute data) of the image memory 3 displayed by the image memory controller 3. The line buffer 4 outputs data in the order in which the data is written by the code memory controller 7.

The flag register 5 is used by the code memory controller 7 to determine whether the data in the code memory 8 is valid or invalid by looking at the data in the flag register 5. "Valid" indicates a case where the data of the image memory 3 to be displayed at present is not changed and the code memory 8 has already taken in the data of the image memory 3. "Invalid" means that the image data of the image memory 3 to be currently displayed has already been changed,
It refers to the case where the data in the code memory 8 must be ignored. When there is a change in the image memory 3, the code memory controller 7 invalidates the data in the changed line.

As shown in FIG. 3, each bit of the flag register 5 corresponds to one bit for each row of the display screen, and is represented by 25 bits. The output of the data receives the data of the current line to be displayed from the display controller 6 and outputs the data corresponding to the line to be displayed.

The display controller 6 has a register (not shown) for displaying characters on the display device 13, and generates display timing of the display device 13 according to the setting.
A display address is generated based on the display area setting. Further, the display controller 6 notifies the flag register 5 of the line on the display screen where the current display position is based on the display address. Further, since one character is 16 dots vertically, the display controller 6 instructs the code memory controller 7 to read the code from the image memory 3 once every 16 lines. Further, since one character is eight horizontal dots, the display controller 6 generates a character clock which is a clock obtained by dividing the dot clock by eight.

The code memory controller 7 monitors a write access from the system bus interface circuit 1 to the image memory 3 and performs a flag operation of the flag register 5. The code memory controller 7 receives the display area data from the display controller 6 and determines whether the write access to the image memory 3 is within the display area. Also,
The code memory controller 7 receives the character code reading instruction from the display controller 6, checks the bit of the flag register 5 corresponding to the line to be currently displayed, and determines whether data is required in the image memory 3 or 8 to determine whether the data exists.

When the flag register 5 indicates invalid, the code memory controller 7 outputs a display refresh request to the image memory controller 2. After the display refresh request, the code memory controller 7 sequentially outputs the image data written in the line buffer 4. Then, the code memory controller 7 controls the MPX 9
, The image data of the line buffer 4 is transferred to the font memory controller 10. At the same time, the code memory controller 7
Is written to the code memory 8 as needed, and after the writing of data for one row is completed, the flag of the flag register 5 corresponding to that row is made valid.

When the flag register 5 indicates valid, the code memory controller 7 sequentially reads out the image data from the code memory 8 and operates the selection signal of the MPX 9 to transfer the image data of the code memory 8 to the font memory controller 10. Pass to.

The code memory 8 is a memory for storing image data for one screen in the display area by the code memory controller 7.

The font memory controller 10 has an MP
It has a function of converting the code data selected in X9 into font data in character clock units. here,
Conversion of font data by the font memory controller 10 is performed by converting code data that is sequentially input into an address of the font memory 11 and reading font data from the font memory 11.

The font memory 11 has font data of characters to be displayed on the screen. The font memory 11 outputs font data based on the converted code data output from the font memory controller 10.

The display data conversion circuit 12 generates a synchronization signal suitable for the display device 13 using the synchronization signal and various display timing signals output from the display controller 6. Further, the display data conversion circuit 12 converts the font data read from the font memory 11 into a data format of the display device 13, adjusts an output synchronization signal and timing, and outputs display data. The attribute data selected by the MPX 9 is adjusted within the display data conversion circuit 12 at the timing when the data similarly converted by the MPX 9 is converted into font data, and the display data conversion circuit 12 modifies the font data.

The display device 13 is a general display device used in a computer such as a CRT or an LCD panel.
The display device 13 displays data on a screen according to the synchronization signal and the display data output from the display data conversion circuit 12.

FIG. 2 shows the output of the line buffer 4 and the output of the code memory 8 in this embodiment,
An example of a timing waveform up to the output of X9 is shown. FIG.
As is clear from the above, the flag status of the flag register 5 is "no change in the contents of the image memory 3 of the line to be displayed".
Is displayed, the MPX 9 selects the output of the code memory 8, and when the flag status of the flag register 5 indicates “the contents of the image memory 3 of the line to be displayed have been changed”, the MPX 9 4 is selected.

FIG. 3 shows the relationship between the vertical direction and the horizontal direction of the display screen and the relationship between the bits of the flag register 5 and the display row in this embodiment, as described above.

As described above, in the present embodiment,
The data once displayed is written into the code memory 8, and from the next screen scanning, the image memory 3 is not accessed for screen refresh unless the contents of the image memory 3 are rewritten. read out. It is possible to access the image memory 3 from the CPU (not shown) for the time when the access to the image memory 3 is not performed.

A specific description will be given. Assuming that the data width of the image memory 3 is 24 bits or more, the number of readouts of display data required for screen refresh per screen is eight.
0 digits × 25 rows = 2000 times. That is, if there is no change in the contents of the image memory 3 in the display area, another access can be made 2000 times per screen.

As is clear from the above description, a low-cost and high-performance display system having a single-port DRAM in the image memory 3 can be provided.

[0034]

As described above, according to the present invention,
An image memory employing a single port DRAM, a code memory for storing display data for one screen of a display area,
An image memory comprising: a flag register for determining whether or not the content of the image memory in the display area has been changed; and a code memory controller for monitoring the flag register and determining whether to access the image memory. Since the image memory is accessed only when there is a change in the content of the image memory, the image memory access for the screen refresh by using the single port DRAM as the image memory can be reduced. There is an effect that deterioration in access performance from the CPU to the image memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a display data generation circuit of a code refresh type display system according to an embodiment of the present invention.

FIG. 2 is a time chart showing an example of a timing waveform in the display data generation circuit shown in FIG. 1 from selection of an output of a line buffer and an output of a code memory to an output of a multiplexer.

FIG. 3 is a diagram illustrating a relationship between a vertical direction and a horizontal direction of a display screen and a relationship between bits of a flag register with respect to a display row in the display data generation circuit illustrated in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 System bus interface circuit 2 Image memory controller 3 Image memory 4 Line buffer 5 Flag register 6 Display controller 7 Code memory controller 8 Code memory 9 Multiplexer (MPX) 10 Font memory controller 11 Font memory 12 Display data conversion circuit 13 Display device

Claims (4)

[Claims] 1. An image memory employing a single-port DRAM, a code memory for storing display data for one screen of a display area, and determining whether or not the contents of the image memory in the display area have been changed. A flag register, and a code memory controller that monitors the flag register and determines whether or not to access the image memory, and only accesses the image memory when the contents of the image memory are changed. A display data generation circuit for a code refresh type display system, wherein the display data generation circuit is configured to perform the above operation. 2. The code memory stores code data and attribute data as the display data.
A display data generation circuit for the code refresh display system according to claim 1. 3. An image memory controller for controlling the image memory, wherein the code memory controller is configured to control the image memory when the flag register indicates that the content of the image memory is changed. 2. The display data generation circuit according to claim 1, wherein the display data generation circuit outputs a display refresh request to a controller. 4. A line buffer for buffering one line of image data of the image memory to be displayed by the image memory controller, and in response to a selection signal of the code memory controller,
4. The display data generating circuit according to claim 3, further comprising a multiplexer for selecting and outputting the output of the line buffer and the output of the code memory.