JP2000121686A - Threshold test circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately determine a threshold and shorten the test time. SOLUTION: In inputting a test signal to operate a threshold circuit BI in a designated repead cycle by a sampling clock, the level determination result determined according to a threshold of the threshold circuit BI is sequentially taken as the threshold test result on the threshold of the threshold circuit in a shift register 15 in synchronization with the sampling clock, and the threshold test result taken in the shift register 15 is output to output circuits of a generating circuit 11 and a test determination output buffer BO from the outside.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold test circuit for an input terminal.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional threshold test circuit for testing a threshold of a threshold circuit such as an I / O input / output buffer in a microcomputer. 7, 1 is an address input terminal for inputting an address signal, 2 is a data input / output terminal for inputting / outputting a data signal, and 3 is an address provided with an input buffer BI for inputting an address signal to the address bus 107. An input circuit 4 is a data input / output circuit having an input buffer BI and an output buffer BO for inputting / outputting a data signal to / from a data bus, 100 is an I / O constituting the address input circuit 3 and the data input / output circuit 4, etc. 101 is C
PU, 102, RAM, 103, ROM, 104, an internal clock generation circuit, 105, a clock terminal for external oscillator circuit output or external clock, 106, a clock signal line for outputting an internal clock, 107, an address bus,
108 is a data bus.

FIG. 8 shows an address input circuit 3 shown in FIG.
FIG. 2 is a circuit diagram showing a configuration of a data input / output circuit 4. FIG.
7, the same or corresponding parts as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 8, 1ai to 1
ni indicates each bit input constituting the address signal, and the address signal is composed of a bit to n bits. 1 ao to 1 no indicate the input of each bit from the a bit to the n bit constituting the internal address signal. 2
ai to 2ni denote each bit from the a bit to the n bit constituting the data signal input / output from the data input / output terminal 2. 2ao to 2no indicate each bit from the a bit to the n bit constituting the internal data signal.

Reference numeral 5 denotes an input buffer B of the address input circuit 3.
Address input control signal supplied to each control terminal of I, 6
Is a data input control signal supplied to each control terminal of the input buffer BI of the data input / output circuit 4, and 7 is an output buffer B
O is a data output control signal supplied to each control terminal.

FIG. 9 shows an address signal input from the address input terminal 1 and an input / output from the data input / output terminal 2 based on a clock signal input to the external oscillation circuit output or the clock terminal 105 for an external clock. FIG. 4 is a timing chart of a data signal.

Next, the operation will be described. In the input / output test circuit shown in FIG.
The frequency of the clock signal input from the external oscillation circuit output or the clock terminal 105 for the external clock is divided and the
An internal clock for operating 101 is generated.

When performing the input test of the I / O 100, first, the bits 1ai to 1ni of the address signal are supplied to the address input terminal 1 of FIG. 8, and each of the input buffers BI of the address input circuit 3 is supplied at the timing of FIG. The address input control signal supplied to the control terminal is turned on, and the address signal is input from the address input terminal 1.

At this time, thresholds VIH and VIL shown in FIG. 9 are set for bits 1ai to 1ni of the address signal input from address input terminal 1. As a result, bits 1ao to 1no of the internal address signal have the same values as bits 1ai to 1ni of the address signal input from the address input terminal 1.

An internal address signal consisting of bit 1 ao to bit 1 no is supplied to the CPU via an address bus 107.
It is input to a program counter in 101.

Next, the data input control signal 6 is turned on, and an instruction code for outputting the data output control signal 7 is input from the data input / output terminal 2 at the timing shown in FIG. At this time, the threshold values VIH and VIL shown in FIG. 9 are set in the data input / output terminal 2. This allows
Bits 2ao to 2no of the internal data signal are input as an instruction code to the CPU 101 via the data bus 108, and as a result, the data output control signal 7 is output from the instruction decoder. Then, at the timing when the data output control signal 7 is output, the address input to the program counter is output from the data input / output terminal 2 via the data bus 108.

As described above, the threshold test of the input terminal is performed by comparing the address input from the address input terminal 1 with the address output from the data input / output terminal 2.

FIG. 10 is a block diagram showing a conventional analog input test circuit. In FIG. 10, the same or corresponding parts as in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. 10, reference numeral 8 denotes an analog input terminal of a comparator to which an analog signal is input, COM denotes the comparator, 9 denotes a test determination result output terminal that outputs a test determination result which is an output of the comparator COM, and 10 denotes a test determination output buffer. A test judgment output control signal 111 supplied to the control terminal of the BO is an internal data input signal.

FIG. 11 is a waveform diagram showing an input waveform at the time of a test and a test judgment output supplied to the analog input terminal of FIG. In FIG. 11, reference numeral 8a denotes a step width of a step voltage constituting an analog signal supplied to the analog input terminal 8, and 8b denotes a threshold voltage for the analog signal supplied to the analog input terminal 8.

Next, the operation will be described. In a threshold test of an amplifier for detecting an analog input (for example, zero-cross detection, etc.), an analog signal composed of a step voltage shown in FIG. 11 is applied to an analog input terminal 8 in FIG. 10, and a data input control signal 6 is turned on. And the test decision output control signal 10 for each step voltage.
Are turned on, and the test determination output is checked to detect a change point (rising portion of the waveform of the test determination result in FIG. 11).

Each of the above-described procedures for the threshold test of the input terminal in the digital circuit and the threshold test of the amplifier for the analog input is programmed through the above-described procedures, and is performed through software.

[0016]

Since the conventional threshold test circuit is configured as described above, it requires an instruction execution time because of the software for the threshold test, and further tests only for the presence or absence of a change. Therefore, there is a problem that an accurate threshold cannot be determined. In a threshold test for a special input (for example, zero-cross detection), a step voltage is input and a change point is checked finely outside, so that an accurate threshold can be determined. (Which may take longer than software-based methods in some cases).

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to provide a threshold test circuit capable of accurately determining a threshold and shortening a test time.

[0018]

A threshold test circuit according to the present invention is characterized in that a test signal is inputted and a threshold circuit is operated based on a threshold value of the threshold circuit when the threshold circuit is operated at a predetermined repetition cycle by a sampling clock. A shift register that sequentially takes in the determined level determination result as a threshold test result in synchronization with the sampling clock; and an output circuit that outputs the threshold test result taken into the shift register to the outside. .

A threshold test circuit according to the present invention is based on a test determination output control signal generated by incorporating a level determination result for one cycle of a test signal into all bits of a shift register as a threshold test result. And an output circuit for outputting the threshold test result from the shift register operating in synchronization with a sampling clock to the outside.

According to the threshold test circuit of the present invention, a sampling clock is generated based on a test determination output control signal generated by incorporating a level determination result of a test signal into a first stage bit of a shift register as a threshold test result. An output circuit outputs the level determination result from the shift register operating in synchronization to the outside.

A threshold test circuit according to the present invention is characterized in that a test signal is input to a plurality of threshold circuits and each of the threshold circuits is operated at a predetermined repetition cycle by a sampling clock, based on a threshold value of each of the threshold circuits. The threshold determination result is taken in as a threshold test result in synchronization with the sampling clock, and a shift register provided for each of the threshold circuits and connected in series with another shift register, and the threshold circuit, A switch circuit for opening and closing a path for taking a threshold test result to the shift register for each circuit; and when the switch circuit opens the taking path, the circuit is taken into each of the serially connected shift registers. And an output circuit for continuously outputting the threshold test result from one test determination output terminal to the outside. Than it is.

According to the threshold test circuit of the present invention, when a test signal is input and the threshold circuit is operated at a predetermined repetition cycle by a sampling clock, a level determination result determined based on the threshold value of the threshold circuit is obtained. A shift register which sequentially takes in as a threshold test result in synchronization with the sampling clock; an upper limit specification value and a lower limit specification value which are standards for the threshold value of the threshold circuit; and the threshold test result which is taken in the shift register. A determination circuit that outputs a test determination output control signal according to a threshold state of the threshold circuit indicated by the threshold test result with respect to a range defined by the upper limit specification value and the lower limit specification value; An output circuit that outputs the threshold test result to the outside based on the test determination output control signal output by the determination circuit. It is obtained by obtaining way.

A threshold test circuit according to the present invention holds an upper limit specification value holding circuit that holds an upper limit specification value that is a standard for a threshold value of a threshold circuit, and holds a lower limit specification value that is a standard value for a threshold value of the threshold circuit. A lower limit specification value holding circuit,
A first comparator for comparing a threshold test result taken into the shift register with an upper limit specification value held in the upper limit specification value holding circuit and outputting a comparison result; and the threshold test taken into the shift register. A second comparator for comparing a result with a lower limit specification value held in the lower limit specification value holding circuit and outputting a comparison result; and a comparison result output by the first comparator and the second comparator. Based on the comparison result output, a test determination output control signal according to the threshold state of the threshold circuit indicated by the threshold test result for the range defined by the upper limit specification value and the lower limit specification value And a control signal output circuit for outputting the control signal.

A threshold test circuit according to the present invention includes a D / A converter for converting a threshold test result taken into a shift register into an analog signal, and an upper limit standard value which is a standard for a threshold value of the threshold circuit. A first voltage detector that holds the value as a value, compares the threshold test result converted into an analog signal by the D / A converter with the held analog upper reference value, and outputs a comparison result; A lower limit specification value which is a standard for a threshold value of a threshold circuit is held as an analog lower reference value, and the threshold test result converted into an analog signal by the D / A converter and the held analog lower reference value are compared. A second voltage detector that compares and outputs a comparison result; and a comparison result output by the first voltage detector and a comparison result output by the second voltage detector. When the threshold test result exceeds a range defined by the analog upper reference value and the analog lower reference value, the determination circuit includes a control signal output circuit that outputs a test determination output control signal. It was made.

A threshold test circuit according to the present invention includes a D / A converter for converting a threshold test result taken into a shift register into an analog signal, and an upper limit standard value which is a standard for a threshold value of the threshold circuit. A first voltage detector that holds the value as a value, compares the threshold test result converted into an analog signal by the D / A converter with the held analog upper reference value, and outputs a comparison result; A lower limit specification value which is a standard for a threshold value of a threshold circuit is held as an analog lower reference value, and the threshold test result converted into an analog signal by the D / A converter and the held analog lower reference value are compared. A second voltage detector for comparing and outputting a comparison result, and a threshold value of the threshold circuit or an arbitrary threshold level between an upper limit specification value and a lower limit specification value. Held as a log on the lower within the reference value,
A third voltage detector that compares the threshold test result converted into an analog signal by the D / A converter with the held analog upper / lower limit reference value and outputs a comparison result; A voltage detector, the second voltage detector, and a comparison result output from the third voltage detector based on any combination of the analog upper reference value, the analog lower reference value, and And a test determination result output circuit that outputs a test determination result according to a threshold state of the threshold circuit indicated by the threshold test result for each range defined by an analog upper and lower limit reference value. It was made.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to the first embodiment. This data input / output circuit is configured as, for example, an I / O data input / output circuit in the microcomputer shown in FIG. In FIG. 1, 41 is a data input / output circuit, BO is a test determination output buffer (output circuit),
BI is a threshold circuit, and is a circuit to be subjected to a threshold test. Reference numeral 10 denotes a test determination output control signal supplied to the control terminal of the test determination output buffer BO. For example, when the output of the threshold circuit BI for an analog signal is stored in the first bit of the shift register 15, or This signal is output when the output of the threshold circuit BI for one cycle of the analog signal is stored in all the bits of the register 15.
Reference numeral 11 denotes a circuit (output circuit) for generating the test determination output control signal 10, which generates and outputs the test determination output control signal 10 when a shift clock is input to the shift register 15. Alternatively, the shift clock supplied to the shift register 15 is counted, and when the output of the threshold circuit BI for one cycle of the analog signal is stored in all the bits of the shift register 15, the test determination output control signal 10 is generated. Output.

A sampling clock 12 for sampling the input analog signal is a shift clock for the shift register 15. Reference numeral 13 denotes an analog signal input terminal for inputting the analog signal, 14 denotes a test determination output terminal for outputting a test result, and 15 denotes, for example, an 8-bit shift register.

FIG. 2 is an explanatory diagram showing the operation of the threshold test circuit. FIG. 2A shows an analog signal input to the analog signal input terminal 13, and Vth denotes a threshold circuit BI.
(B) shows the sampling clock of the analog signal, and (c) shows the output of the threshold circuit BI stored in the shift register 15 sequentially shifted by the shift clock. FIG. 9D shows the test state output from the test state output terminal 14 in the transition state.

Next, the operation will be described. In this embodiment, the analog signal input to the analog signal input terminal 13 is a pseudo sine wave (a triangular wave or a sawtooth wave may be used). The pseudo sine wave is supplied to the threshold circuit BI at the rising timing of the sampling clock 12. The level when the pseudo sine wave is captured is determined based on the threshold Vth of the threshold circuit BI. If the level exceeds the threshold Vth, the value is set to “1”; A binary signal “0” is output. The binary signal of "1" or "0" is sequentially stored in the shift register 15 in synchronization with the shift clock. Then, for example, when the output of the threshold circuit BI is shifted and stored in all the bits of the shift register 15, a test determination output control signal 10 is generated in the generation circuit 11, and the data stored in the shift register 15 It is output as a test determination output to the test determination output terminal 14 in synchronization with the clock.

Note that the test decision output control signal 10 may be generated when the first stage bit of the shift register 15 is determined. In this case, the generation circuit 11 sends the threshold circuit BI to the first stage of the shift register 15. And latches the sampling clock 12a at the timing when the output is taken in, and outputs the test determination output control signal 10 to the control terminal of the test determination output buffer BO. Alternatively, the configuration may be such that the sampling clock 12 is supplied to the control terminal of the test determination output buffer BO.

In the above description, an 8-bit shift register is used. However, the number of bits of the shift register 15 may be increased to further increase the accuracy. At this time, it is necessary to increase the repetition frequency of the sampling clock as the number of bits of the shift register 15 increases.
Therefore, an internal clock and a clock obtained by dividing the internal clock are used as a multi-phase clock, or a clock (not shown) having a phase difference of a PLL is used as a multi-phase clock and used as a sampling clock and a shift clock. .

As described above, according to the first embodiment, the threshold value Vth of the threshold value circuit BI can be accurately grasped, and the threshold value needs to be determined only once. In addition, since the threshold test is performed by hardware instead of the threshold test based on the program operation, software execution time is not required, and a threshold test circuit capable of improving the accuracy of the threshold test result and reducing the test time is obtained. Has the effect.

Embodiment 2 FIG. FIG. 3 shows the second embodiment.
2 is a circuit diagram showing a configuration of a data input / output circuit including the threshold test circuit of FIG. 3, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. FIG.
, 42 is a data input / output circuit, and 16 is a threshold circuit B
An upper limit threshold circuit (upper limit value holding circuit, judgment circuit) in which a threshold upper limit value defined by the standard is set for the threshold value Vth of I, and 17 is a threshold lower limit value defined by the standard for the threshold value Vth of the threshold circuit BI Is a lower limit threshold circuit (lower limit specification value holding circuit, determination circuit) in which is set, and a comparator 18 compares a threshold upper limit value set in the upper limit threshold circuit 16 with an output of the threshold circuit BI stored in the shift register 15. (First comparator, determination circuit), 19 is a comparator (second comparator, which compares the lower threshold value set in the lower threshold circuit 17 with the output of the threshold circuit BI stored in the shift register 15). Determination circuit). Reference numeral 20 denotes the comparison result of the comparator 18 and the comparator 19
Based on the comparison result, the test determination output control signal 10 is generated only when the threshold value Vth of the threshold circuit BI is out of the standard, and the test determination output which is the output of the threshold circuit BI is output from the test determination output terminal 14. An exOR circuit (control signal output circuit, determination circuit) that enables output.

Next, the operation will be described. In the second embodiment, the operation until the output of the shift register 15 is extracted is the same as in the first embodiment. In the threshold test circuit according to the second embodiment, the upper threshold value defined by the standard for the threshold circuit BI is set in the upper threshold circuit 16, and the lower threshold value is set in the lower threshold circuit 17. The comparator 18 compares the upper threshold value set in the upper threshold circuit 16 with the output of each bit of the shift register 15, and compares the lower threshold value set in the lower threshold circuit 17 with each bit of the shift register 15. Is compared with the output of the comparator 19.

The threshold upper limit value is set to Vth_H (8-bit threshold
Value upper limit data), threshold lower limit value is Vth_L (8-bit configuration
, The output of the shift register 15 is SR
_OUTThen, in the comparator 18, Vth_H > SR_OUT In
Vth_H > SR_OUT If ratio
A 'High' level is output as the comparison result. Also, the ratio
In comparator 19, Vth_L <SR_OUT Whether or not
Vth_L <SR _OUT 比較 H
and outputs the high level. As a result, the shift register
15 output SR_OUT Is the threshold upper limit value Vth_H And the lower threshold value
Vth_L , That is, the threshold of the threshold circuit BI
Is out of the standard, the exOR circuit 20 outputs “High”
Output level. The output of this exOR circuit 20 is
For example, the data is latched and
Is supplied to the control terminal of the
Activate the output buffer BO
Test which is the output of the threshold circuit BI stored in the
Test output is output in synchronization with the shift clock.
Output from the terminal 14 is enabled.

As described above, the output of the shift register 15 is compared by the comparators 18 and 19, and the test decision output control signal 1 is output only when the threshold value of the threshold circuit BI is out of the standard.
0 is generated, and the threshold value circuit BI
Is output. As a result, it is not necessary to make all determinations externally, so that the test time can be shortened, and the value of the shift register 15 is stored in the RAM shown in FIG.
If stored in 102 or the like, there is an effect that a threshold test circuit capable of confirming an actual value after the test can be obtained.

Embodiment 3 FIG. 4 shows the third embodiment.
2 is a circuit diagram showing a configuration of a data input / output circuit including the threshold test circuit of FIG. 4, the same or corresponding parts as those in FIG. 1 or FIG. 3 are denoted by the same reference numerals, and description thereof is omitted. 4, the data input-output circuit 43, the D / A converter (decision circuit) 28, 21 is a voltage detection circuit (first upper limit standard value Vth _H defined by the standard to a threshold circuit BI is set the voltage detector, the decision circuit), 22 is a voltage detection circuit for lower specification value Vth _L defined by the standard to a threshold circuit BI is set (second voltage detector, the determination circuit).

Next, the operation will be described. The operation until the output of the shift register 15 is extracted is described in the first embodiment.
Is the same as In the second embodiment, the output of each bit of the shift register 15 is converted into an analog voltage by the D / A converter 28, and the level of this analog voltage is set to the upper limit standard value Vth _{H of} the threshold set in the voltage detection circuit 21. And the level of the analog voltage is detected by a voltage detection circuit 2.
The threshold value is compared with the lower limit specification value Vth _L set to 2.

The voltage detection circuit 21 outputs a smaller if 'High' level than the upper limit standard value Vth _H level threshold of the analog voltage D / A converter 28 is outputted,
The level of the analog voltage is lower than the lower limit standard value Vt.
If it is greater than h _{L, a} 'High' level is output.

As a result, the output of the shift register 15 becomes the upper limit standard value Vth _H and the lower limit standard value Vth _{L of the} threshold value.
If between the exOR circuit 20 outputs a 'Low' level, and if not between the lower specification value Vth _L and upper limit standard value Vth _H of the threshold, i.e. the threshold circuit BI
If the threshold value is out of the standard, a “High” level is output. The output of the exOR circuit 20 is, for example, latched and supplied as a test determination output control signal 10 to the control terminal of the test determination output buffer BO, activates the test determination output buffer BO, and stores the threshold value stored in the shift register 15 The test determination output, which is the output of the BI, is read out in synchronization with the shift clock, and can be output from the test determination output terminal 14.

As described above, the output of the shift register 15 is compared between the voltage detection circuit 21 and the voltage detection circuit 22, and the test judgment output control signal 10 is generated only when the threshold value of the threshold circuit BI is out of the standard. From the test judgment output terminal 14, the test judgment output of the threshold circuit BI which is out of the standard is taken out. As a result, it is not necessary to perform all the determinations externally, so that the test time can be reduced. In addition, if the value of the shift register 15 is stored in the RAM 102 or the like shown in FIG. There is an effect that can be obtained.

Embodiment 4 FIG. 5 shows the fourth embodiment.
2 is a circuit diagram showing a configuration of a data input / output circuit including the threshold test circuit of FIG. 5, the same or corresponding parts as those in FIG. 4 or FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 5, 44 is a data input / output circuit, 14a
And 14b are test decision output terminals, BO1 and BO
2 test determines the output buffer (test result output circuit) 20a and 20b exOR circuit (test analysis result output circuit), the standard value of the threshold in the threshold circuit BI 23 or upper specification limit Vth _H and the lower limit standard value Vth _L voltage detecting circuit arbitrary value Vth _M is set between the (third voltage detector, the decision circuit) is.

Next, the operation will be described. The output of the D / A converter 28, operation up to the upper limit standard value Vth _H is set voltage detecting circuit 21 and the lower limit standard value Vth _L threshold threshold is input to the voltage detection circuit 22 which is set in the This is the same as the third embodiment.

In the fourth embodiment, the voltage detection circuit 23
Since any value Vth _M between the upper standard value Vth _H and the lower limit standard value Vth _L standard value or the threshold in the threshold is set to, the voltage detection circuit 23, D / A converter 28
The level of the analog voltage, which is the output of
comparing any value Vth _M between th _H and the lower limit standard value Vth _L. In this case, the level of the analog voltage is set to AS
Then, the voltage detection circuit 23 determines whether or not AS> Vth _M. Then, AS> Vth _M a long if the voltage detection circuit 23 outputs a 'High' level.

The exOR circuit 20a outputs an exclusive OR operation result of the output of the voltage detection circuit 21 and the output of the voltage detection circuit 23, and the exOR circuit 20b outputs the output of the voltage detection circuit 22 and the output of the voltage detection circuit 23. Outputs the result of exclusive OR operation with the output. The output of the exOR circuit 20a is output to the test determination output buffer BO1. Also, exO
The output of the R circuit 20b is supplied to a test determination output buffer BO2.

[0046] Therefore, if beyond the level AS, i.e. the upper limit standard value data indicating output is stored threshold circuit BI is in the shift register 15 Vth _H of a is the analog voltage output of the D / A converter 28, EXOR Only the circuit 20a outputs a “High” level. And this exOR
The output of the circuit 20a is used as a test judgment output via a test judgment output buffer BO1 as a test judgment output terminal 14a.
Output from

If the level AS of the analog voltage output from the D / A converter 28 is within the range between Vth _M set in the voltage detection circuit 23 and the upper limit standard value Vth _H , an exOR circuit Both outputs of 20a and 20b are 'L
ow 'level. Therefore, as a test determination output, “Lo” is output from both the test determination output terminals 14a and 14b.
The w 'level is output.

If the level AS of the analog voltage output from the D / A converter 28 is within the range between Vth _M set in the voltage detection circuit 23 and the lower limit specification value Vth _L , exOR Both circuits 20a and 20b are set to "Hig".
Outputs the h 'level. Then, this exOR circuit 20
The outputs of a and 20b are test decision output buffers BO1, B
The signal is supplied to O2, and a “High” level is output from the test determination output terminals 14a and 14b as a test determination output.

[0049] The level AS of which is the output analog voltage of the D / A converter 28, if lower than the lower limit standard value Vth _L, only exOR circuit 20a outputs a 'High' level, as a result, the test The “High” level is output only from the test determination output terminal 14a as the determination output.

As a result, it becomes clear on which side the threshold value of the threshold circuit BI is distributed between the upper limit specification value and the lower limit specification value, so that feedback to the wafer process and correction of the threshold circuit BI become easy. There is an effect that a threshold test circuit can be obtained.

Embodiment 5 FIG. FIG. 6 shows the fifth embodiment.
2 is a circuit diagram showing a configuration of a data input / output circuit including the threshold test circuit of FIG. 6, the same or corresponding parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. FIG.
In the figure, 45 is a data input / output circuit, 13a to 13n are analog input terminals, BIa to BIn are threshold circuits, SWa
To SWn are switch circuits. Shift registers 15a to 15n are connected in series.

Next, the operation will be described. Each threshold circuit B
The switch circuits SWa to SWn arranged between Ia to BIn and the shift registers 15a to 15n are normally in an on state when a threshold test signal is input. An analog signal having the waveform shown in FIG. 2 is input to each of the analog input terminals 13a to 13n, and the outputs of the threshold circuits BIa to BIn are stored in the shift registers 15a to 15n, respectively. When the analog signal input from each of the analog input terminals 13a to 13n is completed, the switch circuits SWa to SWn are turned off.

The shift register 1 connected in series
5a to 15n, and a test determination output control signal 10 to the control terminal of the test determination output buffer BO to supply the shift registers 15a to 15n.
The output of each of the threshold circuits BIa to BIn stored in 15n is output from the test determination output terminal 14.

As described above, according to the fifth embodiment, it is possible to simultaneously perform a threshold test on a plurality of analog input terminals and obtain a threshold test circuit that requires only one test determination output terminal. is there.

[0055]

As described above, according to the present invention, the judgment is made based on the threshold value of the threshold circuit when the test signal is input and the threshold circuit is operated at a predetermined repetition cycle by the sampling clock. An output circuit for sequentially taking a level determination result as a threshold test result for the threshold value of the threshold circuit into a shift register in synchronization with the sampling clock, and outputting the threshold test result taken into the shift register to the outside. This configuration eliminates the need for software execution time, and has the effect of improving the accuracy of threshold test results and shortening the test time.

According to the present invention, the sampling clock is generated based on the test determination output control signal generated by incorporating the level determination result for one cycle of the test signal into all the bits of the shift register as the threshold test result. Since the threshold test result is output from the shift register operating in synchronization with the sampling clock to the outside, the level determination result for one cycle of the test signal is obtained from the shift register operating in synchronization with the sampling clock. The threshold test result based on the threshold test result is output immediately, the accuracy of the threshold test result is improved, the execution time of software is not required, and the test time can be shortened.

According to the present invention, the level determination result of the test signal is taken into the first stage bit of the shift register as the threshold test result, and the test determination output control signal generated in synchronization with the sampling clock is used. Since the shift register that operates is configured to output the threshold test result to the outside, the shift register that operates in synchronization with the sampling clock is based on a level determination result of a predetermined period of a test signal. A threshold test result is obtained after outputting the sampling clocks for the number of bits of the shift register, so that the accuracy of the threshold test result is improved, the execution time of software is not required, and the test time is shortened.

According to the present invention, when a test signal is input to a plurality of threshold circuits and each of the threshold circuits is operated at a predetermined repetition cycle by a sampling clock, a determination is made based on the threshold of each of the threshold circuits. The level judgment result
As a threshold test result of each of the threshold circuits, the data is taken into a shift register provided for each of the threshold circuits and connected in series with another shift register in synchronization with the sampling clock, and taken into each of the shift registers connected in series. Since the threshold test results obtained are continuously output to the outside from one test determination output terminal, each threshold test of a plurality of threshold circuits can be performed simultaneously, and the threshold test results can be obtained at once. In addition, only one test determination output terminal is required, the accuracy of the threshold test result is improved, and the execution time of software is not required, so that the test time can be shortened.

According to the present invention, when the test signal is input and the threshold circuit is operated at a predetermined repetition cycle by the sampling clock, the level determination result determined based on the threshold value of the threshold circuit is determined by the threshold test. As a result, sequentially taken into the shift register in synchronization with the sampling clock, based on the upper limit specification value and the lower limit specification value which are the standards for the threshold value of the threshold circuit and the threshold test result taken into the shift register, Outputs a test determination output control signal according to a threshold state of the threshold circuit indicated by the threshold test result with respect to a range defined by the upper limit specification value and the lower limit specification value, and outputs the threshold test result to an external device. Since the configuration is such that the threshold value of the threshold circuit indicated by the threshold test result indicates the upper limit specification value The threshold test result can be output to the outside only when it is outside the range defined by the lower limit specification value, and only the test determination of the problematic threshold circuit needs to be performed externally. There is no need to make an external determination, and the test time can be shortened.

According to the present invention, the upper limit standard value, which is the standard for the threshold value of the threshold circuit, is held in the upper limit standard value holding circuit, and the lower limit standard value, which is the standard for the threshold value of the threshold circuit, is stored in the lower limit standard value holding circuit. And a first comparator compares the threshold test result captured by the shift register with the upper limit standard value held by the upper limit standard value holding circuit, and outputs a comparison result, which is captured by the shift register. The second threshold value is compared with the lower limit specification value held in the lower limit value holding circuit by a second comparator, and a comparison result is output.The comparison result output by the first comparator is compared with the comparison result output by the first comparator. 2, based on the comparison result output from the comparator 2, and according to the threshold state of the threshold circuit indicated by the threshold test result with respect to a range defined by the upper limit specification value and the lower limit specification value. Control signal Since the output circuit is configured to output a test determination output control signal, the threshold state of the threshold circuit indicated by the threshold test result is out of the range defined by the upper limit specification value and the lower limit specification value. Only in certain cases, it is possible to output the output of the threshold circuit to the outside, so that only the test determination of the problematic threshold circuit needs to be performed externally. This has the effect of reducing time.

According to the present invention, the threshold test result taken into the shift register is converted into an analog signal by the D / A converter, and the threshold test result converted into the analog signal by the D / A converter is held. The first voltage detector compares the set analog upper limit reference value with the analog upper limit reference value and outputs a comparison result. The threshold test result converted into an analog signal by the D / A converter and the held analog lower limit reference value are output. The second voltage detector compares the value with a second voltage detector and outputs a comparison result. Based on the comparison result output by the first voltage detector and the comparison result output by the second voltage detector, Since the threshold test result is configured to output a test determination output control signal from the control signal output circuit when the value exceeds the range defined by the analog upper reference value and the analog lower reference value, The threshold test result may be output to the outside only when the threshold state of the threshold circuit indicated by the threshold test result is outside the range defined by the analog upper reference value and the analog lower reference value. This makes it possible to perform only the test determination of the problematic threshold circuit externally, eliminating the need to perform all the determinations externally, and has the effect of reducing the test time.

According to the present invention, the threshold test result taken into the shift register is converted into an analog signal by the D / A converter, and the threshold test result converted into the analog signal by the D / A converter is held. The first voltage detector compares the set analog upper limit reference value with the analog upper limit reference value and outputs a comparison result. The threshold test result converted into an analog signal by the D / A converter and the held analog lower limit reference value And a comparison result is output by a second voltage detector, and a comparison result is output. The threshold test result converted into an analog signal by the D / A converter and a held analog upper / lower reference value are converted into a third value. A voltage detector compares and outputs a comparison result, and a combination of any of the comparison results output by the first voltage detector, the second voltage detector, and the third voltage detector Originally, a test according to the threshold state of the threshold circuit indicated by the threshold test result for each range defined by the analog upper reference value, the analog lower reference value, and the analog upper and lower reference values. Since the test result output circuit is configured to output the judgment result, it is possible to determine on which side the threshold value of the threshold circuit is distributed within the range of the upper limit standard value and the lower limit standard value, and it is possible to determine the wafer process. Feedback and correction of the threshold circuit are facilitated, the accuracy of the threshold test result is improved,
Further, there is an effect that the execution time of software is not required, and the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to Embodiment 1 of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of the threshold test circuit according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to Embodiment 2 of the present invention;

FIG. 4 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to Embodiment 3 of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a data input / output circuit including a threshold test circuit according to a fifth embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional threshold test circuit.

FIG. 8 is a circuit diagram showing a configuration of an address input circuit and a data input / output circuit in a conventional threshold test circuit.

FIG. 9 is a timing chart of an address signal input from an address input terminal and a data signal input / output from a data input / output terminal in a conventional threshold test circuit.

FIG. 10 is a block diagram showing a conventional analog input test circuit.

FIG. 11 is a waveform diagram showing an input waveform supplied to an analog input terminal and a test determination output in a conventional analog input test circuit.

[Explanation of symbols]

BI, BIa, BIb to BIn threshold circuit, BO test decision output buffer (output circuit), BO1, BO2 test decision output buffer (test decision result output circuit), S
Wa, SWb to SWn switch circuit, 11 generation circuit (output circuit), 15, 15a, 15b to 15n shift register, 16 upper limit threshold circuit (upper limit specification value holding circuit,
Judgment circuit), 17 lower limit threshold circuit (lower limit specification value holding circuit, judgment circuit), 18 comparators (first comparator, judgment circuit), 19 comparators (second comparator, judgment circuit), 20
exOR circuit (control signal output circuit, judgment circuit), 20
a, 20b exOR circuit (test determination result output circuit), 21 voltage detection circuit (first voltage detector, determination circuit), 22 voltage detection circuit (second voltage detector, determination circuit), 23 voltage detection circuit ( Third voltage detector, determination circuit), 28 D / A converter (determination circuit).

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G032 AA04 AA09 AB04 AC07 AE08 AE10 AG01 AG07 AK11 AK14 2G035 AA02 AB10 AC15 AD23 AD65 2G036 AA27 BB09 CA10 9A001 BB02 BB03 BB04 EE05 KK31 KK37 LL05

Claims (8)

[Claims] 1. A threshold test circuit for performing a threshold test to determine whether an actual threshold of a threshold circuit in which a standard for a threshold is set is within the standard, wherein a test signal is input and the threshold circuit is sampled. When operating at a predetermined repetition cycle by a clock, a level determination result of the test signal determined based on a threshold of the threshold circuit is synchronized with the sampling clock as a threshold test result of the threshold of the threshold circuit. And a shift register that sequentially takes in the shift register, and an output circuit that externally outputs the threshold test result taken into the shift register. 2. An output circuit, comprising: a sampling clock based on a test determination output control signal generated by incorporating a level determination result for one cycle of a test signal into all bits of a shift register as a threshold test result; 2. The threshold test circuit according to claim 1, wherein the threshold test result is output to the outside from the shift register operating in synchronization with the threshold test. 3. An output circuit, in synchronization with a sampling clock, based on a test determination output control signal generated by incorporating a level determination result of a test signal into a first stage bit of a shift register as a threshold test result. 2. The threshold test circuit according to claim 1, wherein the threshold test result is output from the operating shift register to the outside. 4. A threshold test circuit for performing a threshold test as to whether an actual threshold value of a threshold circuit in which a standard for a threshold value is defined is within the standard, wherein a test signal is input to a plurality of threshold circuits. When each of the threshold circuits is operated at a predetermined repetition cycle by a sampling clock, a level determination result determined based on a threshold of each of the threshold circuits is taken in as a threshold test result in synchronization with the sampling clock, and A shift register provided for each threshold circuit and connected in series with another shift register; and a switch circuit for opening and closing a path for taking in a level determination result from the threshold circuit to the shift register for each threshold circuit. When the take-in path is opened by the switch circuit, the take-in to each shift register connected in series is performed. An output circuit for continuously outputting a threshold test result to the outside from one test determination output terminal. 5. A threshold test circuit for performing a threshold test to determine whether an actual threshold value of a threshold circuit in which a standard for a threshold value is within the standard is input, and a test signal is input to sample the threshold circuit. When operating at a predetermined repetition cycle by a clock, a level determination result determined based on the threshold value of the threshold circuit is
A shift register that sequentially takes in as a threshold test result of the threshold circuit in synchronization with the sampling clock; an upper limit specification value and a lower limit specification value that are standards for a threshold value of the threshold circuit; and the threshold test result that is taken into the shift register. Based on the above, the determination that outputs a test determination output control signal according to the threshold state of the threshold circuit indicated by the threshold test result for the range defined by the upper limit specification value and the lower limit specification value A threshold test circuit comprising: a circuit; and an output circuit that outputs the threshold test result to the outside based on the test determination output control signal output by the determination circuit. 6. A determination circuit, comprising: an upper-limit specification value holding circuit that holds an upper-limit specification value that is a standard for a threshold value of a threshold circuit; and a lower-limit specification value that holds a lower-limit specification value that is a specification of a threshold value of the threshold circuit. A holding circuit; a first comparator for comparing a threshold test result taken into the shift register with the upper limit specification value held in the upper limit specification value holding circuit and outputting a comparison result; A second comparator that compares the threshold test result with a lower limit specification value held in the lower limit specification value holding circuit and outputs a comparison result; and a comparison result output by the first comparator and the second comparator. 2, based on the comparison result output by the comparator 2, and according to the threshold state of the threshold circuit indicated by the threshold test result with respect to a range defined by the upper limit specification value and the lower limit specification value. Threshold test circuit according to claim 5, characterized in that a control signal output circuit for outputting the strike determination output control signal. 7. A D / A converter for converting a threshold test result taken into a shift register into an analog signal, and an upper limit standard value, which is a standard for a threshold value of the threshold circuit, is held as an analog upper limit reference value. A first voltage detector that compares the threshold test result converted into an analog signal by the D / A converter with the held analog upper reference value and outputs a comparison result; A lower limit standard value, which is a standard for a threshold, is held as an analog lower limit reference value, and the threshold test result converted into an analog signal by the D / A converter is compared with the held analog lower limit reference value. A second voltage detector that outputs a result; and a threshold value based on a comparison result output by the first voltage detector and a comparison result output by the second voltage detector. 6. A control signal output circuit for outputting a test determination output control signal when a test result exceeds a range defined by the analog upper reference value and the analog lower reference value. A threshold test circuit as described. 8. A decision circuit, comprising: a D / A converter for converting a threshold test result taken into a shift register into an analog signal; and an upper limit standard value, which is a standard for a threshold value of the threshold circuit, held as an analog upper limit reference value. A first voltage detector that compares the threshold test result converted into an analog signal by the D / A converter with the held analog upper reference value and outputs a comparison result; A lower limit standard value, which is a standard for a threshold, is held as an analog lower limit reference value, and the threshold test result converted into an analog signal by the D / A converter is compared with the held analog lower limit reference value. A second voltage detector that outputs a result, and a standard value of a threshold value of the threshold circuit or an arbitrary threshold level between an upper limit specification value and a lower limit specification value. A third voltage detector that holds the value as a value, compares the threshold test result converted to an analog signal by the D / A converter with the held analog upper / lower limit reference value, and outputs a comparison result. Based on any combination of the comparison results output by the first voltage detector, the second voltage detector, and the third voltage detector, the analog upper reference value and the analog A test determination result output circuit that outputs a test determination result according to a threshold state of the threshold circuit indicated by the threshold test result for each range defined by the lower limit reference value and the analog upper and lower limit reference value. The threshold test circuit according to claim 5, further comprising: