JP2000115656A - Graphics display circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of image quality of graphics image by providing a synthesizing circuit, which synthesizes the I(interlace) graphics input and the output of a switch I based on the graphics synthesizing control signal I input, an I image output terminal which outputs the output of the synthesizing circuit, etc. SOLUTION: P(progressive) graphics signals inputted via a P graphics input terminal 121 are synthesized by a synthesizing circuit C 124, based on a graphics synthesizing control signal P and then outputted via an image output terminal 105. Meanwhile, I graphics signals inputted via an I graphics input terminal 123 are synthesized by a synthesizing circuit D 125, based on a graphics synthesizing signal I and then outputted via an I image output terminal 106. Thereby since an I/P conversion circuit 101 and a P/I conversion circuit 102 transmit no graphics signals, an interpolation calculation for an I/P conversion mode and the conversion of the number of scanning lines of a P/I conversion mode will not be carried out, and, deterioration of the image quality of graphics images will not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to simultaneously output signals corresponding to each of a progressive system and an interlace system when graphics generated by digital data broadcasting or the like are combined with video and output. The present invention relates to a graphics display circuit.

[0002]

2. Description of the Related Art As a technique capable of simultaneously outputting a progressive video and an interlaced video in which a graphics signal is synthesized, an input video signal is converted into a progressive video (hereinafter referred to as a P video). If you want to create progressive graphics
I which has been converted from a progressive system to an interlaced system (hereinafter referred to as P → I conversion) after being synthesized with a video
This is realized by simultaneously outputting a video and a P video obtained by synthesizing progressive graphics with the input P video, and when the input video signal is an interlaced video (hereinafter, referred to as an I video). Creates interlaced graphics and combines them into I-video, then converts from interlaced to progressive (hereinafter I →
There is known a P-picture which is realized by simultaneously outputting a P picture which is described as P conversion) and an I picture obtained by combining interlaced graphics with an input I picture. An example will be described with reference to the drawings.

FIG. 5 shows a conventional example of a device for simultaneously outputting a P image and an I image. In FIG. 5, reference numeral 100 denotes an input terminal of an I video or P video, 108 denotes an input terminal of an I graphics or P graphics, and 107 denotes an I or P
A control signal input terminal 109 for synthesizing graphics input from the graphics input terminal 108 and video input from the I or video input terminal 100, and 109 is a graphics input from the I or P graphics input terminal 108. And a video input from the video input terminal 100 or a video signal input from the video input terminal 100.

[0004] 101 is an I → P for converting an I image into a P image.
A conversion circuit 102 is a P → I conversion circuit for converting a P video into an I video, and 103 is a switch for switching between the signal output from the synthesis circuit 109 and the output of the I → P conversion circuit 101. If the input video input is a P video, the signal itself output from the synthesizing circuit 109 is selected. On the other hand, if the video input signal input to the input terminal 100 is an I video, an I → P conversion circuit is used. The switches P and 104 that select and output the output of the output circuit 101 are the synthesis circuit 1
A switch for switching between the signal output from the input terminal 09 and the output of the P → I conversion circuit 102. If the video input input to the input terminal 100 is an I video, the signal output from the synthesis circuit 109 is selected. , On the other hand, the input terminal 10
If the video input signal input to 0 is a P video, P →
Switches I and 105 for selecting and outputting the output of the I conversion circuit 102 are P video output terminals, and 106 is an I video output terminal.

[0005] The operation of this device is as follows. A video signal input from an I or P video input terminal 100 is combined with a graphics input from an I or P graphics input terminal to a synthesis control signal input from a synthesis control signal input terminal. The combining is performed by the combining circuit 109 based on the combination. When the composite signal is progressive, the composite progressive signal is output as a P image, and the composite progressive signal is output as P → I
The conversion circuit 102 performs an interlace signal conversion by a scanning line number conversion process and outputs it as an I-video. On the other hand, when the output of the synthesizing circuit 109 is interlaced, the synthesized interlaced signal is output as an I-video, and the synthesized interlaced signal is converted by the I → P conversion circuit 101 by scanning line number conversion by scanning line interpolation. Perform progressive signal conversion and
Output as video.

[0006]

In the conventional circuit configuration, after generating graphics data and synthesizing it with an input video, if an I video is input, an I → P video output is applied.
Since P conversion is performed and P → I conversion is performed on the I video output when a P video is input, blurring of graphics video occurs due to conversion of the number of scanning lines or interpolation of the number of scanning lines in these conversion processes. Is deteriorated.

[0007]

According to the present invention, as a first invention, a P and I graphics image is input and a P image input or an I → P converted image is provided. In other words, the P graphics image is synthesized based on the P graphics synthesis control signal input, and the I graphics image is converted into the I graphics synthesis control signal for the I video input or the P → I converted video. Provided is a graphics display device capable of simultaneously outputting P and I graphics composite images without deteriorating image quality of graphics images by combining based on inputs.

According to a second aspect of the present invention, the graphics generation circuit generates P graphics signals (YSP, YMP, G).
P, RP, BP) and I graphic signals (YSI, Y
MI, GI, RI, and BI), half-brightness processing is performed on a P image input or I → P converted image based on YMP, and then GP, RP, and BP are synthesized based on the YSP signal, and I The video input or P → I converted video is subjected to half-brightness processing based on YMI, and then GI, RI, and BI are synthesized based on the YSI signal. Provided is a graphics display device capable of simultaneously outputting a graphics composite image.

According to a third aspect of the present invention, first, P graphics signals (YSP, YMP, GP, RP, BP) are generated, and the GP, RP, and BP signals are subjected to flicker removal. BP signal and YSP, YMP
Is converted to a graphic signal of I (YS
I, YMI, GI, RI, BI)
Provided is a graphics display device capable of simultaneously outputting a P and I graphics composite video without flickers without deteriorating the image quality of the P graphics video.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a graphics display circuit according to the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a graphics display circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 100 denotes an input terminal for an I video or a P video, 101 denotes an I → P conversion circuit for converting an I video to a P video, 102 denotes a P → I conversion circuit for converting a P video to an I video, and 103 denotes an input. Signal input from terminal 100 and I →
A switch for switching and outputting the output to and from the P conversion circuit 101. When the signal input to the input terminal 100 is a P video, the video signal of the input terminal 100 is output.
If the video input from 00 is an I video, I → P conversion circuit 1
The switches P and 104, which select and output the output of the P.I.
2 is a switch for switching and outputting the output. When the signal input to the input terminal 100 is an I video, the video of the input terminal 100 is output. When the input video from the input terminal 100 is a P video, P → A switch I for selecting and outputting the output of the I conversion circuit 102.

Reference numeral 123 denotes an I graphics input terminal for inputting an interlaced graphics signal, 121 denotes a P graphics input terminal for inputting a progressive graphics signal, and 120 denotes a terminal for synthesizing a progressive graphics signal and a P video. , A graphics synthesis control signal P input terminal 122 for controlling the synthesis of the interlaced graphics signal and the I video, and 124 a P
A synthesizing circuit C, 1 for synthesizing the graphics input and the output of the switch P based on the graphics synthesis control signal P input
05 is a P video output terminal for outputting the output of the synthesizing circuit C, 1
Reference numeral 25 denotes a combining circuit D for combining the I graphics input and the output of the switch I based on the graphics combining control signal I input, and 106 denotes an I video output terminal for outputting the output of the combining circuit D.

The operation of this device is as follows. When the video signal input from the input terminal 100 is a P video, the P-I conversion circuit 102 converts the I video generated by the scanning line number conversion process into the input P video. If the input video signal is an I video, the I → P conversion circuit 101 outputs a P video generated by scanning line number conversion by scanning line interpolation and the input I video.

In this embodiment, first, when the input signal is progressive with respect to the P video input or the I video input inputted from the I or P video input terminal 100,
This progressive signal is output from the switch P103, and this progressive signal is output to the P → I conversion circuit 10
In step 2, an interlace signal is converted by a scanning line number conversion process and output from a switch I104.

On the other hand, when the input signal is interlaced, this interlaced signal is output from the switch I104, and this interlaced signal is converted to an I → P conversion circuit 101.
Performs a progressive signal conversion by converting the number of scanning lines by scanning line interpolation, and outputs the result from the switch P103.

Next, the progressive graphics signal input from the P graphics input terminal 121 to the output of the switch P103 is synthesized by the synthesizing circuit C124 based on the graphics synthesizing control signal P, and is output from the P video output terminal 105. . Further, the interlaced graphics signal input from the I graphics input terminal 123 is combined with the output of the switch I104 by the combining circuit D125 based on the graphics combining control signal I, and is output from the I video output terminal 106.

As described above, in the first embodiment, since the graphics signal does not pass through the I-to-P conversion circuit 101 or the P-to-I conversion circuit 102, an interpolation operation for converting the number of scanning lines at the time of I-to-P conversion can be performed. No scanning line number conversion processing is performed at the time of P → I conversion, and no image quality degradation occurs in the graphics portion of the video output.

(Embodiment 2) FIG. 2 is a block diagram of a graphics display circuit according to Embodiment 2 of the present invention. 2, reference numeral 100 denotes an input terminal of an I video or a P video, 101 denotes an I → P conversion circuit for converting an I video to a P video, 102 denotes a P → I conversion circuit for converting a P video to an I video, and 103 denotes an input. Signal input from terminal 100 and I →
A switch for switching and outputting the output to and from the P conversion circuit 101. When the signal input to the input terminal 100 is a P video, the video signal of the input terminal 100 is output.
If the video input from 00 is an I video, I → P conversion circuit 1
The switches P and 104, which select and output the output of the P.I.
2 is a switch for switching and outputting the output. When the signal input to the input terminal 100 is an I video, the video of the input terminal 100 is output. When the input video from the input terminal 100 is a P video, P → A switch I for selecting and outputting the output of the I conversion circuit 102.

Reference numeral 110 denotes a progressive graphics signal (YSP, YMP, GP, RP, BP) and an interlaced graphics signal (YSI, YM).
I, GI, RI, BI), a graphics generation circuit 111 for performing half-luminance processing of the output of the switch P103 in accordance with the YMP of the output signal of the graphics generation circuit 110, The half-brightness processing circuits B and 113 which perform half-brightness processing on the output of the switch I102 in accordance with the YMP of the output signal of the graphics generation circuit 110 are output from the half-brightness processing circuit A111 and the output signals GP and RP of the graphics generation circuit 110, The synthesizing circuits A and 114 for synthesizing the BP with the output of the half-brightness processing circuit B 112 and the graphics generating circuit 110
A synthesizing circuit B for synthesizing GI, RI, and BI output signals according to YSI, a P video output terminal 105 for outputting a signal from the synthesizing circuit A 113, and an I video output terminal 106 for outputting a signal from the synthesizing circuit B 114 It is.

The operation of the graphics generation circuit 110 will be described in detail later (Embodiment 3) and will not be described here.

In this embodiment, first, (Embodiment 1)
In the same manner as above, graphics are synthesized after P → I conversion or I → P conversion, and then, for the P signal before graphics synthesis, the luminance value of the portion corresponding to the background of the subtitle signal is lowered to make the subtitle easier to read. Then, the half-brightness processing circuit A111 performs half-brightness processing, and the combining circuit A113 combines the progressive graphics signals GP, RP, and BP with the output of the half-brightness processing circuit A111 based on YSP, and outputs as a P video output. . The I signal before graphics synthesis is subjected to half-luminance processing in accordance with YMI by a half-luminance processing circuit B112, and the interlaced graphics signals GI, RI, and BI are processed by a synthesis circuit B114 based on YSI. And output as an I-video output.

[0022] With this configuration, even in the graphic display of a subtitle broadcast such as a terrestrial data broadcast, it is possible to view the video without deteriorating the image quality of the graphics.

(Embodiment 3) FIG. 3 is a block diagram of a graphics generation circuit of a graphics display circuit according to another embodiment of the present invention. In FIG. 2, 1 is a CPU, 2 is a frame memory, 3 is a line memory A, 4
Is a YS generation circuit, 5 is a YM generation circuit, 6 is a color map A, 7 is a switch A, 8 is an output terminal for outputting a progressive YS signal, 8 is an output terminal for outputting a progressive YS signal, and 10 is a progressive terminal. An output terminal for outputting a progressive G signal, an output terminal for outputting a progressive B signal, a frame memory 2 and a line memory A
The control circuits B and 14 for controlling the switches 3 and the switches are flickerless circuits.

Reference numeral 15 denotes a line memory B, 16 denotes an H pulse generation circuit P for generating a progressive H pulse, 17 denotes a control circuit C for controlling the line memory B15, 18 denotes a clock generation circuit, and 19 denotes an interlace H pulse. The H pulse generating circuits I and 20 that generate the
An output terminal for outputting an S signal, 21 is an interlaced Y
An output terminal for outputting an M signal, 22 is an output terminal for outputting an interlaced R signal, 23 is an output terminal for outputting an interlaced G signal, 24 is an output terminal for outputting an interlaced B signal, and 25 is V Input terminal for inputting pulse, 2
6 is an input terminal for inputting an interlaced H signal,
3 is an input terminal for inputting a progressive H pulse.
4 is a frequency dividing circuit for dividing a progressive H pulse.
0 is a switch B for switching between the output of the frequency divider circuit and the interlaced H-pulse input from the interlaced H-pulse input terminal 26, and 41 is an input terminal for a signal for controlling the switch B.

Hereinafter, a detailed description will be given with reference to FIGS. The CPU 1 writes graphics data into the frame memory 2. The graphics data written in the frame memo 2 is a progressive horizontal pulse (hereinafter, PLLH) generated by the H pulse generation circuit P16.
P) and a DMA_START pulse generated from the clock generated by the clock generation circuit 18
It is transferred to the line memory A3 during the “0” period of the MA_START pulse. FIG. 4 corresponds to A, B, C, D, E, and F. The transferred data is read out from the line memory A3 during the “1” period of the BRANKP generated by delaying the DMA_START by one horizontal period, and converted into color data by the color map A.
The display data of the P, GP, and BP signals is output. Note that B
Control signals such as LANKP and DMA_START are generated by the control circuit 13.

In FIG. 3, RGB_A, RGB_B, RGB
_C, RGB_D, RGB_E, and RGB_F. YMP and YM are generated by the YS generation circuit 4 and the YM generation circuit 5, respectively.
An SP is generated. The above is the progressive display operation. In the present invention, this progressive RP, GP, B
After P is flicker-reduced by the flickerless circuit 14, YS
Along with P and YMP, data is written to the line memory B15 while BLANK is "1". Writing to the line memory B15 is performed at a progressive rate.
Reading from 5 is performed at the interlace rate.

The read control signal from the line memory B15 is generated by the control circuit C17. The control circuit C17 generates BLANKI from the interlaced horizontal pulse (hereinafter, PLLHI) generated by the H pulse generation circuit I and the clock generated by the clock generation circuit 18, and generates BLAKI.
During the period when NKI is "1", data is read from the line memory B15 and interlaced output of YSI, YMI, RI, GI, and BI is performed. Further, in the present invention, the circuit is configured to divide the PH by the frequency dividing circuit 34 so that the interlace and the progressive graphic display can be performed simultaneously regardless of whether the PH is input from the outside or the IH is input.

As a simple configuration of the flickerless circuit, RGB_A data is delayed by a progressive one horizontal period delay line memory, and read from the line memory in synchronization with RGB_B transfer data (RGB_A + RGB_B).
B) / 2 may be performed.

In the present invention, the flickerless calculation is performed on progressive graphics, so that the flickerless calculation can be performed in frame units. With this configuration, for example, assuming that a frame is composed of black / white / black / white / black / white scanning lines, the frame configuration after flicker-less is black-gray-gray-gray-gray-white in the present invention, which has a flicker-less effect. If so, flickerless processing is performed for each of the two fields of black-black-black-black and white-white-white, so that even after the flicker-less processing, the fields have no change in the two fields of black-black-black-black and white-white-white and have no flickerless effect.

With the above circuit configuration, one progressive graphics generation circuit can simultaneously output interlaced and progressive graphic images.

[0031]

According to the graphics display circuit of the present invention, since the graphics synthesis is performed on the video after the P → I conversion or the I → P conversion, the image quality of the graphics section does not deteriorate. Also, since graphics generation is performed progressively, and interlace is performed by performing flickerless operation on P graphics data and then converting it to interlace using a memory, one graphics generation circuit is required. Can generate P and I graphics data.

[Brief description of the drawings]

FIG. 1 is a block diagram of a graphics display circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a graphics display circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a graphics generation circuit of a graphics display circuit according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of a graphics display circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram of an example of a conventional graphics display circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Frame memory 3 Line memory A 4 YS generation circuit 5 YM generation circuit 6 Color map A 8 YSP output terminal 9 YMP output terminal 10 RP output terminal 11 GP output terminal 12 BP output terminal 13 Control circuit B 14 Flickerless circuit 15 Line memory B 16 H pulse generation circuit P 17 Control circuit C 18 Clock generation circuit 19 H pulse generation circuit I 20 YSI output terminal 21 YMI output terminal 22 RI output terminal 23 GI output terminal 24 BI output terminal 25 V input terminal 26 IH input Terminal 33 PH input terminal 34 Divider circuit 35 Input terminal 40 Switch B 41 HSEL input terminal 100 I or P video input terminal 101 I → P conversion circuit 102 P → I conversion circuit 103 Switch P 104 Switch I 105 P video output terminal 106 I video output Terminal 107 Synthesis control signal input terminal 108 I or P graphics input terminal 110 Graphics generation circuit 111 Half-brightness processing circuit A 112 Half-brightness processing circuit B 113 Synthesis circuit A 114 Synthesis circuit B 120 Graphics synthesis control signal P input terminal 121 P graphics input terminal 122 graphics synthesis control signal I input terminal 123 I graphics input terminal 124 synthesis circuit C 125 synthesis circuit D

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 7/01 H04N 7/01 GF Term (Reference) 5C023 AA11 AA40 BA01 BA09 BA11 CA03 DA04 DA08 EA03 5C025 AA11 BA20 BA28 CA08 CB10 DA01 DA04 5C063 AA01 AB07 AC01 BA04 BA09 CA01 CA05 CA36 CA40 DA01 DA13 EA03 EB24 EB39 EB42 EB46 5C082 AA02 BA12 BA27 BA41 BB15 BC06 BC07 CA11 CA55 CA84 MM10

Claims (3)

[Claims] 1. An input terminal for inputting an interlaced video (hereinafter, referred to as an I video) or a progressive video (hereinafter, referred to as a P video), and an I → P for converting the input I video into a P video. A conversion circuit;
A switch P for switching a video and an output of the I → P conversion circuit between a P video and an I video, a P → I conversion circuit for converting the input P video to an I video, A switch I for switching between the I video and the output of the P → I conversion circuit between the P video and the I video, and an I for inputting an interlaced graphics signal.
A graphics input terminal, a P graphics input terminal for inputting a progressive graphics signal, a graphics synthesis control signal P input terminal for controlling the synthesis of the progressive graphics signal and the P video, and the interlacing. Graphics signals and I
A graphics synthesis control I-P input terminal for controlling when synthesizing video, a synthesis circuit C for synthesizing a P graphics input and the output of the switch P based on a graphics synthesis control signal P input, and the synthesis circuit A P video output terminal for outputting an output of C, a synthesizing circuit D for synthesizing an I graphics input and the output of the switch I based on a graphics synthesis control signal I input, and an I video for outputting the output of the synthesizing circuit D A graphics display circuit comprising an output terminal. 2. An input terminal for inputting an I image and a P image,
An I → P conversion circuit for converting an input I image into a P image, and a switch P for switching between the input I image and the output of the I → P conversion circuit depending on whether the input image is a P image or an I image.
A P-to-I conversion circuit for converting an input P-video into an I-video, and a switch I for switching between the input I-video and the output of the P-to-I conversion circuit depending on whether the input video is a P-video or an I-video. A YSI signal, a YSP signal, and a YMI signal, and a YMP signal, which control the amplitude of a luminance signal at the time of graphics synthesis, for controlling the synthesis switching when the graphics are synthesized with the P and I graphics images, the I images, and the P images. A semi-brightness processing circuit A that performs a luminance / amplitude conversion process on the output of the I → P conversion circuit from a YMP signal output from the graphics generation circuit, and a P → I conversion circuit. Y which is the output of the graphics generation circuit
A half-brightness processing circuit B that performs brightness-amplitude conversion processing based on the MI signal, a synthesis circuit A that synthesizes the output of the half-brightness processing circuit A and the graphics video of P from the YSP signal output from the graphics generation circuit, A synthesizing circuit B for synthesizing the output of the half-brightness processing circuit B and the graphics image of I with the YSI signal output from the graphics generating circuit
A graphics display circuit comprising: a P video output terminal for outputting an output of the synthesis circuit A; and an I video output terminal for outputting an output of the synthesis circuit B. 3. A frame memory, and a CPU for writing graphics data to the frame memory in a frame configuration.
And a line memory A used to convert data read from the frame memory into data of a clock rate for progressive display, and Y from the output of the line memory A
A YS generation circuit for generating an SP, a YM signal generation circuit for generating a YMP from the output of the line memory A, a YSP output terminal for outputting the YSP, a YMP output terminal for outputting the YMP, and a progressive output for the line memory A A color map A for converting color data of an R signal, a progressive G signal, and a progressive B signal; an RP output terminal for outputting a progressive R signal (hereinafter, referred to as RP); and a progressive G signal (hereinafter, referred to as RP). A GP output terminal for outputting a progressive B signal (hereinafter referred to as BP), and a R output terminal for outputting a progressive B signal (hereinafter referred to as BP).
A flickerless circuit that inputs P, GP, and BP and removes flicker when converting RP, GP, and BP to an interlace signal, and outputs the progressive rate flickerless circuit and YSP and YMP at the interlace rate. A line memory B for converting the data into data (RI, GI, BI, YSI, YMI), and a YSI output from the line memory B
, An YMI output terminal for outputting the YMI output from the line memory B, an RI output terminal for outputting the RI output from the line memory B, and a GI output for the line memory B. A GI output terminal for
A BI output terminal for outputting BI which is an output of the line memory B, a PH input terminal for inputting a progressive horizontal synchronization signal (hereinafter, referred to as PH), and an interlace horizontal synchronization signal (hereinafter, referred to as IH). An input IH input terminal, a frequency divider for dividing PH so as to have the same cycle as IH, and a switch B for switching the output of the frequency divider and IH
And a switch B control signal (hereinafter, referred to as a switch B control signal) for controlling the switch B.
HSEL input terminal for inputting an HSEL), an output signal of the switch B (hereinafter, referred to as SH) and a P, which will be described later.
A progressive graphic display clock generation circuit for generating a clock so that edges with the LLH meet;
An H pulse generation circuit I that generates an interlaced horizontal synchronization pulse (hereinafter, referred to as PLLH) from a clock generated by the clock generation circuit, and a progressive horizontal synchronization pulse (hereinafter, PLLH2) generated from a clock generated by the clock generation circuit. H), and an H pulse generating circuit P for generating a vertical synchronizing signal (hereinafter, referred to as V).
A pulse input terminal, a control circuit B for controlling a line memory A, a frame memory, and a control circuit C described later based on V, PLLH2, and an output of the clock generation circuit; a control circuit C for the control circuit B; 3. The graphics generation circuit for a graphics display circuit according to claim 2, further comprising a control circuit C for controlling the line memory B based on a clock generated by the clock generation circuit.