JP2000115283A - Serial communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide clock synchronous serial communication equipment that can conduct serial communication with a minimum number of signal lines and be restored to a normal state even when the communication hangs up. SOLUTION: The equipment where clock synchronous serial communication with a prescribed data number is conducted between a 1st device and a 2nd device is provided with a means that transmits clocks of a prescribed data number from the 1st device 1, a transmission means that sequentially transmits data synchronously with the clock from the 1st device, a reception means of the 2nd device 2 that receives the data synchronously with the clock, an initializing instruction means that transmits clocks whose number if more than the prescribed data number from the 1st device 1, and a means that uses the initializing instruction means to initialize communication by the 2nd device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronous serial communication device for sequentially transmitting and receiving data in synchronization with a clock.

[0002]

2. Description of the Related Art Conventionally, clock synchronous serial communication has been disclosed in Japanese Patent Application Laid-Open No. Hei 6-243052.
A handshake signal line is provided in addition to the clock signal line and the data signal line, so that when an error occurs in communication, recovery can be performed using the handshake signal line.

[0003]

However, in the above conventional example, a signal line for handshaking is required in addition to a clock signal line and a data signal line required for clock synchronous serial communication.

The present invention has been made in view of the above points, and provides a clock synchronous serial communication device capable of performing serial communication with a minimum number of signal lines and returning to a normal state even if communication hangs up. The purpose is to:

[0005]

In order to achieve the above object, a serial communication device according to the first aspect of the present invention comprises a first device and a second device which perform clock synchronization of a predetermined number of data. In a device that performs serial communication, means for transmitting a clock for a predetermined number of data from the first device,
Transmitting means for sequentially transmitting data from the first device in synchronization with the clock; receiving means for receiving the data in synchronization with the clock in the second device; An initialization instructing unit for transmitting a clock larger than the number of data, and a unit for initializing communication of the second device by the initialization instructing unit are provided.

[0006]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is an overall configuration diagram showing a first embodiment of a serial communication device according to the present invention.

In FIG. 1, reference numeral 1 denotes an apparatus which is a master side of serial communication as a first apparatus, 2 denotes an apparatus which is a slave side of serial communication as a second apparatus, and 3 denotes an apparatus 1
4 is a bidirectional data signal line for transmitting and receiving data in synchronization with the clock signal, 5 is a microcomputer for controlling the device 1, 6 is an output port of the microcomputer 5, and 6 is an output port of the microcomputer 5. An SO output terminal for outputting data in synchronization, 7 is an input port of the microcomputer 5 and an SI input terminal for inputting data in synchronization with a clock signal, 8 is a transistor used as an open collector, and the base is an SO output terminal. To terminal 6,
When the collector is connected to the data signal line 4 and the SO output terminal 6 is at a high (hereinafter referred to as “H”) level, the transistor 8 is turned on to bring the data signal line 4 to an L level,
When the SO output terminal 6 is at a low (hereinafter “L”) level, the transistor 8 is turned off and the data signal line 4 is connected to the resistor 9.
Becomes H level because it is pulled up.

Reference numeral 10 denotes a microcomputer for controlling the device 2, and reference numeral 11 denotes data at the SI input terminal 13 every time the clock signal input to the CK terminal 12 rises, sequentially shifts internal latch data, and The microcomputer 10 is an 8-bit shift register that outputs the output of the latch to the SO terminal 14.
When the / W terminal 15 is set to L level, the data is output to the DATA bus terminal 16 and input to the microcomputer 10.

The microcomputer 10 has an R /
By setting the W terminal 15 to H level, setting the transmission data to the DATA bus terminal 16 and setting the LD terminal 17 to L level, data can be input to each latch of the shift register 11.

Reference numeral 18 denotes a counter for counting from 0 to 8, and the count value is increased by +1 at the rise of the clock signal 3.
The microcomputer 10 counts the count value 19
Can be read, and the count value can be returned to 0 by setting the CLR terminal 20 to the L level.

Reference numeral 21 denotes an EX-OR circuit. The microcomputer 10 outputs an inverted signal of the clock signal 3 to the CK terminal 12 by setting the MD terminal 22 to the H level.
By setting the D terminal 22 to the L level, the clock signal 3 is output to the CK terminal 12 as it is.

Reference numeral 23 denotes a D flip-flop. Since the D terminal is pulled up, the Q terminal 24 goes high at the rising edge of the CK terminal 12, and the microcomputer 10 turns the RXS terminal 25 high. The D flip-flop 23 is reset and the Q terminal 24 is L
Become a level.

26 is a NAND circuit, 27 is a transistor used as an open collector, and the base is a NAND circuit.
When the collector of the circuit 26 is connected to the data signal line 4 and the output of the NAND circuit 26 is at the H level,
When the transistor 27 is turned on to set the data signal line 4 to the L level and the output of the NAND circuit 26 is at the L level, the transistor 27 is turned off and the data signal line 4 is pulled up by the resistor 28 to the H level. Become.

Reference numeral 29 denotes a counter for counting from 0 to 24, and the count value is increased by + at the rise of the clock signal 3.
The microcomputer 10 counts the count value 3
1 can be read, and the count value can be returned to 0 by setting the CLR terminal 30 to L level.

In the above configuration, the microcomputer 5 operates so that the first device 1 sends a clock signal to the second device 2 in accordance with the number of data for transmission or reception, by sending a clock, The microcomputer 10 operates to receive the data of the data signal sequentially or transmit the data to the data signal sequentially using the shift register 11 in synchronization with the clock signal transmitted by the first device 1. Is that the first device 1 sends out a sufficiently large number of clock signals with respect to the number of data,
It operates to instruct the second device 2 to initialize communication. When the microcomputer 10 recognizes that the initialization has been instructed from the first device 1 by the initialization instructing means,
It operates so that the communication of the second device 2 is initialized.

The operation of the circuit will be described below with reference to FIGS.

FIG. 2 is a timing chart according to the first embodiment of the present invention, FIGS. 3 and 4 are flowcharts according to the first embodiment of the present invention, and FIG. 5 is a timing chart according to the first embodiment of the present invention. 6 is a flowchart according to the embodiment.

FIG. 2 is a timing chart when one cycle of transmission / reception is performed normally, and FIGS.
FIG. 5 is a communication control flowchart of the device 2.

A communication operation in which command data is transmitted from the device 1 to the device 2 and the device 1 receives status data from the device 2 will be described with reference to FIGS.

First, the operation of the first apparatus 1 will be described with reference to FIGS.

In step S301, command data transmitted by the microcomputer 5 is set in a transmission register which is a built-in 8-bit general-purpose register used for transmission. In step S302, 1 is set to a built-in general-purpose register (loop register) that stores the number of loops. In step S303, the CK terminal 3 is set to L level. In step S304, it is determined whether the data of the 8th bit at the bit position of the transmission register is 0 or 1. If the 8th bit is 0, the process proceeds to step 305. If the 8th bit is 1, the process proceeds to step S306. In step S305,
By setting the SO terminal 6 to the H level, the DATA signal line 4
To L level. In step S306, the SO terminal 6
Is set to L level, so that the DATA signal line 4 is set to H level. In step S307, the CK terminal 3 is set to the H level. In step S308, the value of the loop register is determined. If the number of loops is other than 8, the process proceeds to step S309, and if the number of loops is 8, the process proceeds to step S311.
In step S309, 1 is added to the value of the loop register. In step S310, the data of the transmission register is shifted to the left by one bit (the data of the seventh bit is moved to the eighth bit, the data of the sixth bit is moved to the seventh bit, and so on. (Data is set to 0)
Then, the process returns to step S303.

In step S311, since transmission of the 8-bit command data has been completed, the SO terminal 6 is set to the L level, and the DATA signal line 4 is set to the H level to set the DA signal.
The TA signal line 4 is opened to the device 2. In step S312, it is monitored whether or not the SI terminal 7 is at the L level.
Goes to the L level, the flow shifts to step S313 to start receiving the status. In step S313, 1 is set in the loop register. In step S314,
The CK terminal 3 is set to L level. In step S315,
The CK terminal 3 is set to the H level. In step S316,
The level of the SI terminal 7 is determined. If the SI terminal 7 is at the H level, the process proceeds to step S317. If the SI terminal 7 is at the L level, the process proceeds to step S318. In step S317, the microcomputer 5 sets 1 to the first bit of a reception register which is a built-in 8-bit general-purpose register used for receiving status data. In step S318, 0 is set to the first bit of the reception register.

In step S319, the value of the loop register is determined, and if the number of loops is not 8, step S32
The process proceeds to 0, and if the number of loops is 8, the process proceeds to step S322. In step S320, 1 is added to the value of the loop register. In step S321, the data in the reception register is shifted left by one bit, and the process returns to step S314.
In step S322, since the reception of the 8-bit status data has been completed, the data of the reception register is stored in another register, the communication for one cycle of the command / status data is completed, and the process returns to step S301.

Next, the operation of the apparatus 2 will be described with reference to FIG.

In step S401, the microcomputer 10 sets the count value of the counter 18 to 0 by setting the CLR terminal 20 to the L level for a predetermined period. In step S402, the RXS terminal 25 is set to L level,
The A signal line 4 is used by the device 1. In step S403, data 0 is set in the shift register 11 (the R / W terminal 15 is set to the H level,
6, the LD terminal 17 is set to L level to set each latch of the shift register 11 to 0), so that the SO terminal 14 is set to L level, the DATA signal line 4 is set to H level, and DATA is set. The signal line 4 is opened to the device 1.
Further, by setting the MD terminal 22 to the L level, the reception mode is set in which the clock signal line 3 is used as it is. In step S404, the count value of the counter 18 is monitored,
When the count value reaches 8, the process proceeds to step S405.

In step S405, since the reception of the 8-bit command data has been completed, the data bus terminal 16
Is stored in the built-in command register. In step S406, the contents of the command register are analyzed, and the process specified by the command is executed. Step S
At 407, the count value of the counter 18 is set to 0 by setting the CLR terminal 20 to the L level for a predetermined period. In step S408, in order to set status data in the shift register 11, the R / W terminal 15 is set to H level,
Status data is input to the ATA bus terminal 16 and LD
By setting the terminal 17 to L level, status data is set in each latch of the shift register 11.

In step S409, the LD terminal 17 is set to H level.
By returning the R / W terminal 15 to the L level and setting the MD terminal 22 to the H level, the clock signal line 3 is inverted and set to the transmission mode for use, and the RXS terminal 25 is set to the H level for a predetermined period. To set the DATA signal line 4 to the L level to notify the device 1 that the transmission preparation is completed. In step S410, the count value of the counter 18 is monitored, and when the count value reaches 8, the transmission ends, and the process returns to step S403.

FIG. 6 is a timing chart according to the first embodiment of the present invention, FIG. 7 is a flowchart according to the first embodiment of the present invention, and FIG. 8 is a flowchart according to the first embodiment of the present invention. It is a flowchart concerning a form.

FIG. 6 is a timing chart when the device 1 is instructing the device 2 to initialize communication. FIG. 7 is a flowchart for controlling the initialization of the device 1, and FIG. It is a flowchart.

The operation of the apparatus 2 for initializing communication in response to an initialization instruction from the apparatus 1 will be described with reference to FIGS.

First, an initialization instruction operation of the device 1 will be described with reference to FIG.

In step S601, the data terminal line 4 is set to L level by setting the SO terminal 6 to H level. In step S602, the microcomputer 5
Sets 1 in a built-in general-purpose register (second loop register) that stores the number of loops. In step S603, the CK terminal 3 is set to L level. In step S604, the CK terminal 3 is set to the H level. In step S605, the value of the second loop register is determined, and the number of loops is 2
If it is other than 4, the process proceeds to step S606, and the number of loops is 2
If it is 4, the process returns to step S603. In step S606, 1 is added to the value of the loop register, and in step S60
Return to 3. In step S607, the DATA signal line 4 is set to the H level by setting the SO terminal 6 to the L level.
In step S608, the communication process described with reference to FIGS. 3 and 4 is stopped, and after waiting for a predetermined time, communication is restarted from step S301.

Next, the communication initialization operation of the device 2 will be described with reference to FIG.

In step S701, it is monitored whether the SI terminal 7 is at the L level. When the SI terminal 7 is at the H level, the process proceeds to step S702, and when the SI terminal 7 is at the L level, the process proceeds to step S703. Step S702
Then, it is determined that the instruction is not an initialization instruction, and the value of the counter 29 is set to 0 by setting the CLR terminal 30 to the L level for a predetermined period. In step S703, the count value of the counter 29 is monitored.
01 and if the count value is 24, the process proceeds to step S7.
Move to 04. In step S704, it is determined that the device 1 has instructed communication initialization, the communication process described with reference to FIG. 5 is stopped, and after waiting for a predetermined time, communication is restarted from step S401.

As described above, when there is an abnormality in communication, the device 1 fixes the DATA signal to the L level to the device 2 and sends out more clocks than usual,
Since communication initialization can be performed, serial communication can be performed using two clock signal lines 3 and data signal lines 4.

(Second Embodiment) A second embodiment of the serial communication device according to the present invention has a configuration in which the counter 29 is eliminated from the device 2 shown in FIG. 1, and the description is omitted. In FIG. 1, the communication control of the device 1 is the same as that of the first embodiment, and the description thereof is omitted.

FIG. 9 is a timing chart according to a second embodiment of the serial communication apparatus according to the present invention.
0 is a flowchart according to the second embodiment of the present invention, and FIG. 11 is a flowchart according to the second embodiment of the present invention.

FIG. 9 is a timing chart when the device 1 instructs the device 2 to initialize communication.
FIG. 11 is a flowchart of an initialization instruction control of the apparatus 1;
5 is a communication control flowchart of the device 2.

The operation of the apparatus 2 for initializing communication in response to an initialization instruction from the apparatus 1 will be described with reference to FIGS.

First, the initialization instruction operation of the device 1 will be described with reference to the flowchart of FIG.

In step S901, the DATA signal line 4 is released by setting the SO terminal 6 to the L level. In step S902, the microcomputer 5 sets a built-in general-purpose register (second loop register) for storing the number of loops to one. In step S903, the CK terminal 3 is set to L level. In step S904, the CK terminal 3 is set to the H level. In step S905, the value of the second loop register is determined. If the number of loops is other than 24, the process proceeds to step S906, and if the number of loops is 24, the process proceeds to step S907. In step S906, 1 is added to the value of the loop register, and the process returns to step S903.
In step S907, the communication processing described in the first embodiment with reference to FIGS. 3 and 4 is stopped, and the processing is restarted from step S301.

Next, the communication control and communication initialization operation of the device 2 will be described with reference to the flowchart of FIG.

In step S101, the microcomputer 10 sets the count value of the counter 18 to 0 by setting the CLR terminal 20 to the L level for a predetermined period. In step S102, the RXS terminal 25 is set to L level,
The A signal line 4 can be used in the device 1. In step S103, data 0 is set in the shift register 11 (the R / W terminal 15 is set to the H level, and the DATA bus terminal 1 is set).
6, the LD terminal 17 is set to L level to set each latch of the shift register 11 to 0), so that the SO terminal 14 is set to L level, the DATA signal line 4 is set to H level, and DATA is set. The signal line 4 is opened to the device 1.
Further, by setting the MD terminal 22 to the L level, the reception mode is set in which the clock signal line 3 is used as it is.

In step S104, the count value of the counter 18 is monitored, and when the count value reaches 8, the process proceeds to step S105. In step S105, since the reception of the 8-bit command data is completed, the data of the DATA bus terminal 16 is stored in the built-in command register.
In step S106, the content of the command register is F
If it is Fh, it is determined that the communication is to be initialized, and step 11 is performed.
The process returns to step S101 after waiting for a predetermined time, and if the contents of the command register are other than FFh, the process proceeds to step S107.

In step S107, the contents of the command register are analyzed, and the processing specified by the command is executed. In step S108, the count value of the counter 18 is set to 0 by setting the CLR terminal 20 to the L level for a predetermined period. In step S109, the R / W terminal 15 is set to the H level to set the status data in the shift register 11.
Level, status data is input to the DATA bus terminal 16, and the LD terminal 17 is set to L level, thereby setting the status data in each latch of the shift register 11. In step S110, the LD terminal 17 is returned to the H level, the R / W terminal 15 is returned to the L level, and the MD terminal 22 is set to the H level, thereby setting the transmission mode in which the clock signal line 3 is inverted and used, and the RXS terminal is used. By setting 25 to the H level for a predetermined period, the DATA signal line 4 is set to the L level to notify the device 1 that the transmission preparation is completed. Step S
At 111, the count value of the counter 18 is monitored, and when the count value reaches 7, the transmission is terminated.
Return to 03.

As described above, when there is an abnormality in the communication, the device 1 sends a clock three times or more the normal frequency while leaving the DATA signal open to the device 2,
The apparatus 2 always receives the FFh data, and initializes the communication when the data is FFh, so that the communication can be initialized without providing a counter for counting the clock for the initialization. I can do it.

[0048]

As described above, according to the serial communication device of the first aspect, a hang can be achieved by setting a sufficiently large number of clocks for the number of data of one transmission / reception as the communication initialization instruction. It is possible to recover from the up state, and to perform serial communication with the minimum necessary number of signal lines.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing a first embodiment of a serial communication device according to the present invention.

FIG. 2 is a timing chart according to the first embodiment of the present invention.

FIG. 3 is a flowchart according to the first embodiment of the present invention.

FIG. 4 is a flowchart continued from FIG. 3;

FIG. 5 is a flowchart according to the first embodiment of the present invention.

FIG. 6 is a timing chart according to the first embodiment of the present invention.

FIG. 7 is a flowchart according to the first embodiment of the present invention.

FIG. 8 is a flowchart according to the first embodiment of the present invention.

FIG. 9 is a timing chart according to a second embodiment of the serial communication device according to the present invention.

FIG. 10 is a flowchart according to a second embodiment of the present invention.

FIG. 11 is a flowchart according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 device 1 (first device) 2 device 2 (second device) 3 clock signal line 4 data signal line 5, 10 microcomputer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Koichi Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term within Canon Inc. (reference) 5B083 AA00 BB03 CD00 CE01 DD13 GG04 5K034 AA05 AA12 CC01 DD01 FF01 HH01 HH02 HH09 HH12 LL03 PP01 5K035 AA05 DD01 FF01 FF02

Claims (1)

[Claims] An apparatus for performing clock synchronous serial communication of a predetermined number of data between a first apparatus and a second apparatus, comprising: means for transmitting a clock of a predetermined number of data from the first apparatus; Transmitting means for sequentially transmitting data from the first device in synchronization with the clock; receiving means for receiving the data in synchronization with the clock in the second device; A serial communication device comprising: an initialization instruction unit for transmitting a clock having a number of data larger than the number of data; and a unit for initializing communication of the second device by the initialization instruction unit.