JP4604956B2 - Information processing device - Google Patents

Description

  The present invention relates to an information processing apparatus including an operation panel.

  Some recent multi-function printers (multifunction printers) adopt a configuration as schematically shown in FIG. 7 or FIG. 8, that is, command / data exchange between the operation panel and the controller. There are devices that employ a configuration that is performed by serial communication. Note that an operation panel (an operation panel on which a CPU is mounted) provided in the multifunction peripheral shown in FIG. 7 is called an intelligent operation panel. In addition, the operation panel provided in the multifunction peripheral shown in FIG. 8 is called a non-intelligent operation panel (for example, see Patent Document 1). The serial interface circuit (“serial I / F circuit”) in this type of operation panel has a higher function than the serial interface circuit in the intelligent operation panel.

  The above configuration is adopted because the number of signal lines between the operation panel and the controller can be reduced. However, when this configuration is adopted, the firmware for the controller has a large size. As a result, there arises a problem that it becomes difficult to create firmware.

  This is because when the configuration shown in FIG. 7 or FIG. 8 is adopted, various devices in the operation panel [LCD, a plurality of LEDs (“LEDs”), a plurality of push button switches (“SWs”) )] Must be accessed via a single serial interface circuit, the controller firmware can be controlled by, for example, an LED control module [ON / OFF of various LEDs as schematically shown in FIG. Program for performing control], LCD control module [program for displaying image on LCD], SW control module [program for detecting the state (ON / OFF) of various pushbutton switches] Only the module has a serial I / F command control module [controls the serial interface circuit Because you must be created as including an exclusive control module to utilize the program].

JP-A-9-224109

  Accordingly, an object of the present invention is an information processing apparatus (an information processing apparatus in which command / data exchange between the operation panel and the control unit is performed by serial communication) such as the above-described multifunction peripheral, and the size of the firmware It is an object of the present invention to provide an information processing apparatus having a configuration capable of reducing the size of the firmware and a configuration capable of facilitating the creation of firmware.

In order to solve the above problems, an information processing apparatus of the present invention includes an operation panel and a control unit,
The operation panel performs serial communication between the LCD, a plurality of switches, a plurality of LEDs, and the control unit, thereby receiving image data to be supplied to the LCD, each of the plurality of LEDs And a serial communication circuit that executes processing for receiving LED control data indicating a state to be taken or processing for transmitting switch state data indicating the states of the plurality of switches, and the control unit The image data transmission process for transmitting the image data to the serial communication circuit by performing serial communication between the CPU and the serial communication circuit, and the LED control data for transmitting the LED control data to the serial circuit Data transmission processing or switch status data for receiving the switch status data from the serial communication circuit An operation panel communication circuit that executes communication processing, and the operation panel communication circuit performs serial communication with the serial communication circuit in the operation panel, and the CPU The LED control data register in which the LED control data is written, and the LED circuit that repeatedly performs the process of transmitting the LED control data set in the LED control data register to the serial circuit; and A switch status data register accessible by the CPU for storing switch status data is provided, and a switch that periodically receives the switch status data from the serial communication circuit and stores it in the switch status data register Circuit and supplied image data to the LCD An LCD circuit that outputs as a kimono, and an arbitration circuit that uses the operation unit side serial communication circuit for any one of the LED circuit, the SW circuit, and the LCD circuit. The CPU provides new image data to the LCD circuit at an arbitrary timing, sets new LED control data to the LED control data register at an arbitrary timing, and receives the switch state data. The switch state data received by the processing is obtained from the switch state data register at an arbitrary timing .

That is, the information processing apparatus according to the present invention allows the CPU to be connected to each circuit on the operation panel communication circuit at any timing (whatever processing is performed between the operation panel and the operation panel communication circuit). It has a configuration capable of supplying data and setting control data . If the CPU can supply data to each circuit on the operation panel communication circuit or set control data at an arbitrary timing, a program equivalent to the exclusive control module (see FIG. 9) is created. of that of the there is no need to, will be able to create a firmware easily. In addition, the size of the firmware to be created is reduced because it is not necessary to create a program corresponding to the exclusive control module. Therefore, it can be said that the information processing apparatus according to the present invention is an apparatus having a configuration capable of reducing firmware and facilitating firmware creation.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  First, the outline of the information processing apparatus 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

  As shown in FIG. 1, the information processing apparatus 10 according to an embodiment of the present invention is an apparatus (so-called multifunction machine) including a scanner unit 20 and a printer unit 30 provided with an operation panel 21.

  As shown in FIG. 2, the operation panel 21 provided in the scanner unit 20 includes a plurality of LEDs (“LEDs”), an LCD, a plurality of push button switches (“SWs”), and a serial interface circuit (“serial”). I / F circuit ") 25. In addition to the operation panel 21 having such a configuration, the scanner unit 20 includes a lamp, a sensor (document cover / ADF opening / closing detection sensor), a motor, a CCD, an AFE (analog front end), and an interface circuit. (“I / F”) and the like.

  The printer unit 30 (FIG. 2) is a unit that includes a controller 31 and a print engine 32.

  The print engine 32 included in the printer unit 30 is a unit for printing on paper.

  The controller 31 is a unit for causing the information processing apparatus 10 to function as a multifunction machine (copy machine, network printer, network scanner, etc.). As shown in the figure, the controller 31 includes a scanner interface circuit, an engine interface circuit, a PC interface circuit, a CPU 40, a ROM, a RAM, a network interface circuit, and an image processing. The unit includes a circuit, an LED interface circuit 41, an LCD interface circuit 42, an SW interface circuit 43, an arbitration circuit 44, a serial interface circuit 45, and the like.

  The scanner interface circuit, the engine interface circuit, the PC interface circuit, the CPU 40, the ROM, the RAM, the network interface circuit, and the image processing circuit are all the same as the circuits with the same names / similar names used in the existing printer controllers. is there.

  The LED interface circuit 41, the LCD interface circuit 42, the SW interface circuit 43, the arbitration circuit 44, and the serial interface circuit 45 are provided in the controller 31 so that the CPU 40 can control (use) the operation panel 21. Circuit (details will be described later).

  The information processing apparatus 10 according to this embodiment includes three signal lines (CLK signal lines) each having a length of about 1 m between the operation panel 21 (serial interface circuit 25) and the controller 31 (serial interface circuit 45). , TXDATA signal line and RXDATA signal line).

  Based on the above, the configuration and operation of the information processing apparatus 10 according to the present embodiment will be described more specifically below.

  The serial interface circuit 25 (FIG. 2) in the operation panel 21 receives data (commands) transmitted from the serial interface circuit 45 in the controller 31 through the TXDATA signal line in synchronization with the clock signal supplied through the CLK signal line. / Data) and a process for transmitting data on the RXDATA signal line.

  The serial interface circuit 25 is a circuit having the following functions.

  When an LED write command (1-byte command: details will be described later) is transmitted from the serial interface circuit 45, the serial interface circuit 25 transmits each bit after that, and each bit is in a specific LED state (ON / OFF) is controlled on the operation panel 21 in accordance with 64-bit data (data including bits in which the corresponding LED does not actually exist; hereinafter referred to as LED control data). For various LEDs.

  The serial interface circuit 25 detects the state of various push button switches on the operation panel 21 when an SW read command (1-byte command: details will be described later) is transmitted from the serial interface circuit 45. Then, based on the detection result, the serial interface circuit 25 uses 64-bit data in which each bit indicates the state of a specific switch (data including a bit for which no corresponding switch actually exists; , Expressed as SW state data) and transmitted to the serial interface circuit 45.

  Further, when an LCD write command (1-byte command: details will be described later) is transmitted from the serial interface circuit 45, the serial interface circuit 25 displays an image based on data (image data) transmitted thereafter. The processing for causing the LCD to perform is performed.

  The serial interface circuit 45 converts the command / data from the arbitration circuit 44 (command / data from the interface circuits 41 to 43; details will be described later) into serial data and transmits the serial data to the serial interface circuit 25. This is a circuit that receives serial data transmitted from, converts it into parallel data, and supplies (transmits) it to the arbitration circuit 44.

  As shown in FIG. 3, the serial interface circuit 45 is a circuit that changes the frequency of an output clock according to the type of command given from the arbitration circuit 44.

  Specifically, when the command given from the arbitration circuit 44 is an SW read command (FIG. 3B), the serial interface circuit 45 has a high-frequency (10 MHz in this embodiment) clock. A circuit that outputs a signal and outputs a low-frequency (1 MHz in this embodiment) clock signal when the command from the arbitration circuit 44 is an LCD write command or an LED write command (FIG. 3A). It has become.

  The arbitration circuit 44 (FIG. 2) is a circuit (interface circuit that has transmitted a command) that causes the interface circuit (the LED interface circuit 41, the LCD interface circuit 42, or the SW interface circuit 43) that has transmitted a command to use the serial interface circuit 45. And a serial interface circuit 45).

  When the arbitration circuit 44 receives the SW read command / LED write command while the LED interface circuit 41, the LCD interface circuit 42 or the SW interface circuit 43 is using the serial interface circuit 45, the arbitration circuit 44 receives the command. (And data transmitted thereafter) are ignored. Further, the arbitration circuit 44 uses the LED interface circuit 41 or the SW interface circuit 43 when receiving the LCD write command while the LED interface circuit 41 or the SW interface circuit 43 is using the serial interface circuit 45. When the use of the serial interface circuit 45 is completed, the LCD interface circuit 42 causes the serial interface circuit 45 to be used.

  The arbitration circuit 44 and the LED interface circuit 41 (see FIG. 2) connected to the system bus are, as schematically shown in FIG. 4, a command register 51, a data register 52, a period register 53, and a transmission control circuit 54. And a circuit provided with a timer 55.

  The command register 51 included in the LED interface circuit 41 is a 1-byte register into which the LED write command is written by the CPU 40.

  When it is necessary to change the state of some LEDs on the operation panel 21, the data register 52 is controlled by the CPU 40 by the above-described LED control data (64 LEDs including LEDs not existing on the operation panel 21). This is an 8-byte register in which data for designating the state is written.

  The cycle register 53 is a register in which a cycle [data indicating time (for example, 20 ms)] is written by the CPU 40. The timer 55 is a circuit that repeats the process of outputting a trigger signal to the transmission control circuit 54 at the period set in the period register 53.

  When an LED write command is written in the command register 51, the transmission control circuit 54 receives information (1) set in the command register 51 and the data register 52 each time a trigger signal is input from the timer 45. This is a circuit that operates in a state in which a byte command and 8-byte data) are transmitted to the arbitration circuit 44. The transmission control circuit 54 is a circuit that does nothing when the LED write command is not written in the command register 51.

  The arbitration circuit 44 and the SW interface circuit 43 (see FIG. 2) connected to the system bus are, as schematically shown in FIG. 5, a command register 61, a data register 62, a period register 63, and a reception control circuit 64. And a circuit provided with a timer 65.

  The command register 61 is a 1-byte register in which the above-described SW read command is written by the CPU 40.

  The data register 62 is an 8-byte register for storing SW state data from the serial interface circuit 25 (64-bit data indicating the states of 64 SWs including SWs not existing on the operation panel 21). is there.

  The cycle register 63 is a register in which a cycle [data indicating time (for example, 20 ms)] is written by the CPU 40, and the timer 65 is a cycle set in the cycle register 63 with respect to the reception control circuit 64. This circuit outputs a trigger signal.

  When the SW read command is set in the command register 61, the reception control circuit 64 receives the command (SW read command) set in the command register 51 every time a trigger signal is input from the timer 65. This is a circuit that operates in a state in which the data transmitted to the arbitration circuit 44 and the data transmitted by the arbitration circuit 44 as a response thereto are stored in the data register 62. The reception control circuit 64 is a circuit that does nothing (does not rewrite the contents of the data register 62) when there is no response to the transmitted SW read command. Further, like the transmission control circuit 54, the reception control circuit 64 is a circuit that does nothing when the SW read command is not set in the command register 61.

  When an LCD write command is given, the LCD interface circuit 42 is a circuit that transmits the LCD write command to the arbitration circuit 44 and then transfers the image data supplied to the own circuit to the arbitration circuit 44. is there.

  In short, a circuit (LED write command, SW read command, etc.) that includes the LED interface circuit 41, LCD interface circuit 42, SW interface circuit 43, arbitration circuit 44, and serial interface circuit 45 provided in the information processing apparatus 10 is set. (Hereinafter referred to as an operation panel communication circuit) is connected to the operation panel 21 (serial interface circuit 25) in any state in which the LED interface is used. When LED control data is set in the data register 51 in the circuit 41, the state of each LED on the operation panel 21 is controlled to the state indicated by the LED control data. In addition, the operation panel communication circuit can read the contents of the data register 61 in the SW interface circuit 43 regardless of what processing is being performed with the operation panel 21 (on the operation panel 21). The CPU 40 can grasp the state of each SW.

  Further, the operation panel communication circuit can provide any data to the LCD interface circuit 42 after giving an LCD write command to the LCD interface circuit 42 in any state with the operation panel 21. In this circuit, an image corresponding to the image data is displayed on the LCD on the operation panel 21.

  For this reason, the information processing apparatus 10 according to the present embodiment determines whether or not other types of elements are being controlled when a certain type of element (LED, LCD, or SW) on the operation panel 21 is controlled. An apparatus configured by storing firmware that is not checked at all (in this embodiment, equivalent to that not including the exclusive control module and the serial I / F command control module in FIG. 9) in the ROM in the controller 31; It has become.

<Deformation>
The information processing apparatus 10 described above can perform various modifications. For example, in place of the serial interface circuits 25 and 45, a 4-wire set of serial interface circuits (a set of interface circuits connected by TXCLK, TXDATA, RXCLK, and RXDATA signal lines) is used. The device 10 can be modified.

  In addition, when higher speed data transfer is required (when the size of the LCD is extremely large, etc.), as shown in FIG. This can be done via the driver 51 and the receiver 52. When this configuration is adopted (and the length of the signal line is about 1 m), the frequency of the clock signal can be set to about 50 MHz.

  When the arbitration circuit 44 receives a SW read command / LED write command while a certain circuit is using the serial interface circuit 45, the command is sent after the use of the serial interface circuit 45 by the circuit is completed. It can be transformed into a circuit to be processed. Further, the operation panel 21 may be provided with a serial interface circuit having a lower function than the serial interface circuit 25 and a CPU. Of course, a device other than a so-called multifunction device may be realized based on the technology used in the information processing device 10.

1 is an external view of an information processing apparatus according to an embodiment. The block diagram of the information processing apparatus which concerns on embodiment. FIG. 5 is a diagram for explaining the operation of a serial interface circuit provided in the controller of the information processing apparatus according to the embodiment. The block diagram of the LED interface circuit provided in the controller of the information processing apparatus which concerns on embodiment. The block diagram of SW interface circuit provided in the controller of the information processing apparatus which concerns on embodiment. Explanatory drawing of the deformation | transformation form of the information processing apparatus which concerns on embodiment. FIG. 3 is a schematic configuration diagram of a conventional multi-function peripheral in which command / data exchange between an operation panel and a controller is performed by serial communication. FIG. 3 is a schematic configuration diagram of a conventional multi-function peripheral in which command / data exchange between an operation panel and a controller is performed by serial communication. The figure for demonstrating the problem which arises when the structure which performs transmission / reception of the command / data between an operation panel and a controller by serial communication is employ | adopted.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Information processing apparatus, 20 Scanner unit, 21 Operation panel 25, 45 Serial interface circuit, 30 Printer unit 31 Controller, 32 Print engine, 40 CPU
41 LED interface circuit, 42 LCD interface circuit 43 SW interface circuit, 44 arbitration circuit

Claims (1)

An information processing apparatus including an operation panel and a control unit,
The operation panel is
LCD,
Multiple switches,
A plurality of LEDs;
Processing for receiving image data to be supplied to the LCD by performing serial communication with the control unit, processing for receiving LED control data indicating a state that each of the plurality of LEDs should take, or A serial communication circuit that executes a process of transmitting switch status data indicating the status of a plurality of switches.
The control unit is
CPU,
Image data transmission processing for transmitting the image data to the serial communication circuit by performing serial communication with the serial communication circuit, LED control data transmission processing for transmitting the LED control data to the serial circuit, Alternatively, it is a unit having an operation panel communication circuit for executing switch state data reception processing for receiving the switch state data from the serial communication circuit,
The operation panel communication circuit comprises:
An operation unit side serial communication circuit for performing serial communication with the serial communication circuit in the operation panel;
An LED circuit that includes an LED control data register in which the LED control data is written by the CPU, and that repeatedly performs the process of transmitting the LED control data set in the LED control data register to the serial circuit; ,
A switch state data register accessible by the CPU for storing the switch state data is provided, and the switch state data is received from the serial communication circuit and stored in the switch state data register periodically. SW circuit,
An LCD circuit for outputting the supplied image data to be supplied to the LCD;
A circuit constituted by an arbitration circuit that causes the operation unit side serial communication circuit to be used by any one of the LED circuit, the SW circuit, and the LCD circuit;
The CPU
New image data is given to the LCD circuit at an arbitrary timing,
Set new LED control data in the LED control data register at an arbitrary timing,
Obtaining the switch status data received by the switch status data reception process from the switch status data register at an arbitrary timing;
An information processing apparatus characterized by that.