JP3133732B2 - Multi-slave bus line system and serial transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus line system in which a plurality of slave devices are controlled by one or more master devices. A multi-slave bus line system suitable for a management system for monitoring status, a management system for displaying status by an LED (light emitting diode), an LCD (liquid crystal display), or the like, or a management system for managing version numbers for each device or module; Related to serial transfer method.

[0002]

2. Description of the Related Art In recent years, a management system for monitoring the state of a data processing apparatus such as voltage and temperature, opening and closing of a cover or the number of rotations of a fan, a management system for displaying a state by an LED, an LCD, or the like, or a device or module unit. The development of a bus line system suitable for a management system for managing version numbers has been actively pursued.

A serial transfer bus used for such a management system of an information processing apparatus generally includes an I2C bus composed of two lines, a serial data line (SDA) and a serial clock line (SCL). Often used. Normally, one I2C bus has a master device for controlling the management system, a sensor for monitoring the status, and an LED and L for displaying the status.
A plurality of slave devices such as a CD controller and a memory for managing version numbers are connected.

However, as the number of connected devices increases, the stray capacitance of the bus increases and it becomes difficult to maintain the signal level, so that the number of connected devices is limited. Further, a general slave device is limited in the number of selectable slave addresses, and it is not possible to connect more than the same type of slave devices on the same bus.

On the other hand, in a large-scale information processing apparatus, the number of required slave devices increases with the increase in the scale.
It is required to connect slave devices beyond the limit of the characteristics of the transmission line or the number of slave addresses.

[0006] As a prior art meeting this demand, there is, for example, one disclosed in Japanese Patent Application Laid-Open No. 8-84154. FIG. 5 is a functional block diagram for explaining a conventional multi-slave bus line system. In the prior art, as shown in FIG. 5, a plurality of I2Cs are provided so as to avoid division of a transmission line or duplication of a slave address.
I2C bus (hereinafter referred to as a master bus) to which slave devices are connected in a distributed manner and to which a master device 24 is connected
And a plurality of I2C buses (hereinafter, slave buses) to which slave devices are connected by a switch, and selectively connect them to realize a data transfer (hereinafter, multi-slave bus line system). .

The technique disclosed in the prior art, as shown in FIG. 5, employs switches 26, 27, 28, and 29 for switching between slave buses 39, 40, 41, and 42, and the above-described switches corresponding to data transfer destinations. And a master device 24 having an I2C bus master interface 23 having a function of transmitting a data transfer destination to the switch control circuit 25.

[0008]

However, in the prior art, for example, when data transfer is performed from the master device 24 to the slave device 30, before the master device 24 transmits / receives data to / from the master bus 38, The changeover switch 26 is connected so that the slave bus 39 of the transmission / reception destination and the master bus 38 are connected.
To ON, and changeover switches 27, 28, 29 to OF
F is required. Therefore, it is necessary to provide the master device 24 with the I2C bus master interface 23 having the function of transmitting and receiving data to and from the I2C bus and the function of controlling the switch of the data transmission / reception destination to the switch control circuit 25. . As a result, a general master device 24 cannot be used to realize a bus line system, and software compatibility with a bus line system realized by one I2C bus is also lost. There was a point. Also,
There is also a problem that the system does not cope with a system in which a plurality of master devices are connected.

Changeover switches 26, 27, 28, 29
ON or OFF of the I2C bus 38, 39, 40,
Since the operations must be performed in a bus-free state, the master device 24 shifts the I2C bus 38, 39, 40, 41, 4 from the bus-free state before data transfer.
2 must be occupied. As a result, when two or more master devices 24 are connected, it is necessary to separately provide an arbitration function between the master devices 24 in the I2C bus master interface 23 of each master device 24 so that the communication adjustment procedure of the I2C bus functions. There is also a problem that a very complicated circuit is required.

[0010] The present invention has been made in view of such a problem, and an object of the present invention is to use a currently used general I2C bus master device and a slave device while improving software compatibility. It is another object of the present invention to provide a multi-slave bus line system and a serial transfer method that can connect more slave devices while maintaining the same.

[0011]

The gist of the present invention is to provide a multi-slave bus line system in which a plurality of slave devices are controlled by at least one master device. At least one or more of the master devices having a bus master interface for controlling the slave device, at least one or more of the slave devices,
Logical address and real address, corresponding to the real address
At least the bus number of the slave bus
An address decode table, an address decoder that performs a slave address decoding process by referring to the address decode table, and a logical address transmitted from the master device is converted to a real address by referring to the address decode table. transmits to the slave device, possess a bus switching system for controlling data transfer between said master device and said slave device, said bus switching system, before
Set the decoding bit width of the slave address to the specified width.
Limited and transmitted on the master bus from the master device
Said slave device to be transmitted and received
Address logical table, and the address decode table.
Decode with reference to the slave device is connected
Slave bus and the master bus are connected,
Switch control and the actual address of the slave device
The slave address on the slave bus.
Transmitted, it consists in a multi-slave bus line system comprising a call <br/> to perform operations that send and receive data. According to a second aspect of the present invention, there is provided a multi-slave bus line system for controlling a plurality of slave devices by at least one or more master devices, wherein at least one or more of the master devices are connected. A master bus, a plurality of slave buses to which at least one or more of the slave devices are connected, and at least one switch for turning on or off a connection between the master bus and one or more of the plurality of slave buses A switch control circuit for turning on or off a switch for switching the slave bus; and a logical address and a real address of the slave device.
Vinegar, Basunan of slave Bubasu corresponding to the real address
An address decode table in which a bar is described at least , an address decoder for performing a slave address decoding process by referring to the address decode table, and referring to the address decode table based on a logical address transmitted from the master device. wherein by supplying data to the switch control circuit from the address decoder controls said switch, possess a bus switching system for switching by selecting a plurality of buses which the slave device is connected, the bus switching system,
The bit width for decoding the slave address is a predetermined width.
Limited from the master device to the master bus
The slave that is transmitted and that is the object of data transmission / reception
The logical address of the device is stored in the address decode table.
And decodes it with reference to the slave device.
The connected slave bus and the master bus are connected.
Switch control so that the slave device
To the real address of the slave bus
The operation of sending an address and sending and receiving data
The present invention resides in a multi-slave bus line system. The gist of the invention described in claim 3 of the present invention is that the bus switching system supplies data to be supplied to the switch control circuit from the address decoder provided on the slave bus. A multi-slave bus line system according to claim 1 or 2 . Further, the gist of the invention according to claim 4 of the present invention is that the bus switching system transmits the logical address of the slave device, which is transmitted and received from the master device on the master bus, to which data is to be transmitted and received. Decoding is performed with reference to an address decode table, the switch is controlled so that the slave bus to which the slave device is connected and the master bus are connected, and the switch is converted into a real address of the slave device and is converted on the slave bus. The multi-slave bus line system according to any one of claims 1 to 3 , wherein a slave address is transmitted to said multi-slave bus line system. The gist of the invention described in claim 5 of the present invention is that the bus number of the slave bus to be connected and the bus number of the slave bus to be connected are referred to based on the logical address of the slave device transmitted from the master device with reference to the address decode table. 3. The multi-slave bus line system according to claim 1, further comprising an address decoder for generating a real address of the slave device. Further, claim 6 of the present invention
The gist of the present invention resides in the multi-slave bus line system according to claim 5 , wherein the address decoder transmits the bus number to the switch control circuit and turns the switch ON or OFF. . The gist of the invention described in claim 7 of the present invention is that when the slave bus to which the slave device to be transferred is connected and the master bus are connected,
The address decoder transmits a real address to the master bus, and the master device and the slave device transmit and receive data.
5 is a multi-slave bus line system. The gist of the invention described in claim 8 of the present invention is as follows.
And at least one master device having a bus master interface for controlling transmission and reception of data, and at least one or more slave devices, the Surebude
Device logical address and real address, the real address
The bus number of the slave bus corresponding to
Described above, and a multi-slave bus line system including an address decoder that decodes a slave address with reference to the address decode table. A serial transfer method including a step of controlling data transfer, wherein a logical address transmitted from the master device is converted to a real address with reference to the address decode table and transmitted to the slave device, and have a bus switching step of controlling the data transfer between the device and the slave device, said bus switching step,
The bit width for decoding the slave address is a predetermined width.
And a master bus from the master device.
The above-mentioned thread for which data is transmitted and received is transmitted.
Decodes the logical address of the
Decoding with reference to the table,
Is connected to the slave bus to which the master bus is connected.
Switch control so that the slave device
To the real address of the slave bus
Sending an address, the operation of transmitting and receiving data
A serial transfer method characterized by having a step of executing . The gist of the invention according to claim 9 of the present invention is that a master bus to which at least one or more of the master devices is connected, a plurality of slave buses to which at least one or more of the slave devices are connected, the master bus and at least one or more switches to ON or OFF the connection between the one or more plurality of slave bus, and a switch control circuit for turning ON or OFF a switch for switching the slave bus, said slave
Logical address and real address of the
If the bus number of the slave bus corresponding to the
Between the master device and the slave device, for a multi-slave bus line system including an address decode table also describing the address decode table and an address decoder for performing a slave address decoding process with reference to the address decode table. A serial transfer method including a step of controlling data transfer, wherein the data is supplied from the address decoder to the switch control circuit by referring to the address decode table based on a logical address transmitted from the master device. A bus switching step of controlling the switch to select and switch a plurality of buses to which the slave device is connected.
The bus switching step includes the step of
Limiting the bit width to be decoded to a predetermined width;
Data transmitted from the master device on the master bus
Logic of the slave device to be transmitted / received data
Refer to the address decode table for the address.
Decodes the slave to which the slave device is connected.
Switch so that the bus and the master bus are connected.
Control and convert to the real address of the slave device
To send a slave address on the slave bus,
It has the step of performing the operation of sending and receiving data
It consists in serial transfer method characterized by that. Also,
The gist of the invention according to claim 10 of the present invention is characterized in that the bus switching step includes a step of supplying data supplied to the switch control circuit from the address decoder provided on the slave bus. Claim 8
Or the serial transfer method described in Item 9 . The gist of the invention according to claim 11 of the present invention is that, in the bus switching step, the logical address of the slave device to be transmitted and received from the master device on the master bus, Decoding with reference to an address decode table, and controlling the switches so that the slave bus to which the slave device is connected and the master bus are connected;
The converted into real address of the slave device sends a slave address on the slave bus, 8 through claim, characterized in that a step of transmitting and receiving data
10. The serial transfer method according to any one of the above items 10 . Further, the gist of the invention according to claim 12 of the present invention refers to a bus number of the slave bus to be connected, based on a logical address of the slave device transmitted from the master device, by referring to the address decode table. / or existing in the serial transmission method according to claim 8 or 9, characterized in that a bus address decoder generating a real address of the slave device. The gist of the invention described in claim 13 of the present invention is characterized in that the bus address decoder step includes a step of transmitting the bus number to the switch control circuit and turning on or off the switch. Claim 1
0 in the serial transfer method.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) In order to clarify the above and other objects, features and advantages of the present invention, an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a functional block diagram for explaining one embodiment of the multi-slave bus line system 100 of the present invention. Referring to FIG. 1, a multi-slave bus line system 100 includes one master device 2 having an I2C bus master interface 1, four slave buses 19, 20, 21 and 22, and slave devices 10 and 1.
1, 12, 13, 14, 15, 16, 17 and a bus switching system 70.

FIG. 2 shows an embodiment of the address decode table 3 used in the multi-slave bus line system 100 of FIG. The bus switching system 70
It comprises an address decode table 3, an I2C bus address decoder 4, a switch control circuit 5, and bus changeover switches 6, 7, 8, and 9.

The address decode table 3 includes slave devices 10, 11, 12, 13, 14, 15, 1
At least the logical addresses 6 and 17 and the real addresses, and the bus numbers of the slave buses 19, 20, 21, and 22 corresponding to the real addresses are described.

The switch control circuit 5 includes a slave bus 1
A switch 6, 7, 8 or 9 for switching 9, 20, 21 or 22 is turned on or off.

The bus switching system 70 of the present embodiment
Converts the data supplied to the switch control circuit 5 into I2
It has a function of supplying from an address decoder 4 provided on the C bus.

For example, when transferring data from the master device 2 to the slave device 10, the bus switching system 70 uses the logical address of the slave device 10 to be transmitted and received, which is transmitted on the master bus 18 from the master device 2. Are controlled by referring to the address decode table 3 and the switches 6, 7, 8, and 9 are controlled so that the slave bus 19 to which the slave device 10 is connected and the master bus 18 are connected. Convert to real address and slave bus 1
9 to transmit a slave address and transmit and receive data.

The logical address transmitted to the master bus 18 contains data necessary for switch control. For this reason, the master device 2 and the switch control circuit 5
No need to have an interface. Also, since the switches 6, 7, 8, 9 are turned on or off in the data transfer procedure of the I2C bus, the communication adjustment procedure of the I2C bus is effective. Therefore, two or more existing master devices 2 are maintained while maintaining software compatibility.
, A slave bus line system having a large number of slave buses can be realized.

Next, the serial transfer method of the present embodiment executed by the multi-slave bus line system 100 will be described.

The serial transfer method according to the present embodiment includes a master bus 18 to which at least one or more master devices 2 are connected, and a plurality of slave buses 19, 20, 21, and 21 to which at least one or more slave devices are connected. 22
At least one or more switches 6 (7, 8, 9) for turning on or off the connection between the master bus 18 and one or more slave buses;
Switch for switching 0, 21 or 22;
A switch control circuit 5 for turning on, off or 7, 7, or 9 an address decode table 3 for the slave devices 10 to 17 and an address decoder for decoding the slave address with reference to the address decode table 3 A serial transfer method including a step of controlling data transfer between a master device 2 and a slave device with respect to a slave bus line system, wherein the address decode table 3 is based on a logical address transmitted from the master device 2. , A bus switching step and a bus address decoder step of supplying data from the address decoder to the switch control circuit 5 to control the switch, and selecting and switching a plurality of buses to which the slave devices are connected.

The bus switching step includes a step of limiting the bit width for decoding the slave address to a predetermined width. Further, the data supplied to the switch control circuit 5 is
There is a step of supplying from the address decoder 4 provided on the slave bus. A step of decoding the logical address of the slave device 10 to be transmitted / received from the master device 2 on the master bus 18 with reference to the address decode table 3; The switches 6, 7, 8, and 9 are connected so that the bus 19 and the master bus 18 are connected.
9 and a step of transmitting the slave address on the slave bus 19 by converting it into a real address of the slave device 10 and transmitting and receiving data.

The bus address decoder step refers to the address decode table 3 and, based on the logical address of the slave device 10 transmitted from the master device 2, determines the bus number of the slave bus 19 to be connected and / or the actual number of the slave device 10. Generating an address. Further, the method includes a step of transmitting the bus number to the switch control circuit 5 to turn on or off the switches 6, 7, 8, and 9.

Next, the operation of the multi-slave bus line system 100 that executes the serial transfer method of this embodiment will be described. The I2C bus address decoder 4 generates the bus number of the I2C bus 19 to be connected and the real address of the slave device 10 from the logical address of the slave device 10 sent from the master device 2 with reference to the address decode table 3. . I2
The C bus address decoder 4 transmits the bus number to the switch control circuit 5, and turns on or off the switches 6, 7, 8, and 9. In response, the master bus 18 to which the master device 2 is connected and the I2C bus 19 to which the slave device 10 to which data is to be transferred are connected are connected.
In response to this, the I2C bus address decoder 4 transmits a real address to the master bus 18 and thereafter performs data transmission and reception between the master device 2 and the slave device 10.

Next, referring to FIG. 1, the data transfer from the master device 2 to the slave device 10 will be described as an example. The I2C bus address decoder 4 refers to the address decode table 3 based on the logical address of the slave device 10 input from the master device 2 and generates the bus number of the slave bus 19 and the real address of the slave device 10. Execute.

The generated slave bus number (the bus number of the slave bus 19) is transmitted to the switch control circuit 5. In response to this, the switch control circuit 5 turns on the bus changeover switch 6 and turns off the bus changeover switches 7, 8, and 9 based on the contents of the slave bus number, and transmits and receives data to and from the master bus 18. The slave bus 19 is connected.

The logical address transmitted to the master bus 18 contains data necessary for switch control. Therefore, it is not necessary to provide a special interface for performing switch control in the I2C bus master interface 1 of the master device 2.

The slave devices 10, 11, 1
The logical addresses of 2, 13, 14, 15, 16, 17 are I
It is set according to the address format of the 2C bus. Therefore, there is no need to set a special data transfer protocol in the I2C bus master interface 1 of the master device 2, and it is only necessary to be aware that the slave address is not a real address but a logical address.

On the other hand, the I2C bus address decoder 4
The generated real address is transmitted to the slave bus 19.
In response to this, the slave device 10 determines, based on the real address transmitted from the I2C bus address decoder 4,
It recognizes that the transmission / reception object is itself, and starts data transmission / reception processing.

At this time, the slave devices 10, 11,
Since data is transmitted and received to 12, 13, 14, 15, 16, and 17 based on the real address, there is no need to pay special attention.

The operation of this embodiment will be described below.
First, regarding the operation of the I2C bus address decoder 4,
This will be described with reference to the timing chart of FIG. FIG.
FIG. 2 is a timing chart for explaining a first embodiment of data transfer executed between the master bus 18 and the slave bus by the multi-slave bus line system 100 of FIG. 1.

When the start condition signal 43 is transmitted on the SDA (master bus / serial data line) 18a and the SCL (master bus / serial clock line) 18b of the master bus 18, the logic of the slave device is set as 7 bits following the start condition signal 43. The address 45 is transmitted.

When the 7 bits following the start condition signal 43 are received, the I2C bus address decoder 4
8 SCL (master bus serial clock line) 1
8b is held LOW, and the master device 2 is put into a waiting state by synchronizing the clock of the I2C bus. Next, referring to the address decode table 3, the received logical address 45 is converted into a slave bus number and a real address 46 of the slave device.

The converted slave bus number is transmitted to the switch control circuit 5, and the switch control circuit 5 determines from the slave bus number,
The master bus 18 is connected to a slave bus to which data is transmitted and received.

The I2C bus address decoder 4 receives the start condition signal 44 from the master bus 18 and
When it is confirmed that the slave bus 19 is connected to the slave bus 19 as a data transmission / reception destination,
The real address 46 of the bit is transmitted.

When the transmission of the real address 46 is completed, the I2C bus master interface 1 releases the SCL 18b of the master bus 18 and releases the waiting state of the master bus 18.

Thereafter, the I2C bus address decoder 4
Does not perform any conversion processing on data transmission and reception between the master bus 18 and the slave bus until the next start condition signal 44 is received from the master bus 18.

As described above, the master device 2 and the I2C
Data transfer with the bus address decoder 4 follows the data transfer procedure of the I2C bus, although there is a difference that the transmitted slave address is not a real address but a logical address. Therefore, the communication arbitration procedure of the I2C bus is effective. It is. Therefore, even when a plurality of master devices 2 are connected to the master bus 18, the above operation can be performed. The operation of the slave bus is equivalent to that of a general I2C bus data transfer procedure.

In summary of the first embodiment, at least one or more I2C bus master devices having a standard I2C bus master interface 1 without using a special interface or a special transfer protocol, and a general I2C bus master device A bus switching system 70 and a multi-slave bus line system 1 that realize selection and switching of a plurality of slave buses by decoding slave addresses based on a basic configuration of an I2C bus line system using a plurality of I2C bus slave devices.
00 and the serial transfer method. Furthermore, a slave bus line system having a large number of slave buses can be realized using two or more existing master devices 2 while maintaining software compatibility.

(Second Embodiment) FIG. 4 is a timing chart for explaining a second embodiment of data transfer executed between the master bus 18 and the slave bus by the multi-slave bus line system 100 of FIG. Second embodiment of the present invention
The basic configuration of the embodiment is the same as that of the first embodiment, but the capacity of the address decode table 3 is reduced by reducing the width of the decode bit of the slave address.
It is possible to reduce the time for the decoding process. For example, when the lower 3 bits of the slave address are the same as the real address and only the upper 4 bits are decoded, the I2C
The timing chart of the bus address decoder 4 is as shown in FIG.

That is, when the start condition signal 43 is transmitted from the SDA (master bus / serial data line) 18a and the SCL (master bus / serial clock line) 18b of the master bus 18, the four bits following the start condition signal 43 are set to the slave device. The upper 4 bits 48 of the logical address 45 are transmitted.

When receiving the upper 4 bits 48 of the logical address 45 of the slave device, the I2C bus address decoder 4 keeps the SCL 18b of the master bus 18 LOW, and waits for the master device 2 by synchronizing the clock of the I2C bus. To Next, the upper 4 bits 48 of the received logical address are converted into the slave bus number and the upper 4 bits 49 of the real address 46 of the slave device with reference to the address decode table 3.

The converted slave bus number is transmitted to the switch control circuit 5. In response, the switch control circuit 5 performs switch control during the switch control period 47 based on the slave bus number, and connects the master bus 18 and the slave bus 19 to which data is transmitted and received.

The I2C bus address decoder 4 receives the start condition signal 44 from the master bus 18 and
When it is confirmed that the slave 8 and the slave bus 19 to which data is to be transmitted and received are connected, the upper 4 bits 49 of the real address are transmitted to the slave bus 19. When the transmission of the upper 4 bits 49 is completed, the I2C bus master interface 1 releases the SCL 18b of the master bus 18 and releases the waiting state of the master device 2.

The master device 2 transmits the lower 3 bits and subsequent bits of the real address 46 of the slave device. Thereafter, until the next start condition signal 44 is received from the master bus 18, the I2C bus address decoder 4 does not perform any conversion processing for data transmission and reception between the master bus 18 and the slave bus.

In summary of the second embodiment, at least one or more I2C bus master devices having a standard I2C bus master interface 1 without using a special interface or a special transfer protocol, and a general I2C bus master device, A bus switching system 70 and a multi-slave bus line system 1 that realize selection and switching of a plurality of slave buses by decoding slave addresses based on a basic configuration of an I2C bus line system using a plurality of I2C bus slave devices.
00 and the serial transfer method. Furthermore, a slave bus line system having a large number of slave buses can be realized using two or more existing master devices 2 while maintaining software compatibility.

It should be noted that the present invention is not limited to the above-described embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, but can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0048]

According to the present invention, the serial transfer bus for connecting devices can be realized beyond the limit of the number of devices connected to the bus. Further, there is an effect that more slave devices can be connected while using a general I2C bus master device and slave devices and maintaining software compatibility.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating an embodiment of a multi-slave bus line system according to the present invention.

FIG. 2 is an embodiment of an address decode table used in the multi-slave bus line system of FIG. 1;

FIG. 3 is a diagram illustrating a first example of data transfer performed between the master bus and the slave bus by the multi-slave bus line system of FIG.
5 is a timing chart for explaining the embodiment.

FIG. 4 is a diagram illustrating a second data transfer performed between the master bus and the slave bus by the multi-slave bus line system of FIG. 1;
5 is a timing chart for explaining the embodiment.

FIG. 5 is a functional block diagram for explaining a conventional multi-slave bus line system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... I2C bus master interface 2 ... Master device 3 ... Address decode table 4 ... I2C bus address decoder 5 ... Switch control circuit 6,7,8,9 ... Switch 10,11,12,13,14,15,16,17 ... Slave device 18 Master bus 18a Master bus serial data line (SDA) 18b Master bus serial clock line (SC
L) 19, 20, 21, 22 ... slave bus 19a ... slave bus serial data line (SD
A) 19b: Slave bus serial clock line (SC
L) 43, 44 start condition signal 45 logical address of slave device 46 actual address of slave device 47 switch control period 48 upper 4 bits of logical address of slave device 49 upper 4 bits of real address of slave device 70 bus switching system 100 multi-slave bus line system

Claims (13)

(57) [Claims] 1. A multi-slave bus line system for controlling a plurality of slave devices by at least one or more master devices, wherein at least one or more of the master devices have a bus master interface for controlling transmission and reception of data. One or more of the slave devices, a logical address and a real address of the slave device,
Bus number of the slave bus corresponding to the real address
An address decode table that describes at least a slave address with reference to the address decode table, and a real address transmitted from the master device with reference to the address decode table. converted to it and transmits to the slave device, possess a bus switching system for controlling data transfer between said master device and said slave device, said bus switching system, the slave address
The bit width to be decoded is limited to a predetermined width, and the master data is decoded.
Of data transmitted from the device to the master bus
The logical address of the slave device to be
Decoding with reference to the address decode table,
A slave bus to which the slave device is connected;
Perform switch control so that it is connected to the master bus,
After converting to the real address of the slave device,
Slave address on the slave bus and send / receive data
A multi-slave bus line system, which performs an operation of performing communication . 2. A multi-slave bus line system for controlling a plurality of slave devices by at least one or more master devices, wherein a master bus to which at least one or more of the master devices is connected; A plurality of slave buses to which slave devices are connected; at least one switch for turning on or off the connection between the master bus and one or more slave buses; and a switch for switching the slave bus. A switch control circuit for turning on or off, a logical address and a real address of the slave device,
Bus number of the slave bus corresponding to the real address
An address decode table in which at least is described ; an address decoder that performs a slave address decoding process with reference to the address decode table; and an address decoder that references the address decode table based on a logical address transmitted from the master device. and supplying data from the address decoder to the switch control circuit controls said switch, possess a bus switching system for switching by selecting a plurality of buses which the slave device is connected, the bus switching system, the Slave address
The bit width to be decoded is limited to a predetermined width, and the master data is decoded.
Data transmitted from the device to the master bus.
Logical address of the slave device to be received
With reference to the address decode table.
The slave device to which the slave device is connected.
Switch control so that the bus and the master bus are connected.
And convert it to the real address of the slave device.
The slave address is transmitted on the slave bus,
A multi-slave bus line system that performs an operation of transmitting and receiving data. Wherein said bus switching system, multi-slave bus according to claim 1 or 2, characterized in that to supply data to be supplied to the switch control circuit, from the address decoder provided on the slave bus Line system. 4. The bus switching system decodes a logical address of the slave device, which is a target of data transmission and reception, transmitted from the master device on the master bus with reference to the address decode table, The switch is controlled so that the slave bus to which the slave device is connected and the master bus are connected, the switch is converted into a real address of the slave device, a slave address is transmitted on the slave bus, and data transmission / reception is performed. The multi-slave bus line system according to any one of claims 1 to 3 , wherein the bus operation is performed. 5. A bus number of the slave bus to be connected and / or a real address of the slave device are generated based on a logical address of the slave device transmitted from the master device with reference to the address decode table. 3. The multi-slave bus line system according to claim 1, further comprising an address decoder. 6. The address decoder transmits the bus number to the switch control circuit and turns on the switch.
The multi-slave bus line system according to claim 5 , wherein the multi-slave bus line system is turned off. 7. When the slave bus to which the slave device to be transferred is connected and the master bus are connected, the address decoder transmits a real address to the master bus, and The multi-slave bus line system according to claim 5 , wherein the slave device transmits and receives data. 8. At least one or more master devices having a bus master interface for controlling transmission and reception of data, at least one or more slave devices,
A logical address and a real address of the slave device,
Bus number of the slave bus corresponding to the real address
And a multi-slave bus line system including an address decode table in which at least is described, and an address decoder that performs a slave address decoding process with reference to the address decode table. A serial transfer method comprising a step of controlling data transfer between, the logical address transmitted from the master device, referring to the address decode table and converted to a real address and transmitted to the slave device, have a bus switching step of controlling the data transfer between said master device and said slave device, said bus switching step, the slave address decode bit width predetermined width
A step of limiting, the sent on the master bus from the master device, de
Logic of the slave device to be transmitted / received data
Refer to the address decode table for the address.
Decodes the slave to which the slave device is connected.
Switch so that the bus and the master bus are connected.
Control and convert to the real address of the slave device
To send a slave address on the slave bus,
It has the step of performing the operation of sending and receiving data
Serial transfer wherein the that. 9. A master bus to which at least one or more master devices are connected, a plurality of slave buses to which at least one slave device is connected, and a plurality of slaves to the master bus at least one or more switches to ON or OFF the connection between the bus, and a switch control circuit for turning ON or OFF a switch for switching the slave bus, said
The logical address and real address of the slave device,
The bus number of the slave bus corresponding to the real address is low.
An address decode table described at least ,
Controlling a data transfer between the master device and the slave device to a multi-slave bus line system including an address decoder for performing a slave address decoding process with reference to the address decode table. A serial transfer method, wherein the slave device controls the switch by supplying data to the switch control circuit from the address decoder with reference to the address decode table based on a logical address transmitted from the master device, have a bus switching step of switching to select a plurality of buses connected, the bus switching step, the slave address decoding predetermined width bit wide
A step of limiting the, transmitted from the master device on the master bus
The slave device to be used for data transmission and reception
Refer to the address decode table.
And decodes it, and the slave device is connected
So that the slave bus and before Symbol master bus is connected, vinegar
Switch control to determine the actual address of the slave device.
And sends the slave address on the slave bus.
The step of performing an operation of transmitting and receiving data
Serial transfer method characterized by having a. 10. The bus switching step according to claim 8 , further comprising the step of supplying data to be supplied to the switch control circuit from the address decoder provided on the slave bus. Serial transfer method. 11. The bus switching step includes: decoding a logical address of the slave device, which is a target of data transmission and reception, transmitted from the master device onto the master bus, with reference to the address decode table. Controlling the switch so that the slave bus to which the slave device is connected and the master bus are connected; and converting the slave device into a real address of the slave device and transmitting a slave address on the slave bus; 8 through claim, characterized in that a step of transmitting and receiving data
Serial transfer method according to any one of 10. 12. A bus number of the slave bus to be connected and / or a real address of the slave device are generated based on a logical address of the slave device sent from the master device with reference to the address decode table. serial transfer method according to claim 8 or 9, characterized in that a bus address decoder process. 13. The serial transfer method according to claim 10 , wherein the bus address decoder step includes a step of transmitting the bus number to the switch control circuit and turning on or off the switch.