JP2000114197A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an N-type diffusion layer and a P-type diffusion layer at the same time, in which junction is shallow and resistance is low through annealing treatment, by rapidly increasing a temperature up to a temperature where enhanced diffusion due to point defect is generated, in an oxygen added atmosphere, and containing a process restraining the generation of enhanced diffusion due to oxidation. SOLUTION: A silicon substrate 101, is subjected to rapid thermal anneal(RTA) treatment boron ions and phosphorus ions in the respective implantation layers 107, 109 are activated, and a P-type extension 110 and an N-type extension 111 are formed. In the RTA treatment at this time, the temperature is rapidly increased up to a temperature where enhanced diffusion due to point defect is generated, in an oxygen-added atmosphere. After that, a process for restraining the generation of enhanced diffusion due to oxidation is added. As a result, a P-type diffused layer and an N-type diffused layer are formed with the respective shallow junctions and low resistances irrespective of the difference of behaviors of P-type impurities and N-type impurities at annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a shallow junction and a low resistance P-type diffusion layer and an N-type diffusion layer, and more particularly to a P-channel MOS transistor having a shallow junction and a low resistance extension and an N-channel. MOS
The present invention relates to a method for manufacturing a semiconductor device including a transistor.

[0002]

2. Description of the Related Art With the recent increase in the density of semiconductor devices, MOS transistors have been miniaturized, and it is required to make the junction between the source and drain regions shallow. In particular, in a MOS transistor having an LDD structure in which the source / drain is composed of a low-concentration region (LDD) region and a high-concentration region, conventionally, the LDD region is formed with a low concentration in order to cope with a decrease in breakdown voltage due to hot carriers. However, its purpose has weakened with the recent decrease in power supply voltage in semiconductor devices.
Rather, the impurity concentration of the LDD region is increased to lower the resistance of the transistor, thereby increasing the operation speed. For this reason, such an LD with an increased impurity concentration is used.
The area corresponding to D is called an extension area. Therefore, with the miniaturization of semiconductor devices, there is an increasing demand for forming a high-concentration and shallow junction extension region.

A CMOS in which a P-channel MOS transistor and an N-channel MOS transistor having such an extension region are integrally formed on one semiconductor substrate
In a semiconductor device having a structure, if a conventional CMOS structure manufacturing method including a MOS transistor having an LDD region is applied as it is, a desired extension region, that is, one of a P-channel MOS transistor and an N-channel MOS transistor is used. While the junction is shallow, it is difficult to form a low-resistance extension region having a high impurity concentration.

[0004] This will be described with reference to FIGS. 2 and 3 of a process chart referred to in an embodiment of the present invention described later. This figure is a diagram for explaining a part of the manufacturing process of a semiconductor device having a CMOS structure having a PMOS transistor and an NMOS transistor each having an extension. First,
As shown in FIG. 2A, an N well 102 is formed in a partial region of a P-type silicon substrate 101. Then, after forming an element isolation insulating film 103 on the surface of the silicon substrate 101 to partition and form an element region, a gate insulating film 1 is formed on each element region.
04 and a gate electrode 105 are formed. And
As shown in FIG. 2B, the PMO is
After covering the S region, boron is ion-implanted into the region of the N well 102 to form a boron implanted layer 107. Next, as shown in FIG.
Another photoresist film 108 is formed so as to cover the region, and phosphorus is ion-implanted to form a phosphorus-implanted layer 109. Thereafter, as shown in FIG. 2D, an annealing process is performed to activate each ion-implanted impurity,
Mold and N-type extensions 110 and 111 are formed. Furthermore, although the detailed description of the subsequent steps is omitted,
After a sidewall 112 is formed on a side surface of the gate electrode 105 by a known technique, each of the extensions 11 is formed.
In the same manner as in the method of forming 0 and 111, arsenic is implanted into the NMOS region and boron is implanted into the PMOS at a higher concentration than the extensions 110 and 111 using the photoresist film as a mask and activated by annealing. Then, as shown in FIG. 3D, P-type and N-type high concentration source / drain regions 117 and 118 are formed.

In this manufacturing method, the P-type extension 110 and the N-type extension 111 are simultaneously activated and formed by annealing. However, arsenic or phosphorus as an N-type impurity and boron as a P-type impurity are not activated. The following problems arise because the behavior due to heat during the formation is different. That is, the N-type impurities easily evaporate from the surface of the silicon substrate during the heat treatment. For this reason, the concentration of the impurities implanted in the silicon crystal of the silicon substrate is reduced,
The extension to be formed is reduced in concentration, and the resistance is increased. To avoid this,
A cover oxide film is formed on the surface of the silicon substrate before annealing, or the cover oxide film grows on the surface of the silicon substrate as the annealing progresses by annealing in a slight oxygen-added atmosphere of several hundred to several thousand ppm. However, a method for suppressing the evaporation of N-type impurities has been studied.

FIG. 11 is a view for explaining the above-mentioned matter, in which phosphorus of an N-type impurity is ion-implanted into a silicon substrate.
In an atmosphere in which a cover oxide film is present and oxygen is not added (a1), in an atmosphere in which no cover oxide film is present and oxygen is added (a2), an atmosphere in which no cover oxide film is present and oxygen is not added is present. RT for each of the cases (a3)
A shows the profile of impurities when A (rapid thermal annealing) treatment is performed. FIG. 12 shows the relationship between the implantation dose and the sheet resistance at that time. From these results, the RTA treatment in an atmosphere in which the cover oxide film does not exist and oxygen is not added does not show the phosphorus. It can be seen that the concentration of is low and it is difficult to realize a low resistance.

On the other hand, the P-type impurities are easily taken into the silicon oxide film existing on the surface of the silicon substrate or the like during the heat treatment. The impurities are taken into the film, whereby the concentration of impurities in the silicon crystal is reduced, the concentration of the formed P-type extension region is reduced, and the resistance is increased. In addition, in an oxygen-added atmosphere of a few hundred ppm or more even in a trace amount, accelerated diffusion of boron (OED: Oxidation Enhanced Diffusion) by interstitial silicon supplied by oxidation becomes remarkable, and P-type impurities become N-type wells. , The diffusion layer becomes deeper, and a shallow junction cannot be obtained. In order to avoid this, annealing is performed in a state where the cover oxide film does not exist on the surface of the silicon substrate and in an atmosphere where oxygen does not exist, thereby suppressing the above-described increase in resistance and deepening of the junction. A method is being considered.

FIG. 13 is a view showing this fact. In a case where boron of a P-type impurity is ion-implanted into a silicon substrate and an atmosphere where a cover oxide film is present and oxygen is not added (b1),
The impurity profiles obtained when RTA was performed in an atmosphere where oxygen was added without the cover oxide film (b2) and in an atmosphere where oxygen was not added without the cover oxide film (b3) were shown. Is shown. from now on,
Under each of the conditions, a relatively high concentration can be obtained and a low resistance can be achieved. However, under the condition (b2) where the cover oxide film exists, or under the atmosphere where oxygen is added, the cover oxide film is formed. RTA under the condition (b3) under which GaN is grown
It can be seen that in the treatment, the bonding depth of boron is increased.

As described above, when a P-type extension or an N-type extension is formed by using a P-type impurity and an N-type impurity independently, the above-described methods can be employed. Since the behaviors of the impurity and the N-type impurity are exactly opposite to each other, and the optimum annealing conditions for forming a shallow and high-concentration region are different in each case, the P-type It is difficult to form both the N-type and N-type extensions at a shallow junction and at a high concentration, and a problem arises in that a required CMOS structure cannot be manufactured.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can form an N-type diffusion layer and a P-type diffusion layer having shallow junction and low resistance by simultaneous annealing. It is another object of the present invention to provide an N-channel transistor having a shallow junction and a low-resistance N-type extension.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which is capable of manufacturing a semiconductor device having a CMOS structure having an OS transistor and a P-type extension having a low resistance and a shallow junction.

[0011]

According to the present invention, as an annealing treatment for activating a P-type impurity and an N-type impurity ion-implanted into a semiconductor substrate, the temperature is rapidly raised to a temperature at which TED occurs in an oxygen-added atmosphere; Thereafter, a step of suppressing the generation of OED is included. That is, the present invention suppresses outward diffusion of N-type impurities by an oxide film formed on the surface of the semiconductor substrate due to rapid temperature rise in the oxygen-added atmosphere, and suppresses OED, thereby suppressing the ion implantation. The feature is that the inward diffusion of the P-type impurity is suppressed. For example, the present invention is applied to manufacturing a shallow and low-resistance extension of each transistor in a semiconductor device having a CMOS structure having a PMOS transistor and an NMOS transistor.

As a typical annealing treatment of the present invention, first, a rapid temperature rise is performed from 900 ° C. to 1100 ° C.
It is characterized by an atmosphere in which oxygen is not added at the same time when the temperature reaches 00 ° C. to 1100 ° C. and a temperature lowering process is performed. Second
Is a rapid temperature increase from 900 ° C. to 1100 ° C. in an oxygen-added atmosphere within 1 second.
At 900 ° C in an atmosphere where oxygen is not added.
〜1100 ° C. is maintained for a required time. Third, the rapid temperature rise is from 900 ° C. to 1100 ° C., and within 1 second in an oxygen-added atmosphere.
1100 ° C. and then 80
A heat treatment at 0 ° C. is performed.

The operation of the present invention having the above features will be described. Conventionally, when a diffusion layer of an impurity is formed by ion implantation, TED (Tranjent Enhanced Diffusion) due to a point defect in a semiconductor substrate introduced by ion implantation.
) Is known to occur. Therefore, when this TED is compared with the above-described OED, which is an accelerated diffusion of P-type impurities by interstitial silicon supplied by oxidation of the semiconductor substrate, as shown in FIG. 1, the TED is generated from a relatively low temperature. , 1000 ° C
Its generation peaks at a moderately high temperature and disappears rapidly when the high temperature is reached. On the other hand, the amount of the OED is smaller than that of the TED, but is generated when the temperature reaches a high temperature near 1000, and continues to occur while this temperature state is maintained.

Therefore, in view of these phenomena, even if RTA (rapid heating annealing) is performed in an atmosphere in which oxygen does not exist, the accelerated diffusion due to TED cannot be suppressed. If originally, T
Since the accelerated diffusion by the ED occurs, the effect of the accelerated diffusion by the addition of oxygen can be reduced.
If the heat treatment is performed at a high temperature, for example, at a high temperature of 1000 ° C. or more, almost only diffusion by TED can be caused. Therefore, even in an oxygen-added atmosphere, by performing an RTA for an extremely short time, the N-type impurity is prevented from being outwardly diffused by the growth of the cover oxide film and is diffused only by the TED to form a shallow, high-concentration N-type diffusion layer. Can be formed. Regarding P-type impurities, even in an oxygen-added atmosphere, OED can be substantially suppressed while absorption by the cover oxide film is suppressed to a minimum, and a higher concentration and shallower than normal annealing for several tens of seconds. A P diffusion layer can be obtained.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 2 shows a semiconductor device having a CMOS structure, in particular, an N-channel MO having an extension.
FIG. 14 is a cross-sectional view showing an embodiment applied to the manufacture of a CMOS semiconductor device in which an S transistor and a CMOS transistor are constructed on the same substrate in the order of steps. First, as shown in FIG. 2A, an N-well 102 is formed in a required region of a P-type silicon substrate 101 by a known method, and then the surface of the silicon substrate 101 is selectively oxidized to form a LOCOS structure or a groove structure. An insulating film 103 for element isolation is formed, and the N well 1 is formed.
Each element forming region of the PMOS region 01 and the NMOS region in the P-type silicon substrate 101 is formed. In this embodiment, a groove structure is adopted as the element isolation insulating film 103, a groove is formed on the surface of the silicon substrate 101, and a silicon oxide film is embedded in the groove. Further, a gate insulating film 104 made of a silicon oxide film of about 10 nm is formed on the surface of the silicon substrate 101 in each of the element forming regions of the PMOS region and the NMOS region, and a required width dimension of about 300 nm is formed thereon. To form a gate electrode having a polycide structure made of low-resistance polycrystalline silicon or polycrystalline silicon and a refractory metal silicide. After formation of the gate electrode, the insulating film other than the portion to be the gate insulating film is removed using the gate electrode as a mask.

Next, as shown in FIG. 2B, while the NMOS region is selectively covered with a photoresist film 106, a P-type impurity, ie, boron is ion-implanted into the PMOS region to form a boron implanted layer 107. Form. Here, boron ions are implanted at a dose of 5E14 / cm ² and an energy of 0.5 KeV. Subsequently, FIG.
As shown in (c), the photoresist film 106 is removed, a new photoresist film 108 is formed, and the PMOS
An N-type impurity in the NMOS region;
Here, phosphorus is ion-implanted to form the phosphorus implantation layer 109. Here, the dose of phosphorus ions is 1E15 / c.
Ion implantation is performed at m ² and energy of 0.5 KeV.

Thereafter, the silicon substrate 101 is subjected to an RTA process to activate boron ions and phosphorus ions in each of the implanted layers 107 and 109, and as shown in FIG. A P-type extension 110 and an N-type extension 111 are formed, respectively. In this RTA process, a lamp annealing apparatus 200 as shown in FIG. 4 is used. The lamp annealing apparatus 200 includes a base member 201 and a cap 202.
And a processing chamber 2 whose interior is kept airtight.
03, a table 204 is provided.
The silicon substrate 101 to be subjected to the RTA process is mounted on the substrate 4. A gas supply port 205 is opened in the processing chamber 203 and connected to a gas supply source (not shown). Further, heating lamps 206 are arranged below the table 204 and outside the processing chamber 203 above the table 204, respectively, and by turning on these heating lamps 206, the silicon substrate 101 is rapidly heated. It is possible to do.

At this time, in the RTA process of this embodiment, the gas atmosphere in the processing chamber 203 is set to a nitrogen gas atmosphere containing 1000 ppm of oxygen, and as shown in FIG. Is heated at a heating rate of 100 ° C./sec from a state where it is previously heated to about 600 ° C. which does not contribute to activation, and when the temperature of the silicon substrate 101 reaches 1000 ° C., that is, a holding time for maintaining the temperature at 1000 ° C. Is immediately set to 0 seconds, the temperature is decreased at a rate of 50 ° C./sec, and a step of reducing the temperature to room temperature is executed. The P-type and N-type extensions 11 formed by performing the RTA process as described above.
The concentration profile was measured for 0,111.
FIG. 6 shows a P-type extension 110 using boron ions.
It was confirmed that the junction depth was about 25 nm and the sheet resistance was 1000 Ω / □. FIG. 7 shows a concentration profile of the N-type extension 111 due to phosphorus ions, and the junction depth is 5%.
It was confirmed that the thickness was about 0 nm and the sheet resistance was 250 Ω / □. Therefore, in the P-type extension 110, the junction depth can be formed to be shallower than the concentration profile shown in FIG. 13, while the P-type diffusion layer structure having a sheet resistance almost equal to that of the P-type extension 110 is formed. You can see that there is. Further, the N-type extension 111 can be formed to be as shallow as the junction depth in comparison with the concentration profile shown in FIG. 11, but has an N-type diffusion layer structure in which the sheet resistance is reduced by increasing the concentration. It can be seen that it is formed.

Next, after forming the P-type and N-type extensions 110 and 111 as described above, FIG.
As shown in FIG. 3A, a silicon oxide film is deposited on the entire surface, and the silicon oxide film is etched back by an anisotropic etching method to form sidewalls 112 on the side surfaces of the gate electrode 105. Then, FIG. 3 (b)
As shown in FIG.
In the PMOS region in a state of being selectively covered by
A high-concentration boron-implanted layer 114 is formed by ion-implanting a type impurity, that is, boron at a high concentration. Here, boron ions are dosed at 1E18 / cm ² and energy is 50K.
Ion implantation is performed at eV. Then, as shown in FIG.
The photoresist film 113 is removed, a new photoresist film 115 is formed to selectively cover the PMOS region, and an N-type impurity, here, arsenic is ion-implanted into the NMOS region to form a high-concentration arsenic implantation layer 116. Form. Here, arsenic ions are implanted at a dose of 1E18 / cm ² and an energy of 50 KeV. Then, FIG.
As described above, a second annealing process is performed to form a high-concentration P-type source / drain region 117 and a high-concentration N-type source / drain region 118. It should be noted that a conventional annealing method can be employed as it is for the second annealing process.

As described above, in this embodiment, when manufacturing the P-type and N-type extensions 110 and 111, boron and phosphorus are ion-implanted, respectively.
In an atmosphere containing a trace amount of oxygen, a very short time of 1000
Activating each ion by performing RTA treatment at ° C. causes accelerated diffusion of TED, but eliminates the high temperature state before the accelerated diffusion by OED occurs.
It is possible to suppress or prevent the accelerated diffusion by the OED. Therefore, the concentration of boron, which is an N-type impurity, is prevented from being reduced by a cover oxide film which is not shown in the drawing and is formed on the surface of the silicon substrate 101 by the treatment in the oxygen-added atmosphere, while the N-type extension 11 having a shallow junction is formed.
0 can be formed. Further, diffusion of phosphorus of the P-type impurity by the OED in the P-type impurity is suppressed, and the P-type extension 110 having a shallow junction can be formed. Note that, since the treatment is performed in an oxygen-added atmosphere, part of boron is taken into the cover oxide film by the cover oxide film generated as described above. The thickness of the generated cover oxide film is small, and the amount of boron incorporated is small.
It is possible to minimize the effect of the decrease in density on zero.

Here, RT in the first embodiment is used.
A second embodiment in which the conditions in the process A are different will be described. In the second embodiment, as shown in FIG.
As the RTA temperature diagram, the silicon substrate
After heating at a heating rate of about 100 ° C./second from about 00 ° C., the temperature is maintained for about 10 seconds, and then the temperature is reduced at a rate of 50 ° C./second to lower the temperature to room temperature. At the same time, at the time of heating and raising the temperature,
pm, and the holding time after reaching 1000 ° C. and the addition of oxygen were stopped in the temperature lowering process.
% Nitrogen gas atmosphere. The concentration profiles of the P-type and N-type extensions formed by performing the RTA process as described above were measured. The broken line in FIG. 6 is the concentration profile of the P-type extension due to boron ions, and it was confirmed that the junction depth was about 55 nm and the sheet resistance was 600 Ω / □. The broken line in FIG. 7 is the concentration profile of the N-type extension due to phosphorus ions, and it was confirmed that the junction depth was about 90 nm and the sheet resistance was 200 Ω / □.

When comparing the density profile of the second embodiment with the first density profile, in the second embodiment, in each of the P-type and N-type extensions,
In either case, the junction depth is slightly deeper than in the first embodiment, but the junction can still be made shallower as compared with the conventional concentration profiles shown in FIGS. 13 and 11, and on the other hand, in the first embodiment, It can be seen that the resistance can be reduced by increasing the concentration as compared with the form. Therefore, also in the second embodiment, a low-resistance extension can be formed with a shallower junction as compared with the related art. This is because, when the temperature is raised for an extremely short time in the RTA process, since the atmosphere is an oxygen-added atmosphere, a cover oxide film is formed on the surface of the silicon substrate, and outward diffusion of N-type impurities can be prevented. After that, since the atmosphere does not contain oxygen, the accelerated diffusion of the OED can be prevented, and the inward diffusion of the P-type impurity is suppressed by limiting only the accelerated diffusion by the TED.

Here, with respect to the holding state at 1000 ° C. in the above-mentioned RTA processing, a plurality of silicon substrate samples having different holding times were prepared by the present inventor, and the concentration profiles of the respective samples were compared. Figure 9
Shown in Here, boron, which is a P-type impurity, is used as the impurity, and a comparison is made between the case where the retention time is 0 second, 3 seconds, and 10 seconds. At the same time, a comparison is made between a 100% nitrogen atmosphere in which no oxygen is added and an atmosphere in which only 10% oxygen is added during the holding time. As a result, it can be seen that the longer the holding time, the deeper the junction, but the boron concentration at the junction is 0%.
It can be seen that the boron concentration increases greatly from 2 to 3 seconds, but the boron concentration does not increase significantly from 3 to 10 seconds. From this, it can be confirmed that if the holding time is set to 3 seconds or less, the required impurity concentration can be obtained while the junction depth is reduced. Further, although the junction depth is increased by the addition of oxygen, no remarkable difference is observed in the impurity concentration, and therefore, it is understood that it is not necessary to add oxygen during the holding time. Although FIG. 9 shows the case of boron, the same applies to N-type impurities such as arsenic and phosphorus.

The temperature, the holding time, and the mode of the holding in the RTA process have a correlation with each other, and are not limited to the conditions of the above-described embodiment. For example, as shown in FIG. 10, as a temperature program, as a first example, as shown in FIG. 10A, the temperature is raised to 1050 ° C. in an oxygen-added atmosphere, and then held within 3 seconds. Thereafter, the temperature may be lowered in an atmosphere to which oxygen is not added. Here, as shown in FIG. 9, there is no significant difference between an oxygen-added atmosphere and an atmosphere in which oxygen is not added within 3 seconds. Further, as shown in FIG.
After the temperature is raised to 00 ° C., the holding may be performed for 1 second or less in the oxygen-added atmosphere, and thereafter, the holding may be performed for 9 seconds in an atmosphere of 100% nitrogen. Further, FIG.
After the temperature is raised to 1000 ° C. in an oxygen-added atmosphere as described above, the temperature is maintained within 1 second, and then the temperature in the furnace of the RTA processing apparatus is lowered to 800 ° C. You may hold for about a minute. In particular, in this example, by lowering the temperature to 800 ° C., OED does not occur in the holding state.

The above description shows an example in which the present invention is applied to a method of manufacturing an extension of each of P-type and N-type MOS transistors which is a shallow junction and requires low resistance. If the semiconductor device is required to simultaneously form a low-resistance P-type diffusion layer and an N-type diffusion layer on one semiconductor substrate, the manufacturing method of the present invention is applied as a step of forming the impurity diffusion layer. It is possible to

[0026]

As described above, according to the present invention, in the annealing treatment for activating the P-type impurities and the N-type impurities, the temperature is rapidly raised to a temperature at which TED is generated in an oxygen-added atmosphere, and the generation of OED is thereafter performed. The process includes a step of suppressing out diffusion of N-type impurities by an oxide film formed on the surface of the semiconductor substrate due to a rapid temperature rise to TED, and suppressing the OED by suppressing the OED. By suppressing the inward diffusion of the doped P-type impurity, the P-type diffusion layer and the N-type diffusion layer can be formed with a shallow junction regardless of the difference in behavior between the P-type impurity and the N-type impurity during annealing. , And can be formed with low resistance. This makes it possible to manufacture a semiconductor device having a CMOS structure having a PMOS transistor and an NMOS transistor each having an extension.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the causes of TED and OED.

FIG. 2 is a first cross-sectional view of a manufacturing process of an embodiment for manufacturing a CMOS structure according to the present invention.

FIG. 3 is a second cross-sectional view of the manufacturing process of the embodiment for manufacturing the CMOS structure according to the present invention;

FIG. 4 is a schematic configuration diagram of an example of an RTA apparatus used in the present invention.

FIG. 5 is a temperature diagram of the first embodiment of the present invention.

FIG. 6 is a concentration profile diagram of a P-type extension by boron ions formed according to the present invention.

FIG. 7 is a concentration profile diagram of an N-type extension by phosphorus ions formed according to the present invention.

FIG. 8 is a temperature diagram of the second embodiment of the present invention.

FIG. 9 is a diagram showing a change in concentration profiling when a holding time and a gas atmosphere are changed.

FIG. 10 is a temperature diagram of different processing steps of the present invention.

FIG. 11 is a concentration profile diagram of a conventional N-type extension.

FIG. 12 is a diagram illustrating a relationship between a density and a sheet resistance in an N-type extension.

FIG. 13 is a concentration profile diagram of a conventional P-type extension.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 P-type silicon substrate 102 N well 103 Element isolation insulating film 104 Gate insulating film 105 Gate electrode 106 Photoresist film 107 Boron injection layer 108 Photoresist film 109 Phosphorus injection layer 110 P-type extension 111 N-type extension 112 Side wall 113 Photo Resist film 114 Boron implantation layer 115 Photoresist film 116 Arsenic implantation layer 117 P-type high concentration source / drain region 118 N-type high concentration source / drain region

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, comprising the steps of: ion-implanting a P-type impurity and an N-type impurity into a semiconductor substrate; and performing an annealing process for activating each of the implanted impurities. In an oxygen-added atmosphere, the temperature is rapidly raised to a temperature at which enhanced diffusion (TED) occurs due to point defects generated in the semiconductor substrate due to the ion implantation, and thereafter, oxidation of the semiconductor substrate is a factor. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of suppressing the occurrence of enhanced diffusion (OED). 2. An enhanced diffusion (OED) by suppressing outward diffusion of the ion-implanted N-type impurity by an oxide film formed on a surface of the semiconductor substrate by rapid temperature rise in the oxygen-added atmosphere. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the inward diffusion of the ion-implanted P-type impurity is suppressed by suppressing the diffusion. 3. The rapid temperature rise is to raise the temperature from 900 ° C. to 1100 ° C. and to add oxygen until the temperature reaches 900 ° C. to 1100 ° C., and to use an atmosphere in which oxygen is not added at least after reaching the temperature. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is reduced. 4. The rapid temperature rise from 900 ° C. to 1100 ° C. in an oxygen-added atmosphere within 1 second.
The method according to claim 1, wherein the semiconductor device is maintained at 0 ° C. to 1100 ° C. and further maintained at 1000 ° C. for a required time in an atmosphere in which oxygen is not added. 5. The rapid temperature rise from 900 ° C. to 1100 ° C. in an oxygen-added atmosphere within 1 second.
2. A heat treatment at a temperature of 0 DEG C. to 1100 DEG C., followed by a heat treatment at 800 DEG C. in an oxygen-added atmosphere.
Or a method for manufacturing a semiconductor device according to item 2. 6. A step of forming a gate electrode in each of a PMOS formation region and an NMOS formation region partitioned on a semiconductor substrate, a step of selectively ion-implanting a P-type impurity into the PMOS formation region, and A step of selectively ion-implanting an N-type impurity into a formation region; a step of performing a first annealing process for activating the P-type impurity and the N-type impurity to form respective extensions;
Forming a sidewall on a side surface of the gate electrode in each of the MOS formation regions, selectively implanting high-concentration P-type impurities into the PMOS formation region,
A step of selectively implanting high-concentration N-type impurities into the MOS formation region and a second annealing process for activating the P-type impurities and N-type impurities are performed to form high-concentration source / drain regions. Wherein the first annealing is performed in an oxygen-added atmosphere by enhanced diffusion (TED) caused by point defects generated in the semiconductor substrate by ion implantation of the P-type and N-type impurities. A method for rapidly increasing the temperature to a temperature at which the semiconductor substrate is generated, and thereafter suppressing the occurrence of enhanced diffusion (OED) caused by oxidation of the semiconductor substrate.