JP2000101424A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a clock-generating circuit that realizes spread spectrum processing for a clock signal and reduces the radiation of electromagnetic waves by shifting only slightly an operating clock signal of a semiconductor device. SOLUTION: A phase comparator 10 of a PLL circuit compares a phase of a received reference clock signal SIN with a phase of a frequency division signal SD from a frequency divider 50, outputs an up-down signal SUD in response to a phase difference of the signals, a low-pass filter 20 eliminates a high frequency component of the up-down signal SUD and provides an output of a signal SL, consisting of low frequency components. A DC amplifier 30a generates a control signal SV resulting from adding a bias signal, in response to a frequency control signal SC1 to the signal SL and gives the signal SV to a VCO 40, the VCO 40 oscillates at a frequency set by the control signal SV and generates a clock signal CK0, whose frequency is transited in response to the frequency control signal SC1 and gives it to a semiconductor device as an operating clock signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit for generating a clock signal having a fluctuating frequency to reduce electromagnetic wave radiation.

[0002]

2. Description of the Related Art In recent years, the highest operable frequency of a semiconductor device has been increased by the progress of semiconductor manufacturing technology. For example, as an example, the operating clock frequency of a CPU (central processing unit) widely used in personal computers has been increased from around 10 MHz at the beginning of development to 200 to 300 MHz.
z has been reached. For this reason, many semiconductor devices that can operate at high speed have been realized.

[0003]

As described above, one of the problems brought about by the improvement in the operating frequency of the semiconductor device is electromagnetic wave radiation. As the frequency increases,
When the wavelength of the high-frequency signal is shortened and the wiring length inside the connection circuit or the board is almost the same as the wavelength of the high-frequency signal, the connection part such as the wiring inside the board functions as an antenna, and the electromagnetic radiation to the surroundings rapidly increases. There is a disadvantage that it increases.

[0004] Electromagnetic radiation of electronic devices using semiconductor elements that operate with high-speed clock signals causes malfunctions due to mutual interference between electronic devices, interference with communication devices, and the like.
There are also concerns about the effects on the human body. At present, measures have been taken to reduce the electromagnetic radiation by improving the circuit layout, etc., and to reduce the leakage of electromagnetic waves to the surroundings by shielding the electromagnetic waves for electronic devices where electron radiation is a problem. . However, when a mobile device is required to be reduced in size and weight, a shield for reducing electromagnetic wave radiation cannot be sufficiently provided, and there is almost no effective method for preventing electromagnetic wave radiation.

The present invention has been made in view of the above circumstances, and an object of the present invention is to make it possible to realize a spread spectrum of a clock signal by making a small transition of an operation clock signal of a semiconductor device and to reduce electromagnetic wave radiation. Another object of the present invention is to provide a clock generation circuit that generates a simple clock signal.

[0006]

In order to achieve the above object, a clock generation circuit according to the present invention integrates an input clock signal and makes the slope of a level change with respect to time at the rise and fall of the clock signal gentle. An integration circuit that outputs the integrated clock signal, and a second level that limits the level of the integrated clock signal according to a frequency control signal that changes its level at a lower frequency than the input clock signal, and changes the frequency according to the frequency control signal. A limiter circuit for outputting a clock signal of
And a frequency multiplying circuit for outputting a clock signal obtained by multiplying the frequency of the clock signal by a predetermined multiplication ratio.

In the present invention, preferably, the frequency multiplying circuit compares the phase of the second clock signal and the frequency-divided signal, and outputs a phase difference signal according to the comparison result. And an amplifier circuit for outputting an oscillation control signal having a predetermined level in accordance with the phase difference signal; and a voltage control for oscillating at an oscillation frequency set by the oscillation control signal and outputting the oscillation signal as a clock signal obtained by multiplying the oscillation signal. An oscillation circuit and a frequency dividing circuit for dividing the frequency of the multiplied clock signal by a predetermined frequency dividing ratio and outputting the frequency divided signal to the phase comparing circuit.

Further, the clock generation circuit of the present invention compares the phases of the input clock signal and the divided signal, and outputs a phase difference signal whose level changes according to the phase difference between the input clock signal and the divided signal. A phase comparison circuit, an amplification circuit that outputs an oscillation control signal obtained by adding a bias voltage corresponding to the level of the frequency control signal to the phase difference signal, oscillates at an oscillation frequency set by the oscillation control signal, and generates a clock signal. A voltage-controlled oscillation circuit that outputs the clock signal; and a frequency-dividing circuit that divides the clock signal at a predetermined frequency-division ratio and outputs the frequency-divided signal to the phase comparison circuit.

Further, the clock generation circuit of the present invention compares the phase of the input clock signal with the phase of the divided signal, and outputs a phase difference signal corresponding to the phase difference between the input clock signal and the divided signal. A charge pump circuit that generates a charge or discharge current according to the phase difference signal and the frequency control signal and outputs an oscillation control signal from a capacitor that charges and discharges according to the charge or discharge current; and A voltage-controlled oscillation circuit that oscillates at a set oscillation frequency and outputs a clock signal; and a frequency divider that divides the clock signal by a predetermined frequency division ratio and outputs a frequency-divided signal to the phase comparator. .

According to the present invention, the clock generation circuit generates a clock signal whose frequency slightly changes so as not to affect the normal operation of the semiconductor device, and supplies the clock signal to the semiconductor device as an operation clock signal. Spreading the frequency spectrum of a signal reduces electromagnetic radiation of the semiconductor device. Specifically, for example, by limiting the integrated clock signal from the frequency control signal whose level changes more slowly than the input clock signal, a clock signal whose frequency changes is generated, and according to the clock signal, A PLL circuit generates a clock signal multiplied by a predetermined multiplication number and supplies the clock signal to the semiconductor device.

Further, the clock generation circuit of the present invention has a PLL
A DC amplifier circuit configured to generate a control signal to be supplied to a VCO in the PLL circuit, for example, in a differential amplifier circuit, a phase comparison circuit is input to one input terminal, and a frequency control signal is input to the other input terminal. Is input, the oscillation control signal input to the VCO includes a bias component corresponding to the oscillation frequency, and the oscillation frequency of the VCO is controlled to transition according to the frequency control signal. Further, in the charge pump constituting the PLL circuit, a bias voltage is generated according to the frequency control signal, and the bias current is added to the current generated according to the phase difference signal. The oscillation frequency of the controlled VCO changes according to the frequency control signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of the clock generator according to the present invention. The clock generation circuit according to the present embodiment includes an integrator 1, a limiter 2, a PLL circuit 3, and a frequency divider 4.

The integrator 1 receives the input clock signal CK
By integrating the _IN, and outputs the integrated clock signal CK _S. The limiter 2 receives the integrated clock signal CK _S and the frequency control signal S _C and receives a PLL signal in accordance with these signals.
The clock signal S _IN to be input to the circuit 3 is output. PLL
The circuit 3 receives the clock signal S _IN input from the limiter 2
And the frequency-divided signal _SD input from the frequency divider 4,
For example, it outputs a clock signal CK _OUT whose frequency or phase is controlled according to the clock signal S _IN .

The frequency control signal S input to the limiter 2
Output clock signal CK _OUT of PLL circuit 3 according to _C
By making the output transition with a small fluctuation range,
The spectrum of the clock signal CK _OUT is spread. Therefore, in a semiconductor device that operates using the clock signal CK _OUT as the operation frequency, the spectrum of the operation clock signal is dispersed, so that the reduction of electromagnetic wave radiation can be realized.

FIG. 2 shows an example of the configuration of a PLL circuit 3 including a frequency divider. As illustrated, the PLL circuit 3 includes a phase comparator 10, a low-pass filter (LPF) 20, a DC amplifier 30, a voltage-controlled oscillator (VCO) 40, and a frequency divider 50. The frequency divider 50 in FIG. 2 is the same as the frequency divider 4 shown in FIG.

The phase comparison circuit 10 compares the phase of the frequency-divided signal S _D from the frequency-dividing circuit 50 with the phase of the clock signal S _IN input from the limiter 2, and outputs an up-down signal S indicating the phase difference between these signals. Output _UD . Low-pass filter 20
Removes a high-frequency component contained in the up-down signal S _UD from the phase comparator 10, and outputs a signal S _L comprising only the low-frequency component. DC amplifier 30, as shown, an inverting amplifier circuit consisting of a differential amplifier AMP and resistive elements R1, R2, amplifies the low-frequency signal S _L from the low-pass filter 20, the signal to a predetermined further amplified The signal S _V to which the DC level V _dc is added is used as a control signal and VC
Output to O40. VCO40 oscillates at a controlled oscillation frequency by a control signal S _V from the DC amplifier 30,
Outputs oscillation signal. The oscillation signal output by the VCO40 is supplied to another semiconductor device as an operation clock signal CK _O. Divider 50 divides a frequency division ratio set in advance the clock signal CK _O from VCO 40,
The divided signal _SD is output to the phase comparator 10.

FIG. 3 shows signal waveforms of respective partial circuits of the clock generation circuit according to the present embodiment. Hereinafter, FIGS. 1 to 3
The operation of the clock generation circuit according to the present embodiment will be described with reference to FIG.

The frequency control signal S _C input to the limiter 2 in FIG. 1 is, for example, a triangular wave having a predetermined period, as shown in FIG. The triangular wave is a low-frequency signal whose frequency is considerably lower than that of the input clock signal CK _IN and changes gradually. Here, a triangular wave signal is shown as an example, but the frequency control signal S _C is not limited to a triangular wave, and may be another signal, for example, a sine wave or a signal whose level changes stepwise. May be.

A clock signal CK _IN having a constant period T shown in FIG. 3B is input to the integrator 1 and the result of integration is
Integrating the clock signal CK _S shown in (c) is obtained.
In the limiter 2, as a result of limiting the level of the integrated clock signal CK _S using the frequency control signal S _C , a clock signal whose period constantly changes as shown in FIG. The clock signal is PL as the input signal S _IN
It is supplied to the L circuit 3.

The PLL circuit 3 has a frequency division ratio n (n
The multiplies the frequency of the input signal S _IN in multiplication number set by a positive integer) generates a clock signal CK _O. For example, if the frequency of the input signal S _IN is f, the output clock signal CK
The frequency of _O is nf. Frequency changes of the input signal S _IN, and for example, at the (f + Δf), and following it also the frequency of the output clock signal CK _O, changes (nf + nΔf). As described above, the limit of the result integration clock signal CK _S in accordance with the frequency control signal S _C in the limiter 2, the frequency of the resulting signal S _IN is controlled according to the level of the frequency control signal S _C. Therefore, PLL
The output clock signal CK frequencies _O be the control signal S of the circuit 3
Controlled by _C level. That is, the clock generation circuit of the present embodiment functions as a kind of frequency modulation circuit,
Serve the modulation function with respect to the frequency of the input clock signal CK _IN using a frequency control signal S _C, it is possible to provide a clock signal CK _O whose frequency varies.

[0021] The clock generation circuit of the present embodiment, the clock signal CK _O which changes its frequency according to the frequency control signal S _C is generated. In another semiconductor device that operates the clock signal CK _O as the operation clock signal,
Since the spectrum of the clock signal is spread, electromagnetic radiation can be significantly reduced. FIG. 4B shows the spectrum of a clock signal subjected to spread spectrum. For comparison, FIG. 9A shows the spectrum of the clock signal CK without spread spectrum.

As shown in FIG. 4A, when the spread spectrum is not performed, the spectrum of the clock signal CK has almost the center frequency f _CK except for a portion slightly spread on both sides due to noise components or the like. Is focused on On the other hand, the spectrum of the clock signal, the spectrum of which has been spread by the clock generation circuit of the present embodiment, spreads widely on both sides around the frequency f _CK as shown in FIG. It is greatly reduced as compared with the spectrum shown in FIG. by this,
In the semiconductor device operating at a clock signal CK _O was supplied at a clock generation circuit of the present embodiment, it is possible to electromagnetic radiation is greatly reduced, even if the shield such measures it is difficult for, to device around It is possible to greatly reduce leakage of electromagnetic waves.

Second Embodiment FIG. 5 is a circuit diagram showing a second embodiment of the clock generation circuit according to the present invention. The first of the clock generation circuits described above
In the embodiment, a clock signal having a frequency transition is generated by limiting the level of a clock signal integrated with a frequency control signal S _C whose level changes slowly using a limiter, and the clock signal is subjected to a predetermined multiplication ratio. in generating a multiplied clock signal CK _O. For this reason, an integrator is required in addition to the limiter, and there are many additional circuits other than the PLL circuit, which increases the cost of the circuit.

On the other hand, in the clock generation circuit of the present embodiment, a frequency-spread clock can be generated using only the PLL circuit to generate a spread-spectrum clock. A signal can be generated, and a downsized and inexpensive clock generation circuit can be realized. Hereinafter, the configuration and operation of the clock generation circuit of the present embodiment will be described with reference to FIG.

As shown in FIG. 5, the PLL circuit constituting the clock generating circuit of the present embodiment has substantially the same configuration as the PLL circuit 3 shown in FIG. However, in the present embodiment, the frequency control signal S _C1 whose level changes is input to the differential amplifier AMP constituting the DC amplifier 30a, thereby controlling the level of the control signal S _V output from the DC amplifier 30a, The oscillation frequency of the VCO 40 is controlled.

The clock signal S _IN and the frequency-divided signal _SD from the frequency divider 50 are input to the phase comparator 10 constituting the PLL circuit. The clock signal S _IN is, for example, a reference clock signal having a stable frequency. The phase comparator 10 compares the phases of the input clock signal S _IN and the frequency-divided signal _SD, and outputs an up-down signal _SUD according to the phase difference between these signals. The low-pass filter 20
Removing the high-frequency component included in the up-down signal S _UD from the phase comparator 10, and outputs a signal S _L comprising only the low-frequency component.

The DC amplifier 30a is, for example, made up of a differential amplifier AMP, the differential amplifier AMP low-frequency signal S _L from the low-pass filter 20 through a resistor element R1
Of the differential amplifier AMP via the resistance element R2.
Output terminal. The frequency control signal S _C1 is input to the input terminal “+” of the differential amplifier AMP. As shown, the frequency control signal S _C1 is a signal obtained by _adding a bias voltage ΔV to a DC level V _dc and, for example, FIG.
It is a triangular wave shown.

[0028] Thus, the inverting amplifier circuit is constituted by a differential amplifier AMP and resistive elements R1, R2, bias signals S _C1 to the inverted signal of the input signal S _L from the output terminal
Is added signal S _V is outputted and supplied to the VCO 40. Here, the voltage of the output signal S _L of the low pass filter 20 and V _L, when the voltage of the signal S _V and V _S, the following equation holds.

[0029]

[Number 1] _{V L = (V dc + ΔV} ) - (V S -V dc -ΔV) · R1 / R2 = (V dc + ΔV) (R1 + R2) / R2-V S R1 / R2 ... (1)

[0030] VCO40 is the control signal S _V output from the DC amplifier 30a, the oscillation frequency is controlled, the clock signal CK _O having the oscillation frequency is outputted.
Therefore, the oscillation frequency of the VCO 40 is
The transition is made in accordance with the level change of the frequency control signal S _C1 input to “a”. That is, the spectrum of the output clock signal CK _O is diffused.

[0031] Thus, the results obtained by adding a bias signal S _C1 to the differential amplifier circuit AMP, the voltage level of the output signal S _L of the low pass filter 20 is a PLL circuit so that the voltage V _L shown in Formula (1) Operate. As a result, the oscillation frequency of the VCO 40 changes according to the level of the bias signal S _C1 applied to the differential amplifier AMP.

[0032] the clock signal CK _O operation clock signal, the other semiconductor device is supplied, the electromagnetic radiation of a semiconductor device that operates in the clock signal CK _O is greatly reduced.

As described above, according to the present embodiment, the reference clock signal S _IN input by the phase comparator 10 and the divided signal S _D from the frequency divider 50 in the PLL circuit.
It compares the phases of the outputs up-down signal S _UD in accordance with the phase difference of these signals, the low pass filter 20 removes the high frequency components and outputs a signal S _L composed of a low-frequency component. DC amplifier 30a generates a control signal S _V to bias the frequency control signal S _C1 inputted, VCO
40. VCO40 oscillates at a frequency set by the control signal S _V, generates a clock signal CK _O frequency transitions in response to the frequency control signal S _C1, since the supply to the semiconductor device as the operation clock signal, the spread spectrum clock signal Electromagnetic radiation of a semiconductor device operating on a semiconductor device can be reduced.

Third Embodiment FIG. 6 is a circuit diagram showing a third embodiment of the clock generation circuit according to the present invention. As shown in the figure, the clock generation circuit of this embodiment generates a clock signal having a frequency transition using a PLL circuit, similarly to the second embodiment of the present invention shown in FIG. However, in the present embodiment, the charge pump 60 operating in response to the output signal of the phase comparator 10a generates a predetermined bias current with the frequency control signal S _C2 , thereby controlling the level of the signal S _L , thereby enabling the VCO 40 Control the oscillation frequency of

Signal S input to phase comparator 10a
_IN is, for example, a reference clock signal having a predetermined frequency. The phase comparator 10a receives the reference clock signal S _IN
And the phase of the frequency-divided signal _SD from the frequency divider 50, and outputs an up signal S _UP or a down signal S _DW according to the comparison result. These output signals are, for example, pulse signals whose widths are controlled in accordance with the phase difference between the reference clock signal S _IN and the frequency-divided signal _SD . For example, the reference clock signal S
_{When IN} has a phase advanced from the divided signal _SD , an up signal S _UP which is a pulse signal having a width corresponding to the phase difference between these signals is output, and conversely, the reference clock signal S _IN is divided. When the phase is delayed from the signal S _D , the down signal S which is a pulse signal having a width corresponding to the phase difference between these signals.
_DW is output.

The charge pump 60 generates a charge current i _C according to the up signal S _UP or the down signal S _DW . Further, a bias current Δi _C is generated according to the input frequency control signal S _C2 and added to the charge current i _C. Therefore, the charge current i _C and the bias current Δ
i _C depending on the sum (i _C + Δi _C) of the capacitor C1 is charged or discharged, the signal S _L level in response to the charging and discharging of the capacitor C1 is controlled is output.

The DC amplifier 30 amplifies the signal S _L that is output from the charge pump 60 is supplied to the VCO40 The resulting signal S _V as the control signal. Note that the DC amplifier 30 of the present embodiment is, for example, a PLL circuit 3 shown in FIG.
May have the same configuration as that of the DC amplifier.
VCO40 oscillates at a controlled oscillation frequency by the control signal S _V, and outputs an oscillation signal. The oscillation signal as an operation clock signal CK _O, supplied to the semiconductor device. Divider 50 divides a frequency division ratio n which is set in advance the clock signal CK _O generated by VCO 40, and generates a divided signal S _D, is input to the phase comparator 10a.

FIG. 7 is a circuit diagram showing an example of the configuration of the charge pump 60. As shown, the charge pump 60
Are a pnp transistor P1 and an npn transistor Q connected in series between the power supply voltage _Vdd and the ground potential GND.
1 and a pnp transistor P2 and an npn transistor Q2, and resistance elements R3, R4, R5 and R6 connected to the emitters of these transistors.

The transistor P1 has a resistor R
3 via is connected to a power supply voltage V _dd, the up signal S _UP from the phase comparator 10a is input to the gate. The emitter of the transistor Q1 is grounded via the resistor R4,
The down signal S _DW from the phase comparator 10a is input to the gate. The collectors of the transistors P1 and Q1 are connected to the node ND.
1 connected. The emitter of the transistor P2 is connected to the power supply voltage _Vdd via the resistor R5, and the collector is connected to the node ND1. The emitter of the transistor Q2 is grounded via the resistance element R6, and the collector is connected to the node ND1. Further, the frequency control signal S _C2 is input to the gates of the transistors P2 and Q2. Capacitor C1 is connected between node ND1 and ground potential GN.
D.

When an up signal S _UP , for example, a low-level pulse signal is input from the phase comparator 10a, a current I ₁ flows through the transistor P1 and is input to the node ND1. On the other hand, when a down signal S _DW , for example, a high-level pulse signal is input from the phase comparator 10a, a current I ₂ flows through the transistor Q1. Capacitor C1, when the current I ₁ is input to the node ND1, is charged by the current, the potential of the node ND1 rises. vice versa,
When the current _{I 2} flows from the node ND1 to the transistor Q2, the node ND1 is discharged, the node ND1
Potential drops. Therefore, the capacitor C1 is charged or discharged according to the comparison result of the phase comparator 10a, and the voltage of the node ND1 is controlled.

On the other hand, according to the level of the frequency control signal _SC2 input to the gates of the transistors P2 and Q2, the current flowing through these transistors is controlled. For example, when the level of the frequency control signal S _C2 decreases, the current I ₃ flows through the transistor P2, and the capacitor C1 is charged accordingly. On the other hand, the frequency control signal S _C2
When the level of increases, the current I ₄ flows through the transistor Q2, the capacitor C1 in response thereto is discharged. Therefore, the capacitor C1 is charged or discharged according to the level of the frequency control signal S _C2 , and the voltage of the node ND1 is controlled.

As described above, in the charge pump 60, the voltage of the node ND1, that is, the output of the charge pump 60, according to the up signal S _UP or the down signal S _DW and the frequency control signal S _C2 from the phase comparator 10a. level of the signal S _L is controlled. The signal S _L VCO 40 as later control signal S _V amplified by a DC amplifier 30
Is input to As a result, the oscillation frequency of the VCO 40 is controlled by the frequency control signal S _{C2 in} addition to the up signal S _UP and the down signal S _DW from the phase comparator 10a.

The frequency control signal S _C2 which is input to the charge pump 60, for example, when a triangular wave shown in FIG. 3 (a), the output clock signal CK _O of VCO40 is gentle frequency in response to the level change of the triangular wave Transitions to. Therefore, in the semiconductor device to a clock signal CK _O and the operating clock, the spectrum of the clock signal is spread, the electromagnetic radiation is greatly reduced.

As described above, according to the present embodiment, the phase comparator 10a receives the input reference clock signal S
_It compares the phases of _IN and the frequency-divided signal _SD from the frequency divider 50, and outputs an up signal S _UP or a down signal S _DW according to the phase difference between these signals. The charge pump 60 is a charge or discharge current generated in response to the output signal and the frequency control signal S _C2 of the phase comparator 10a, the capacitor C1 is charged or discharged in response thereto, to control the level of the signal S _L. Amplifies the signals S _L by the DC amplifier 30 generates a control signal S _V, VCO 4
Is supplied to the 0, VCO 40 oscillates at a frequency set by the control signal S _V, since the output clock signal CK _O, frequency of the clock signal CK _O transitions in response to a level change of the frequency control signal S _C2, Since the spectrum is spread, the electromagnetic wave radiation of the semiconductor device using this as an operation clock is greatly reduced.

[0045]

As described above, according to the clock generation circuit of the present invention, the frequency of the generated clock signal changes gradually, so that its spectrum is spread and the semiconductor device which operates accordingly. There is an advantage that electromagnetic radiation can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a clock generation circuit according to the present invention.

FIG. 2 shows a PLL constituting the clock generation circuit shown in FIG. 1;
FIG. 3 is a circuit diagram illustrating a configuration example of a circuit.

FIG. 3 is a waveform diagram illustrating an operation of the clock generation circuit according to the first embodiment.

FIG. 4 is a diagram illustrating a spectrum of a clock signal.

FIG. 5 is a circuit diagram showing a second embodiment of the clock generation circuit according to the present invention.

FIG. 6 is a circuit diagram showing a third embodiment of the clock generation circuit according to the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a charge pump forming the clock generation circuit shown in FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Integrator, 2 ... Limiter, 3 ... PLL circuit, 4 ... Divider, 10, 10a ... Phase comparator, 20 ... Low-pass filter, 30, 30a ... DC amplifier, 40 ... VCO, 50 ...
Frequency divider, 60: charge pump, V _dd : power supply voltage, GN
D: ground potential.

Claims (7)

[Claims] An integrating circuit for integrating an input clock signal and outputting an integrated clock signal having a gradual level change gradient with respect to time at rising and falling of the clock signal; and a frequency lower than the input clock signal. A limiter circuit that limits the level of the integrated clock signal in accordance with the frequency control signal whose level changes in accordance with the above, and outputs a second clock signal whose frequency changes in accordance with the frequency control signal; A frequency multiplying circuit for outputting a clock signal frequency-multiplied by a multiplication ratio. 2. The frequency multiplying circuit according to claim 1, wherein said frequency multiplying circuit compares a phase of said second clock signal with a phase of said frequency-divided signal, and outputs a phase difference signal according to the comparison result. An amplification circuit that outputs an oscillation control signal having a predetermined level, and oscillates at an oscillation frequency set by the oscillation control signal,
A voltage-controlled oscillation circuit that outputs an oscillation signal as the frequency-multiplied clock signal; and a frequency-dividing circuit that frequency-divides the frequency-multiplied clock signal at a predetermined frequency-division ratio and outputs the frequency-divided signal to the phase comparison circuit. The clock generation circuit according to claim 1. 3. A phase comparison circuit for comparing the phases of an input clock signal and a divided signal and outputting a phase difference signal whose level changes in accordance with the phase difference between the input clock signal and the divided signal. An amplifier circuit that outputs an oscillation control signal obtained by adding a bias voltage according to the level of the frequency control signal to the phase difference signal;
A clock generation circuit comprising: a voltage-controlled oscillation circuit that outputs an oscillation signal; and a frequency division circuit that divides the clock signal by a predetermined frequency division ratio and outputs a frequency-divided signal to the phase comparison circuit. 4. The amplifier circuit according to claim 3, wherein said amplifier circuit is constituted by a differential amplifier circuit in which said phase difference signal is inputted to one input terminal and said frequency control signal is inputted to the other input terminal. Clock generation circuit. 5. The clock generation circuit according to claim 3, further comprising a low-pass filter that attenuates high frequency components of the phase difference signal from said phase comparison circuit, extracts low frequency components, and outputs the low frequency components to said amplification circuit. 6. A phase comparison circuit for comparing the phases of an input clock signal and a frequency-divided signal and outputting a phase difference signal corresponding to a phase difference between the input clock signal and the frequency-divided signal; A charge pump circuit that generates a charge or discharge current according to the control signal and outputs an oscillation control signal from a capacitor that charges and discharges according to the charge or discharge current; and oscillates at an oscillation frequency set by the oscillation control signal.
A clock generation circuit comprising: a voltage-controlled oscillation circuit that outputs a clock signal; and a frequency division circuit that divides the clock signal by a predetermined frequency division ratio and outputs a frequency-divided signal to the phase comparison circuit. 7. A charge pump circuit according to claim 1, wherein said charge pump circuit generates a first current in response to a phase difference signal from said phase comparison circuit, and outputs the first current to a connection terminal. A second current generating circuit for generating a second current and outputting the second current to the connection terminal; one electrode connected to the connection terminal, the other terminal grounded; By charging or discharging according to the voltage of the connection terminal,
7. A capacitor for supplying the voltage of the connection terminal as the oscillation control signal to the voltage controlled oscillation circuit.
A clock generation circuit as described.