JP2000101408A - Gate drive circuit for power semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain quick protection processing or proper gate voltage suppression for a power semiconductor element. SOLUTION: A 2nd gate drive circuit 2, using a gate voltage of a power semiconductor element for its power supply, is placed between a gate current input output terminal of a power semiconductor element and a 1st gate drive circuit 1, and the 2nd gate drive circuit 2 is provided with an amplifying means that amplifies the difference voltage between a detected gate voltage of the power semiconductor element and the reference voltage or the detected gate voltage and a voltage, that varies with an output voltage of a 1st gate drive circuit 1 and with a variable resistive element that changes a resistance of a resistor means, provided in parallel with the gate current input output terminal. Thus, a short-circuit current is decreased or dV/dt at switching is suppressed down to a desired value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit for a power semiconductor device such as an IGBT, and more particularly to a driving circuit for suppressing a gate voltage or a gate current when switching a large current such as an overcurrent.

[0002]

2. Description of the Related Art In a large-capacity power converter, an IGBT is used.
Low-loss, high-speed switching type power devices such as (insulated gate bipolar transistors) are becoming mainstream. The IGBT has a large current limited by the gate voltage, and can pass a current of 5 to 10 times the device rated current for a short time of about 10 μs. However, when such a large current is suddenly cut off, a spike voltage is generated which is determined by the product of the current time change (di / dt) and the parasitic inductance of the wiring, and this voltage exceeds the breakdown voltage limit of the device, and the device is destroyed. There is a problem to invite.

As a method of interrupting an overcurrent without destroying the device, for example, a method disclosed in Japanese Patent Publication No. 5-31323 discloses a method in which a diode is provided between the gate of an IGBT and a control power supply, and the gate voltage is reduced when the overcurrent occurs. A clamp method is described which prevents the voltage from increasing beyond the control power supply voltage. Further, the method disclosed in U.S. Pat. No. 5,210,479 describes a method of detecting a collector voltage and a gate voltage of an IGBT, respectively, and gradually decreasing the gate current when both of them become equal to or more than a predetermined value.

Another problem that causes high-speed switching of the IGBT is that a voltage time change (dV / dt) generated at the time of switching causes a high-frequency leakage current, which causes electromagnetic interference. Voltage change over time (dV / d
A method for suppressing t) by a driving circuit is described in Japanese Patent Application Laid-Open No. Hei 6-291163. This method detects the gate voltage and the collector voltage of the IGBT, and turns on and off according to these values.
And a method of changing the gate resistance at the time of turn-off.

[0005]

The gate voltage clamping means represented by Japanese Patent Publication No. 5-31323 is effective for determining the upper limit of the voltage. However, when the overcurrent is cut off, the gate voltage of the IGBT is reduced to the rated voltage (15).
If you want to suppress continuously from V) to several V,
This method without control means is not suitable.

US Pat. No. 5,210,479 or JP-A-6-2916
The method of varying the output of the gate voltage itself as in No. 3 is effective in applications in which overcurrent is cut off in a state where the gate drive circuit and the IGBT module are close to each other. However, when the wiring length between the output terminal of the gate drive circuit and the gate terminal of the IGBT becomes long, the gate drive circuit may not be able to suppress the gate voltage of the IGBT due to the parasitic inductance. A prominent example is a period during which the feedback capacitance is charged and discharged during switching. The IGBT has a feedback capacitance between the collector terminal and the gate terminal, and at the time of turn-off, a displacement current determined by a voltage time change (dV / dt) and the feedback capacitance flows into the gate terminal to increase the gate voltage. Here, when the wiring length between the gate drive circuit and the IGBT is long, the gate drive circuit cannot rapidly control the gate voltage increased by the displacement current due to the impedance of the parasitic inductance. This period is on the order of several μs, but its influence is great. For example, if an inverter in which the IGBTs are connected to a bridge causes an arm short circuit in which the upper and lower IGBTs are simultaneously turned on, the current becomes several times the rated value or more in a period of several μs. Therefore, when an abnormality is detected, it is desirable that the gate drive circuit immediately suppresses the gate voltage of the IGBT. In a large-capacity converter in which the power supply voltage exceeds 1 kV, the gate wiring length may reach several meters, and it is not easy to cut off the overcurrent. In addition, even if the cutoff current is equal to or less than the rated value, when trying to suppress dV / dt, the effect of a delay of several μs is large, and it becomes difficult to suppress the rise in the collector voltage due to a change in the gate voltage. Further, US Pat. No. 5,210,47 discloses a plurality of IGBT modules connected in parallel.
The problem is complicated when the No. 9 gate drive circuit is commonly used. That is, at the time of short-circuit, one of the plurality of IGBTs connected in parallel is often short-circuited first. In this case, it is necessary to change the degree of suppression of the gate voltage between the first short-circuited IGBT and the short-circuited IGBT. For such processing, a gate suppression circuit having a short delay time is required.

[0007] An object of the present invention is to provide a delay time even when a wiring length between a gate drive circuit and an IGBT module is long or a plurality of IGBTs are connected in parallel as in a large-capacity power converter. It is another object of the present invention to provide a gate drive circuit in which the suppression of the gate voltage is started and the overcurrent cutoff or the dV / dt suppression is achieved.

[0008]

According to a first aspect of the present invention, there is provided a power supply device comprising: a gate current input / output terminal of a power semiconductor device and a first gate drive circuit; Amplifying means for providing a drive circuit for amplifying a difference voltage between a gate voltage detection value of the power semiconductor element and a reference voltage, or a difference voltage varying according to an output voltage of the first gate circuit; A variable resistance element for changing a resistance value of a resistance means provided in parallel with the gate current input / output terminal according to the output of the gate drive circuit. This is achieved by providing an amplifying unit for amplifying a difference voltage between the first and second gates, and a variable resistance element for changing a resistance value of a resistance unit provided in parallel with the gate current input / output terminal according to an output of the amplifying unit. .

Further, the first gate drive circuit includes second voltage detecting means for detecting a voltage between the input and output terminals of the power semiconductor element, and an output of the second voltage detecting means and the second gate detecting means. When the output of the amplifying means provided in the drive circuit is in a predetermined state, there is no delay time by suppressing the positive or negative gate current supplied from the first gate drive circuit to the power semiconductor element. Gate voltage suppression can be achieved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention for achieving overcurrent protection of a power semiconductor device. In FIG. 1, Q
Reference numeral 1 denotes an IGBT, a region 1 surrounded by a broken line is a first gate drive circuit, and a region 2 provided in parallel between the gate and the emitter terminal of the IGBT is a second gate drive circuit. First,
The second gate drive circuit which is a feature of the present invention will be described. In a region 2, resistors R1 and R2 are connected in series between the gate and the emitter terminal of the IGBT in parallel.
1 and the capacitor of C2 are connected. R1 and R2 give I
The gate-emitter voltage Vge (hereinafter abbreviated as gate voltage) of the GBT is divided. C1 and C2 are for vibration prevention. The connection point between R1 and R2 is connected to the base terminal of npn transistor Q4. The emitter terminal of Q4 is connected to the emitter terminal of the IGBT via Zener diode ZD1. Here, the base-emitter voltage Vbe of Q4 is
From the value obtained by dividing Vge by R1 and R2 (this value is referred to as Vge '), the voltage of Zener diode ZD1 (this is referred to as Vge)
ZD1) (Vge'-VZD1). The collector terminal of Q4 is connected to the gate of the IGBT via the resistor R3. Here, the collector terminal of Q4 is represented by a. At point a, the base terminals of pnp transistors (Q2 and Q3) connected in Darlington are connected. With such a connection, Q4 functions to amplify (Vge'-VZD1) and vary the resistance of the Darlington-connected Q2.

The second gate drive circuit and the first gate drive circuit are connected by wiring, and the parasitic inductance is represented by Ls in FIG. The first gate drive circuit 1 has push-pull connected transistors Tr1 and Tr2, and has a gate resistor Rg on the output side. When Tr1 turns on, the value of the power supply voltage Vcc1 is applied as a forward bias voltage between the gate and emitter of the IGBT, and conversely, when Tr2 turns on,
IGBT with power supply voltage Vcc2 value as gate reverse bias
Is applied. Current is supplied from the base current control means 3 to the base terminals of Tr1 and Tr2. Here, the base current control means 3 responds to the input signal Vs, the detected value of the collector-emitter voltage Vce of the IGBT (hereinafter abbreviated as the collector voltage) and the signal at the point a in the second gate drive circuit. And a function of varying the output current. Next, these detection systems will be described.

First, the detection of Vce will be described. Power supply voltage Vcc
1 is connected to the emitter terminal of a pnp transistor Tr3, and the base terminal of Tr3 is connected to the IGBT via a diode Dc.
To the collector terminal of A resistor Rd1 is connected in parallel between the emitter and the base of Tr3. This resistor is used to accelerate the turning off of Tr3. The collector terminal of Tr3 is a resistor R
Connected to the negative electrode of Vcc2 via d2. The connection point between the collector terminal of Tr3 and the resistor Rd2 is input to the base current control means 3 via the logic inverter INV. This Vce detection method is also implemented in many known examples, and the Vce of IGBT is
ce is a reference value (Vcc1 to Tr3 base voltage and Dc
Is higher than the value obtained by subtracting the on-state voltage of the signal).
Next, the base current control means 3 will be described. The voltage at the point a is compared with the reference voltage Vref by the comparator CMP, and the result is input to the base current control means 3.

The base current control means 3 changes the output current ib under the following three conditions.

1) The voltage at point a is lower than Vref. 2) Vce of the IGBT is higher than the reference value. 3) The input signal Vs is given.

Here, when all of the conditions 1) to 3) are satisfied, the base current control means 3 changes the current ib indicated by the arrow in FIG. 1 from a positive value ib1 in FIG. 1 to a negative value ib2. Let it. At this time, it is assumed that the change of ib changes continuously over a predetermined period.

As described above, Q4 of the second gate drive circuit
Amplifies (Vge'-VZD1), outputs this value as the voltage at point a, and varies the resistance of the Darlington-connected Q2 according to (Vge'-VZD1). Here, it has already been described that US Pat. No. 5,210,479 describes a conventional example in which Vge of the IGBT is detected and the gate output is changed according to both the value and the Vce detection result. Therefore, the difference between the conventional example and the present invention will be described.

FIG. 2 shows the results of an arm short-circuit test of an IGBT using the conventional example and the present invention. In the arm short circuit, another IGBT was connected in series to the IGBT of FIG. 1 and both were turned on. FIG.
The result of (a) is an operating waveform according to the method described in U.S. Pat. No. 5,210,479. IG that was on at the beginning
With BT as Q1, the short-circuit protection circuit of Q1 detects a short-circuit caused by erroneous firing of the arm, and performs soft cutoff. FIG. 2A shows that when an arm short circuit occurs, the gate voltage of the IGBT Q1 that was initially turned on rises. This phenomenon occurs because the displacement current flows into the gate capacitance through the collector-gate feedback capacitance Crss when the collector-emitter voltage increases to several tens of volts due to the arm short circuit, and the gate voltage increases. In the conventional example described in US Pat. No. 5,210,479, an increase in the collector voltage of the IGBT and an increase in the gate voltage due to the displacement current are detected to recognize that a short circuit has occurred. Normally, the gate should gradually decrease due to the function of the protection circuit from the point of occurrence of the short circuit (this is called gate soft cutoff). However, in FIG. 2A, the gate voltage rises only during the period of 20 μs. Is over. This indicates that the gate soft cutoff does not work effectively due to the parasitic inductance of the wiring from the IGBT module to the gate drive circuit, and conversely, the gate voltage increases due to the inflow of the displacement current.

Next, FIG. 2B shows an operation waveform of the present invention using the embodiment of FIG. According to the present invention, if the gate voltage is to be increased due to the inflow of the displacement current immediately after the occurrence of the short circuit, Q4 of the second gate drive circuit 2 becomes (Vge'-VZ).
D1) is amplified, this value is transmitted to the base current control means, and the resistance of the Darlington-connected Q2 is varied according to (Vge'-VZD1). In the case of FIG. 2B, the current of Q4 increases because Vge 'tries to increase,
As a result, the resistance of Q2 decreases. Therefore, Q2
Bypasses the incoming displacement current with low resistance,
It does not increase the gate voltage of TQ1. next,
The base current control means 3 detects the occurrence of a short circuit from Vce and the output at the point a, controls the base current, and operates so as to softly cut off the gate voltage at Tr1 and Tr2. FIG.
As is clear from the comparison between the waveform of FIG. 2B and the result of FIG. 2A, in FIG. 2B, the swelling of the gate voltage caused when the arm is short-circuited is eliminated, and as a result, the maximum value of the short-circuit current becomes approximately It has been reduced by 1000A. Further, in the conventional example of FIG. 2A, the rate of decrease of the gate voltage (dVge / dt) becomes steeper than the value at the time of the normal soft cutoff due to the effect of the rise of the gate voltage. di / dt)
Is big. In the present invention shown in FIG. 2B, since the swell of the gate voltage is eliminated, dVge / dt is small, and di / dt at the time of cutoff is also suppressed. As a result, the collector voltage Vce during the soft cutoff also decreases, and the voltage-current locus (trajectory) of the IGBT can be kept within a safe operation range where the device maker compensates.

Next, a second embodiment of the present invention is shown in FIG. FIG. 3 shows an IGBT using first and second gate drive circuits.
Is a circuit that suppresses a voltage time change (dV / dt) when turning on or off. In FIG. 3, the first gate drive circuit 1 is similar to the configuration shown in FIG. 1, and only different portions will be described. In the embodiment of FIG. 3, the difference between the voltage at point a in the second gate drive circuit and the reference voltage Vref is amplified using an amplifier AMP, and the output of the AMP is input to the base current control means 3. The difference in the operation of the entire circuit will be described later.

The second gate drive circuit differs from the embodiment of FIG. In region 2, resistors R1 and R2 are connected in series between the gate and emitter terminals of the IGBT in parallel, and a capacitor C1 for preventing vibration is connected to R1. I at R1 and R2
The point at which the gate voltage Vge of the GBT is divided is the same as that of FIG. 1, and the connection point between R1 and R2 is connected to the base terminal of the npn transistor Q4. The emitter terminal of Q4 is connected to the emitter terminal of IGBT via Zener diode ZD1. The collector terminal of Q4 is connected to the gate of the IGBT via a resistor R3, and the collector terminal a of Q4 is connected to the base terminals of pnp transistors (Q2 and Q3) connected in Darlington as in FIG.

The difference between FIG. 3 and FIG. 1 lies in how the emitter voltage of Q4 is applied. In FIG. 3, resistors R6 and R7 are connected in series between the gate and emitter terminals of the IGBT, and the connection point between R6 and R7 is connected to the base terminal of npn transistor Q5. The emitter terminal of Q5 is connected via a resistor R5 to the emitter terminal of the IGBT. The collector terminal of Q5 is connected to the gate terminal of the IGBT.

With this connection, the voltage across the resistor R5 becomes a voltage (denoted as Vref2) that changes according to the input voltage Vo of the second gate voltage shown in the figure. The voltage obtained by dividing the value of Vref2 by the resistor R4 and the internal resistance of the Zener diode ZD1 becomes the emitter voltage of Q4. However, ZD
Since the internal resistance of 1 is much larger than that of R4, the emitter voltage of Q4 is substantially Vref2. As shown in FIG. 2, when a short circuit occurs and the gate voltage rises, Vref2 tends to become larger than VZD1.
Since it is clamped at D1, the upper limit of the emitter voltage of Q4 is VZD1.

With the above configuration, the base-emitter voltage Vbe of Q4 is a value Vge 'obtained by dividing Vge by R1 and R2.
Is subtracted from Vref2 (Vge'-Vref2). Also, Q4 amplifies (Vge'-Vref2) and varies the resistance of Darlington-connected Q2. In the prior art, even if the first gate drive circuit attempts to control the gate voltage of the IGBT to a desired waveform, the wiring inductance L
The gate waveform collapses due to s and the displacement current of the feedback capacitance. In the embodiment of FIG. 3, Vref2 changes according to the input voltage Vo of the second gate voltage. That is, it is an object of the present invention to suppress the gate voltage detection value Vge 'from going to increase by using Vref2 corresponding to the voltage Vo.

FIG. 4 shows the effect of the present invention. FIG. 4A shows a case where the gate voltage of the IGBT is discharged by the gate resistance Rg inside the first gate circuit without using the second gate circuit. At the time of such turn-off, when the gate voltage changes from a forward bias state of a rated 15V to a reverse bias of -10V, a stepwise flat period is once formed at about 10V. If this is termed the terrace period, the collector-emitter voltage of the IGBT rises, a displacement current flows through the collector-gate feedback capacitance Crss into the gate circuit, and the discharge of the gate-emitter capacitance pauses due to this effect. A terrace period occurs. Just before the end of this terrace period, the collector voltage of the IGBT increases sharply,
Subsequently, the current of the IGBT is cut off. However, I
The change when the gate voltage of the GBT decreased from the value during the terrace period was uncontrollable. That is, the gate voltage is gradually reduced to change the collector voltage dV / dt at turn-off.
Was not achieved due to the influence of the terrace period.

Next, FIG. 4B shows a turn-off waveform when the embodiment of FIG. 3 is applied. In the present invention, the feedback capacitance Crs
The displacement current passing through s is the Darlington transistor Q2, Q
3, the terrace period does not occur. Further, since the reference voltage Vref2 changes in accordance with the input voltage Vo of the second gate drive circuit, it can be confirmed that the gate voltage Vge of the IGBT suppressed by this value has a waveform similar to Vo.

The relationship between the first gate drive circuit and the second gate drive circuit shown in FIG. 3 is as follows. That is, 1) the first gate drive circuit causes a predetermined gate current to flow at the start of turn-off.

2) When the gate voltage Vge of the IGBT enters the terrace period, (Vge'-Vref2) increases and Q
The action of 4 reduces the resistance of Q2 and bypasses the displacement current.

3) The collector voltage (point a) of Q4 changes, and the base current control means 3 in the first gate drive circuit changes the current ib from the output of the amplifier AMP.

4) The gate voltage of the IGBT gradually decreases according to the current ib. Here, the collector voltage increases slowly and the current is cut off.

5) When the gate voltage of the IGBT changes from the forward bias to the reverse bias, the operation of the second gate drive circuit ends, and the gate voltage decreases only in the first gate drive circuit. If this period is detected from the output of the amplifier AMP, the base current control means 3 may rapidly decrease the gate voltage of the IGBT.

6) If an arm short circuit occurs during the ON period of the IGBT, Vref2 is clamped at VZD1, and the subsequent operation is controlled so as to be the same as that of the embodiment of FIG.
FIG. 5 shows an embodiment in which the embodiment of FIG. 3 is applied to an IGBT connected in parallel. IGBT Q1 connected in parallel in FIG.
And Q6 have second gate drive circuits 2-1 and 2-2 between the gate and emitter terminals, respectively. The first gate drive circuit detects that one of the collector voltages of Q1 and Q6 is higher than a predetermined value. Second gate drive circuit 2-
In the case of 1 and 2-2, when one of Q1 and Q6 is in the arm short state first, this is detected by the internal transistor Q4, and the rise of the gate voltage is suppressed. The other IG
Although the BT is short-circuited with a delay, the gate voltage does not rise in either case, so that the short-circuit current is reduced as shown in FIG. Subsequent operations are the same as in the embodiment of FIG.

Conventionally, the collector voltage and the gate voltage of one of the IGBTs have been detected. Therefore, if the IGBT whose voltage has not been detected is short-circuited first, current concentrates on the IGBT and the element may be destroyed. There was sex. In addition, as a result of the concentration of the current, the change in the collector voltage and the gate voltage of the other IGBT is delayed, and the detection of the occurrence of the short circuit in the first gate drive circuit is delayed. According to the present invention, since the second gate drive circuits are provided in each case, quick protection processing is possible. The same applies to the case where dV / dt during switching is suppressed in the embodiment of FIG. While connected in parallel, the gate voltages of both IGBTs are not equal due to wiring inductance. Even in such a situation, the second gate drive circuits 2-1 and 2-2 can detect the respective gate voltages and perform appropriate gate voltage suppression based on the difference from the voltage Vo.

[0033]

According to the present invention, when an abnormality such as a short circuit occurs,
The gate voltage of the IGBT can be immediately suppressed, the short-circuit current can be reduced, and the element can be prevented from being destroyed. In addition, at the same time as preventing the displacement current from affecting the gate circuit by the feedback capacitance, appropriate suppression of the gate voltage according to the detection signal of the amplification transistor Q4 is achieved, and dV /
By suppressing dt, it is possible to prevent electromagnetic induction failure and noise malfunction. Further, a plurality of IGBTs connected in parallel
The IGBT that is short-circuited first and the IGBT that is short-circuited with a delay can change the degree of suppression of the gate voltage, and appropriately protect each of them, or suppress dV / dt.

[Brief description of the drawings]

FIG. 1 shows a configuration of overcurrent protection by a gate drive circuit of the present invention.

FIG. 2 is a comparison between the conventional example and the embodiment of FIG. 1 in short-circuit protection.

FIG. 3 shows a configuration of dV / dt suppression by the gate drive circuit of the present invention.

FIG. 4 shows a comparison between the prior art and the embodiment of FIG. 2 at the time of turn-off.

FIG. 5 is an embodiment in which the gate drive circuit according to the present invention is applied to a parallel IGBT.

[Explanation of symbols]

Q1, Q6 ... IGBT, Q1 to Q5, Tr1 to Tr3 ...
Transistors, R1 to R7, Rd1, Rd2, Rg: resistor, C1, C2: capacitor, INV: logic inverter, CMP: comparator, AMP: amplifier, Dc ...
Diode, ZD1 ... Zener diode, Vcc1, Vc
c2: power supply, 1: first gate drive circuit, 2: second gate drive circuit, 3: base current control means, Vs: input signal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Asako Koyanagi 7-2-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Power & Electricity Development Division, Hitachi, Ltd. (72) Inventor Makoto Tachikawa Omika-cho, Hitachi City, Ibaraki Prefecture 5-2-1, Hitachi, Ltd. Omika Plant

Claims (4)

[Claims] 1. A second gate drive circuit provided between a gate current input / output terminal of a power semiconductor element and a first gate drive circuit, and powered by a gate voltage of the power semiconductor element, Amplifying means for amplifying a difference voltage between a gate voltage detection value of a semiconductor element and a reference voltage; and a variable resistor for changing a resistance value of a resistance means provided in parallel with the gate current input / output terminal according to an output of the amplifying means. A gate drive circuit for a power semiconductor device, comprising a device. 2. The second gate drive circuit according to claim 1, wherein the reference voltage is a voltage that changes according to an output voltage of the first gate circuit. Gate drive circuit. 3. A drive circuit for a power semiconductor device using the first and second gate drive circuits according to claim 1 or 2, wherein an input / output terminal of the power semiconductor device is provided in the first gate drive circuit. A second voltage detecting means for detecting an inter-voltage,
When the output of the second voltage detecting means and the output of the amplifying means provided in the second gate driving circuit are in a predetermined state, the positive voltage supplied from the first gate driving circuit to the power semiconductor element is changed. Alternatively, a driving circuit for a power semiconductor element, wherein a gate current in a negative direction is suppressed. 4. A power semiconductor device circuit for driving a plurality of power semiconductor devices connected in parallel using the first and second gate drive circuits according to claim 1, wherein: Along with second voltage detection means for detecting the voltage between the input and output terminals of the plurality of power semiconductor elements connected in parallel, respectively, the gate current input and output terminals of the power semiconductor elements connected in parallel,
Comprising the second gate drive circuit, the output of any one of the amplifying means provided in the plurality of second gate drive circuit,
When the output of the second voltage detection means is in a predetermined state,
A drive circuit for a power semiconductor element, wherein a gate current in a positive or negative direction supplied from the first gate drive circuit to the power semiconductor element connected in parallel is suppressed.