JP2000091563A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a MOS transistor subjected to hyperfine processing. SOLUTION: A Ti film 70 is formed on the whole surface in a state that a TiSi-2/Poly-Si polycide gate 40 is formed on a substrate 10 via a gate insulating film, a hard mask 51 is formed on the gate 40 and spacers 60 are respectively formed on the sidewalls of the gate 40. Annealing is performed, whereby a titanium silicide TiS film 12 is formed on the interface between source and drain regions 12 and a a contact film is formed between the regions 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art With the development of MOS LSI microfabrication technology, large capacity and small chip size have been developed.

A conventional method for manufacturing a MOS transistor will be described with reference to FIGS. FIG. 4 to FIG.
FIG. 9 is a process sectional view of a MOS transistor element constituting M.

First, in a step shown in FIG. 4A, a field oxide film (200) is formed on a p-type region of a silicon substrate (100) by using a LOCOS method, and a gate oxide film (200) is formed by thermal oxidation. 300) is formed.

Subsequently, in a step shown in FIG.
On the gate oxide film (300), polysilicon Poly-Si is formed to a thickness of about 1000 ° by low pressure CVD, phosphorus is doped by thermal diffusion of the POC13, and then etched to form the gate electrode ( 400) is formed. Then, the gate electrode is changed to (40
Using the mask 0) as a mask, ion implantation is performed to form an n − -type low concentration region (101). The ion implantation is performed, for example, by implanting n-type phosphorus with a low dose of 10.sup.14. The region immediately below the gate electrode (400) becomes a p-type channel region (103).

In the step shown in FIG. 4C, a spacer (500) is formed on the side wall of the gate Poly-Si (400) by forming a silicon oxide film on the entire surface and performing etch back on the entire surface. At this time, the gate Poly-S
The gate oxide film (300) other than the i (400) and the sidewall spacer (500) is also removed, and the silicon substrate (100) is removed.
Surface is exposed. Then, the side wall spacer (500)
Is added to the mask, and the ion implantation of phosphorus is performed at a high dose of about 10 15, so that the side wall spacer (50
A high concentration region (102) is formed in a region other than (0). The region immediately below the side wall spacer (500) is a low concentration region (10
1) remains. As a result, the p-type channel region (1
Source and drain regions (102) composed of high concentration regions are formed on both sides of the region (03) with the low concentration region (101) interposed therebetween. Such a structure is LDD (lightly doped drain)
Called.

In the step shown in FIG. 5D, a titanium Ti film (600) is
It is formed to a thickness of about 500 °. In this state, the substrate is subjected to lamp annealing so that the interface between the Ti film (600) and the source and drain regions (102) and the Ti film (60) are formed.
Then, titanium silicide TiSi2 is formed at the interface between the gate poly-Si (400) and the gate poly-Si (400). In general, a stacked structure of a silicide layer and Poly-Si has become mainstream in MOS LSIs because both compatibility with the gate oxide film (30) and reduction in wiring resistance are achieved. In particular, TiS which is a compound of Ti and Si as silicide
i2 is a low resistance wiring.

In the step shown in FIG. 5E, the Ti film (600) is removed by etching, so that the source and drain regions (102) and the gate Poly- are removed.
A TiSi2 film (601, 602) is formed on Si (400). The gate Poly-Si (400) and the TiSi2 film thereon (601) form a polycide gate,
TiSi2 (6) on the source and drain regions (102)
02) becomes a contact film.

In the step shown in FIG. 6 (f), an interlayer insulating film (700) made of a silicon oxide film and / or a silicon nitride film is formed on the entire surface, and this is etched to form a contact hole (CT). I do. Then, a source electrode (800) and a drain electrode (900) connected to the source and drain regions (102) via the contact film (602) are formed by depositing Al by sputtering and etching this. I do.

[0010]

The channel width is 0.35.
In an ultrafine structure of about μm or less, the gate Poly-Si
The thickness of (400) is thin, about 1000 ° or less. With such a fine structure, the generation region of TiSi2 relatively increases in the lamp annealing step shown in FIG. As a result, a residual film of TiSi2 occurs, and the gate Poly-Si (40) shown in FIG.
0) and the TiSi2 (602) on the source / drain region (102) are connected, resulting in a short circuit between the gate and the source and between the gate and the drain.

Further, in the ultrafine structure, when the gate width is reduced, at the interface with the Ti film (600) on the gate Poly-Si (400), titanium silicide TiS is formed.
It becomes difficult to generate i2 (601). As a result, the gate wiring resistance increases, causing a signal delay, which hinders high-speed operation.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has been made in order to solve the above-mentioned problem. In the method of manufacturing a device, a step of forming a mask layer on a polycide film to be the gate electrode,
Forming the gate electrode by etching the polycide film using the mask layer as a mask, forming a spacer on a sidewall of the gate electrode, and forming an impurity-implanted region in the semiconductor substrate; Covering the mask layer and the spacer to form a conductive film layer; and annealing the substrate to form a silicide layer at an interface between the impurity-implanted region and the conductive film layer. is there.

As a result, even if the gate film thickness is reduced,
Short circuit between the gate and the source and / or the gate and the drain due to the remaining film of the silicide layer is prevented.
Further, even if the gate width is reduced, the silicidation is not sufficiently performed to prevent the gate wiring resistance from increasing.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS MO according to an embodiment of the present invention
A method for manufacturing the S transistor element will be described with reference to the process sectional views of FIGS.

First, in the step shown in FIG. 1A, a field oxide film (20) is formed on a p-type region of a silicon substrate (10) by a LOCOS method, and a gate oxide film (30) is thermally oxidized. To form

Subsequently, in the step shown in FIG.
Polysilicon Poly-Si (41) is formed on the gate oxide film (30) to a thickness of about 1000 ° by low-pressure CVD, and phosphorus is doped by thermal diffusion of the POCL3. Furthermore, low pressure C is applied on the Poly-Si (41).
Titanium silicide TiSi2 (42) is 10 by VD.
The film is formed to a thickness of about 00 °.

Next, in the step shown in FIG.
A silicon oxide film (50) is formed on the iSi2 (42) by low-pressure decomposition of TEOS (tetraethoxysilane).
It is formed to a thickness of 00 °. This silicon oxide film (50)
Will later become a hard mask.

In the step shown in FIG. 2D, a hard mask (51) is formed by etching the silicon oxide film (50) into the shape of a gate electrode, and TiSi2 ( 42) / Poly
-Si (41) is etched to obtain TiSi
A gate electrode (40) made of 2 / Poly-Si, that is, a polycide layer is formed.

Since the gate polycide (40) is formed by forming and etching polycide, a low-resistance polycide gate wiring is formed irrespective of the gate width.

Then, ion implantation is performed using the hard mask (51) and the gate electrode (40) as masks. The ion implantation is performed, for example, by implanting n-type phosphorus with a low dose of 10.sup.14. Thus, a low concentration region (11) is formed in a region of the silicon substrate (10) other than immediately below the gate electrode (40). The region immediately below the gate electrode (40) becomes a p-type channel region (13).

In the step shown in FIG. 2E, a silicon oxide film is formed on the entire surface and the entire surface is etched back to form spacers (60) on the side walls of the gate electrode (40) and the hard mask (51). I do. At this time, the gate oxide film (30) other than the gate electrode (40) and the sidewall spacer (60) is also removed, exposing the surface of the silicon substrate (10). Furthermore, the high-concentration region (12) is formed in a region other than the side wall spacer (60) by adding the side wall spacer (60) to the mask and performing phosphorus ion implantation at a high dose of about 10 15. . Side wall spacer (6
In the region directly below 0), the low concentration region (11) remains. As a result, the source and drain regions (12) composed of the high-concentration regions are formed on both sides of the p-type channel region (13) with the low-concentration region (11) interposed therebetween, and an LDD structure is obtained.

In the step shown in FIG. 2F, a Ti film (70) is formed on the entire surface by sputtering at 100 to 500 °.
After forming a film having a thickness of 10 nm, lamp annealing is performed, so that the source and drain regions (12) and the Ti film (70) are formed.
TiSi2 is generated at the interface of.

In the step shown in FIG. 3 (g), only the TiSi2 film (71) formed on the source and drain regions (12) is left by etching away the Ti. This TiSi film (71) becomes a contact film.

Here, in the present invention, the contact film (7
The formation of 1) is performed separately from the gate polycide (40). That is, the gate polycide (40) and the titanium silicide TiSi2 (71) form a hard mask (5).
1) and are insulated by the spacer (60). Therefore, the gate polycide and the contact film (71) are not short-circuited due to the remaining film of titanium silicide TiSi2.

In the step shown in FIG. 3H, an interlayer insulating film (70) made of a silicon oxide film and / or a silicon nitride film is formed on the entire surface and a contact hole (CT) is formed by etching this film. I do. Then, a source electrode (80) and a drain electrode (90) connected to the source and drain regions (12) via the contact film (71) are formed by depositing Al by sputtering and etching the film. I do.

[0026]

As is apparent from the above description, according to the method for manufacturing a semiconductor device having an ultrafine structure of the present invention, the silicide layer forming the contact layer in the source and drain regions is replaced with the silicide layer forming the polycide gate. Since the film is formed separately from the layer, occurrence of a short circuit between the gate and the source or / and between the gate and the drain can be prevented. Further, even when the gate width is reduced, a sufficient silicide layer is formed on the silicon of the gate, so that the wiring resistance of the polycide gate can be prevented from lowering.

[Brief description of the drawings]

FIG. 1 is a process sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 5 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 6 is a process sectional view illustrating a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 Reference Signs List 10 silicon substrate 30 gate oxide film 40 polycide gate 51 hard mask 60 spacer 70 Ti film

Continued on the front page F term (reference) 5F040 DA01 DA14 DC01 EC01 EC04 EC07 EC13 EF02 EH02 EJ03 EK01 FA03 FA05 FA17 FA19 FB02 FB04 FC00 FC19

Claims (1)

[Claims] In a method of manufacturing a semiconductor device having a semiconductor layer on a substrate and a gate electrode formed to face the semiconductor layer with a gate insulating film interposed therebetween, a step of forming a polycide film to be the gate electrode Forming a mask layer on the polycide film; forming the gate electrode by etching the polycide film using the mask layer as a mask; and forming a spacer on a side wall of the gate electrode. Forming an impurity-implanted region in the semiconductor substrate; forming a conductive film layer covering the mask layer and the spacer; and annealing the substrate to form the impurity-implanted region and the conductive film layer. Forming a silicide layer at the interface.