JP2000091354A - Semiconductor device and electronic device using semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the high-density mounting of a semiconductor device and to simplify the mounting process. SOLUTION: With respect to a semiconductor device which has a circuit pattern on a semiconductor substrate 2, a plurality of circuit patterns, which are segmented respectively by scribing area 4a, are made to form an integral body. Thus, a plurality of the semiconductor devices are formed on the same semiconductor substrate. Furthermore, a plurality of the semiconductor devices which have the circuit patterns, are mounted on the semiconductor substrate 2. In this electronic device, a plurality of the patterns which are segmented respectively by the scribing areas 4a are made to form the integral body. Thus, a plurality of the semiconductor devices formed on the same semiconductor substrate are mounted. The space between the semiconductor chips required, when the mounting is performed by the individual semiconductor chips is not required. Therefore, density mounting becomes high. In comparison with the case, where the individual semiconductor chips are mounted, the process is simplified since a plurality of the semiconductor devices are mounted as the integral body.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an electronic device,
In particular, the present invention relates to a technology that is effective when applied to an electronic device in which a plurality of semiconductor devices are mounted at high density.

[0002]

2. Description of the Related Art Notebook type personal computers, PDs
As an information storage medium of a portable information device called A (Personal Digital Assistant), a small information device such as an electronic still camera, a flash ATAPC card in which a plurality of nonvolatile storage devices are housed in a card-shaped housing, a compact flash ( Registered trademark) and the like. Such a storage medium is required to have both a large storage capacity and a small storage capacity and to be inexpensive. Also,
In a silicon file that is a fixed storage device of a computer by mounting a plurality of nonvolatile storage devices, high-density mounting is required in order to increase the capacity. In the conventional method of mounting a semiconductor device on a substrate, there are problems such as difficulty in design due to parasitic inductance and reflection of a package, and a problem such as a speed limitation due to inter-chip delay. It is necessary to shorten the length and reduce the load capacity, and an MCM (Multi Chip Module) in which a plurality of bare chips are mounted on a base substrate on which thin-film multilayer wiring is formed has been considered. However, the cost is increased because the base substrate is required and the process is complicated.

[0003]

In order to achieve both miniaturization and large capacity, it is necessary to reduce the mounting area of each semiconductor device or to increase the mounting density of the semiconductor devices.

[0004] As a method of reducing the mounting area of each semiconductor device, a CSP (Chip Size Package) type semiconductor device has been considered, but this method still has a problem in cost reduction. In addition, a COB (Chip On Board) in which a bare chip is mounted and sealed after bonding has been considered, but this method has a problem that the yield is reduced.

As a method for increasing the mounting density, three-dimensional mounting in which semiconductor devices are stacked has been considered. However, the electronic device becomes thicker, the process becomes complicated, and the cost increases.

An object of the present invention is to provide a technique for realizing high-density mounting of a semiconductor device.

Another object of the present invention is to provide a technique capable of simplifying a semiconductor device mounting process.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

Means for Solving the Problems Among the inventions disclosed in the present application, the outline of typical inventions will be briefly described.
It is as follows.

With respect to a semiconductor device in which a circuit is formed on a semiconductor substrate by patterning, a plurality of circuit devices, each of which is divided by a scribing area, are integrated to form a plurality of semiconductor devices on the same semiconductor substrate.

Also, for an electronic device in which a plurality of semiconductor devices each having a circuit pattern formed on a semiconductor substrate are mounted, a plurality of semiconductor devices formed on the same semiconductor substrate are integrated by integrating a plurality of patterns each divided by a scribing area. Implement.

According to the above-described means, the space required between the semiconductor chips is not required when the semiconductor chips are mounted on the separated semiconductor chips, so that the density mounting is increased.
As compared with a case where individual semiconductor chips are mounted, a plurality of semiconductor devices are integrally mounted, so that the process is simplified.

Hereinafter, embodiments of the present invention will be described.

In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a plan view showing a flash PC card which is an electronic apparatus according to an embodiment of the present invention, and FIG. FIG.

In this electronic device, a wiring board 2 is mounted on a card-shaped housing 1, and external terminals 3 mounted on the wiring board 2 are exposed from the housing 1. Devices.

On the wiring board 2, a storage device 4 and a control device 5 in which nonvolatile storage elements for recording information are integrated are mounted, and the storage device 4 and the control device 5 are connected by wiring 6 provided on the wiring substrate. Further, the wiring connected to the control device 5 is connected to the external terminal 3 at the end of the wiring board 2, and the external terminal 3 is fixed to the wiring board 2. FIG. 1 shows a state in which the lid of the housing 1 is removed.

In the manufacture of a semiconductor device, a plurality of semiconductor device patterns formed by predetermined circuits are formed on the same wafer on a wafer of single crystal silicon or the like, and each pattern is divided by a scribing area for cutting and separating. Normally, the semiconductor device is individually cut for each pattern of the semiconductor device after the completion of the wafer process.

On the other hand, the storage device 4 of the present embodiment
In each of the plurality of memory patterns 4b divided by the scribing area 4a, they are collectively cut by full-cut dicing or semi-full-cut dicing. In the example shown in FIG. 1, six patterns are integrated, and Eight patterns are integrated in the mounted storage device 4. For this reason, a space (usually about 2.5 mm to 3.0 mm depending on the semiconductor device) provided between the chips is not required, so that the mounting density is improved. In addition, although a plurality of chips are conventionally mounted individually, the mounting process is simplified since they are mounted integrally.

Further, a groove 4c formed by half-cut dicing is provided in the scribing area 4a between the patterns. By providing this groove 4c, the groove 4c can be easily deformed when an external force is applied. Even when an external force is excessively applied to the groove 4c where the element is not formed, the element is not easily broken, so that the formed element can be prevented from being broken.

In the present embodiment, the storage device 4 and the control device 5 are mounted face-down on the wiring board 2 and are flip-chip connected. The protruding electrodes 7 such as solder provided on the element forming surfaces of the storage device 4 and the control device 5 are aligned with the bonding leads 8 provided on the wiring board 2 and are melted and joined by being heated. .

In connection between the storage device 4 and the control device 5, each of the plurality of memory patterns 4
For b, there are a wiring 6a individually connected such as data input / output and a wiring 6b commonly connected to each memory pattern 4b such as a power supply.

In the individually connected wiring 6a, the individual pattern 4b and the wiring from the control device 5 are respectively connected, but in the wiring 6b common to each pattern 4b, each memory pattern 4b is connected in parallel. And are connected to the same wiring. With respect to such a common wiring 6b, a wiring pattern may be formed in the scribing area 4a in advance, the wiring pattern may be connected to each memory pattern 4b, and an end of the wiring pattern may be connected to the wiring 6b. it can. With this configuration, it is possible to reduce the wiring length and the load capacity.

When a plurality of patterns 4b are collectively cut from a wafer, defective patterns may be included therein. As a countermeasure in such a case, a defective product should be sorted out in a wafer state, or a burn-in test should be performed in a wafer state, reliability should be confirmed, and a separation should be performed excluding a defective product found. Is valid.

In the case of electronic devices such as memories, several types of products with different capacities are prepared. Therefore, if the above-mentioned sorting is difficult due to cost, time, etc., electronic devices are manufactured without such sorting, and devices that contain defective products during product testing are replaced with lower-capacity devices. The secondary silicon method is also effective.

(Embodiment 2) FIG. 3 is a plan view showing a flash PC card as an electronic apparatus according to another embodiment of the present invention, and FIG. 4 is a longitudinal section taken along the line aa in FIG. FIG.

In this electronic device, a wiring board 2 is attached to a card-shaped casing 1, and external terminals 3 attached to the wiring board 2 are exposed from the casing 1. Devices.

On the wiring board 2, a storage device 4 and a control device 5 in which nonvolatile storage elements for recording information are integrated are mounted, and the storage device 4 and the control device 5 are connected by wiring 6 provided on the wiring board. Further, the wiring connected to the control device 5 is connected to the external terminal 3 at the end of the wiring board 2, and the external terminal 3 is fixed to the wiring board 2. FIG. 3 shows a state where the lid of the housing 1 is removed.

In the manufacture of a semiconductor device, a plurality of semiconductor device patterns formed by predetermined circuits are formed on the same wafer on a wafer of single crystal silicon or the like, and each pattern is divided by a scribing area for cutting and separating. Normally, the semiconductor device is individually cut for each pattern of the semiconductor device after the completion of the wafer process.

On the other hand, the storage device 4 of the present embodiment
In each of the plurality of memory patterns 4b divided by the scribing area 4a, they are collectively cut by full-cut dicing or semi-full-cut dicing. In the example shown in FIG. 1, six patterns are integrated, and Eight patterns are integrated in the mounted storage device 4. For this reason, a space (usually about 2.5 mm to 3.0 mm depending on the semiconductor device) provided between the chips is not required, so that the mounting density is improved. In addition, although a plurality of chips are conventionally mounted individually, the mounting process is simplified because they are mounted integrally.

A groove 4c formed by half-cut dicing is provided in the scribing area 4a between the patterns. By providing the groove 4c, the groove 4c can be easily deformed when an external force is applied. Even when an excessive external force is applied to the groove 4c where the element is not formed, the element is not easily broken, so that the formed element can be prevented from being broken.

In the present embodiment, the storage device 4 and the control device 5 are mounted face-up on the wiring board 2, and the bonding pads 9 provided on the element forming surfaces of the storage device 4 and the control device 5, and the wiring 6 Is connected to the bonding lead 8 by a bonding wire 10.

In the connection between the storage device 4 and the control device 5, each of the plurality of memory patterns 4
For b, there are a wiring 6a individually connected such as data input / output and a wiring 6b commonly connected to each memory pattern 4b such as a power supply.

In the individually connected wiring 6a, the individual pattern 4b and the wiring from the control device 5 are respectively connected, but in the wiring 6b common to each pattern 4b, each memory pattern 4b is connected in parallel. And are connected to the same wiring. For such a common wiring 6b, the corresponding bonding pads 9 may be connected by bonding wires 10, and the memory patterns 4b may be connected in parallel.

Further, it is also possible to form a wiring pattern in the scribing area 4a in advance, connect the wiring pattern to each memory pattern 4b, and connect the wiring pattern to the wiring 6b at the end of the wiring pattern. With this configuration, it is possible to reduce the wiring length and the load capacity. When a wiring pattern is formed in the scribing area 4a, the groove 4c is provided on the surface opposite to that shown in FIG. 4, or the groove 4c is not provided.

When a plurality of patterns 4b are collectively cut from a wafer, defective patterns may be included therein. As a countermeasure in such a case, a defective product should be sorted out in a wafer state, or a burn-in test should be performed in a wafer state, reliability should be confirmed, and a separation should be performed excluding a defective product found. Is valid.

In the case of electronic devices such as memories, several types of products with different capacities are prepared. Therefore, if the above-mentioned sorting is difficult due to cost, time, etc., electronic devices are manufactured without such sorting, and devices that contain defective products during product testing are replaced with lower-capacity devices. The secondary silicon method is also effective.

In the above embodiment, the case where the present invention is applied to a flash PC card has been described.
The present invention can be applied not only to a flash memory but also to a device mounted with a DRAM or an SRAM, or not only to a card but also to a memory module, a silicon file, an MCM, or the like. other,
The present invention can be similarly applied to other electronic devices such as a multiprocessor arithmetic device.

Further, as long as the circuit patterns are formed on the same wafer, the present invention can be implemented even if a plurality of circuit patterns include different types. For example, as shown in FIG. 5, a memory pattern 11b and a controller pattern 11d are divided by a scribing area 11a and are formed on the same wafer so as to be mixed, and a plurality of memory patterns 11b and a controller pattern 11d are formed as shown by broken lines. And the control device 5 can be integrated with the storage device 4 described above.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0041]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that a plurality of semiconductor devices can be formed on the same semiconductor substrate by integrating a plurality of circuit patterns each divided by a scribing area.

(2) According to the present invention, due to the above effect (1), the space required between the semiconductor chips is unnecessary when the semiconductor chips are mounted on the separated individual semiconductor chips, so that the density mounting is increased. effective.

(3) According to the present invention, the above-mentioned effect (1) makes it possible to reduce
Since a plurality of semiconductor devices are integrally mounted, the process is simplified.

[Brief description of the drawings]

FIG. 1 is a plan view showing an electronic device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view taken along the line aa in FIG.

FIG. 3 is a plan view showing an electronic device according to another embodiment of the present invention.

FIG. 4 is a longitudinal sectional view taken along line aa in FIG.

FIG. 5 is a partial plan view showing a wafer on which a plurality of circuit patterns including different types are formed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Case, 2 ... Wiring board, 3 ... External terminal, 4 ... Storage device, 4a, 11a ... Scribe area, 4b, 11b ...
Memory pattern, 4c groove, 5 control device, 6 wiring, 7 projecting electrode, 8 bonding lead, 9 bonding pad, 10 bonding wire, 11d controller pattern.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shinichi Fukasawa 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Hirotaka Nishizawa, Josuihoncho, Kodaira-shi, Tokyo 5--20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Business Headquarters (72) Inventor Hidenori Kitajima 5--20-1, Kamisui Honcho, Kodaira-shi, Tokyo Hitachi Semiconductor Co., Ltd. Semiconductor Business Headquarters (72) Inventor Aoki Hideyuki F-20 terms, 5-20-1 Josuihonmachi, Kodaira-shi, Tokyo F-term in the Semiconductor Division, Hitachi, Ltd. 5F047 AA17 AA19 BA06 BB16 CB03

Claims (10)

[Claims] 1. A semiconductor device having a circuit pattern formed on a semiconductor substrate, wherein a plurality of circuit patterns each divided by a scribing area are integrated to form a plurality of semiconductor devices on the same semiconductor substrate. apparatus. 2. The semiconductor device according to claim 1, wherein each of the plurality of circuit patterns is the same. 3. The semiconductor device according to claim 1, wherein the plurality of circuit patterns include different types. 4. The semiconductor device according to claim 1, wherein the plurality of circuit patterns include a circuit pattern of a semiconductor memory device. 5. The semiconductor device according to claim 1, wherein a groove is formed in a scribing area between the semiconductor devices. 6. An electronic device in which a plurality of semiconductor devices each having a pattern formed on a semiconductor substrate are mounted, wherein a plurality of patterns each divided by a scribing area are integrated to form a plurality of semiconductor devices formed on the same semiconductor substrate. An electronic device characterized by being mounted. 7. The electronic device according to claim 1, wherein each of the plurality of circuit patterns is the same. 8. The electronic device according to claim 1, wherein the plurality of circuit patterns include different types. 9. The electronic device according to claim 6, wherein the plurality of circuit patterns include a circuit pattern of a semiconductor memory device. 10. A groove is formed in a scribing area between the semiconductor devices.
The electronic device according to claim 9.