JP2000089963A - Data processor and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor and its processing method capable of efficiently accelerating initial rise and improving the performance of a system by downloading only necessary configuration data to a configuration memory built in a field programmable gate array in accordance with required data processing to be executed. SOLUTION: At the time of initialization, configuration data prepared for all areas of the configuration memory (RAM) 153 built in the field programmable gate array(FPGA) 150 and previously stored in a file storage device 140 are downloaded to the RAM 153 through a system memory 120 and then only configuration data necessary for data processing are downloaded to a part of the RAM 143.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of storing configuration data of a field programmable gate array for determining the function of predetermined hardware in a configuration memory in a field programmable gate array in the hardware. The present invention relates to a data processing device having a download function and a processing method thereof.

[0002]

2. Description of the Related Art In recent years, downsizing and the like of data processing apparatuses have been called out, and it has been desired to increase the processing speed. Under such demands, technology for dynamically switching hardware functions on a single piece of hardware occupies an important position in hardware technology, and is one of the technologies for dynamically switching hardware functions. A configurable field programmable gate array (FPGA) has become an effective means.

In addition, handling of configuration data at the time of initializing (re-configuring) a part or the whole of the function of a field programmable gate array (FPGA) is also an important technology in the performance of a data processing system. is there.

[0004] Here, an R memory provided with a conventional RAM memory capable of reading and writing configuration data is used.
A general-purpose data processing device using an AM-type FPGA will be described.

FIG. 5 is a diagram showing a data processing device using a conventional RAM-type FPGA. As shown in the figure, a plurality of configuration data are prepared in accordance with the functional specifications of the user, and the hardware functions are dynamically switched and used.

[0006]

However, the reconfiguration techniques described in the above prior art include:
There were the following problems.

First, the conventional RAM type FPG shown in FIG.
In the case of a data processing device using A, means for initializing (re-configuring) the entire function of the FPGA, and
Challenges remain in the management mechanism. At the time of power-on and during a period in which the function of the hardware in the FPGA is not determined during the transfer of the configuration data while re-initializing another function to the already initialized FPGA, Internal and I / O become unstable, power consumption increases, malfunctions occur.-Re-initialize another function for an already initialized FPGA. Re-load configuration data to all areas of RAM in FPGA. A problem such as reduction in speed due to transfer occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. When a desired data processing is executed, only necessary configuration data is stored in a field programmable gate according to the data processing. By downloading to the configuration memory in the array, the initial startup speed is increased efficiently and
An object of the present invention is to provide a data processing device and a processing method thereof with improved system performance.

[0009]

In order to achieve the above object, the present invention provides a configuration of a field programmable gate array which determines the function of predetermined hardware. In a data processing device having a function of downloading to a configuration memory in a gate array, when a desired data processing is executed, a necessary configuration is performed according to the data processing.
A download unit for downloading only data to a configuration memory in the field programmable gate array is provided.

In order to achieve the above object, the present invention provides a method for determining a function of predetermined hardware.
When performing desired data processing in a data processing device processing method having a function of downloading configuration data of a programmable gate array to a configuration memory in a field programmable gate array in the hardware, , Necessary configuration according to the data processing
A download step of downloading only data to a configuration memory in the field programmable gate array.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing the configuration and data flow of a data processing apparatus according to a first embodiment. In the figure, 110 is a central processing unit (CPU), 120 is a system memory, 130 is a device interface (I / F) unit, 140 is a file storage device (HD), 150 is a field programmable gate array (FPGA), 160 is an extension I / F, 1
70 is a host computer.

FIG. 2 is a flowchart showing download control to the FPGA shown in FIG. FIG. 3 is a diagram showing the correspondence between configuration data and RAM. FIG. 4 shows the configuration data FPGA.
9 is a flowchart showing a download process to the POP.

As shown in FIG. 1, in the present embodiment, a file storage device (HD) 140 is used as a storage device for storing configuration data, and an FPGA 150 is transmitted from the file storage device 140 via a system memory 120. Means for downloading to the RAM 153 in the internal memory, and data for fixing the inside of the FPGA 150, data frequently used, program data for diagnosis, etc. in the hardware during a period in which the function of the FPGA 150 in the initial state is not determined. The data is stored in the file storage device 140 in advance, and prior to downloading the necessary functions, the file storage unit 140
→ A means for transferring configuration data to the system memory 120 and a central processing unit (CPU) 110 for controlling download to a configuration memory (RAM) 153 in the FPGA 150 include an FPG.
The state of download to the A memory (RAM) 153 {download data type (data number), FPGA memory (RAM) 153} is managed, and configuration data is transmitted from the file storage device 140 in response to a function change instruction. Select FPGA memory (RAM) 15
3 is provided. still,
The same reference numerals indicate the same objects throughout the drawings.

Hereinafter, the configuration and operation of the data processing apparatus according to the first embodiment will be described with reference to FIGS. As shown in FIG. 1, the central processing unit (CP
The U) 110 executes predetermined data processing by executing various application programs developed in the system memory 120. At this time, FPGA1
Configuration memory (RAM) 15 in 50
By dynamically changing (downloading) the configuration data to be downloaded to the server 3, various data processes can be dynamically switched and processed.

Hereinafter, the operation of downloading to the configuration memory (RAM) 153 in the FPGA 150 will be described with reference to FIGS. Central processing unit (CPU) 110, file storage device 140, FP shown in FIG.
The GA 150 is configured, for example, as shown in FIG. That is, under the control of the microprogram, the central processing unit (CPU) 110 transfers the configuration data from the HD to the RAM stored in the file storage device 140, downloads from the RAM to the FPGA, and downloads the data to the FPGA. By executing the download, the operation shown in FIG. 4 is executed.

First, the operation of the transfer of the configuration data from the HD to the RAM will be described with reference to the flowchart of the processing shown in FIG. 2, the correspondence diagram of the configuration data → RAM shown in FIG. 3, and the flowchart shown in FIG. explain.

In FIG. 1, when the power is turned on, a central processing unit (CPU) 110
→ Execute the transfer of the RAM configuration data. The file storage device 140 stores configuration data 14 such as program data for each function.
1 to 145 are stored in advance.

Therefore, a central processing unit (CPU) 110
Outputs an address to the file storage device (HD) 140 via the device I / F unit 130, and
20 and outputs the RAM address to the file storage device (H
D) Perform configuration data transfer operation from 140 to system memory 120. And HD → RA
This operation is repeated until the M data transfer operation is completed (step S401 shown in FIG. 4).

Thereafter, when the HD → RAM data transfer operation is completed, the central processing unit (CPU) 110 executes a download start program from the RAM → FPGA in the system memory 120 to thereby execute the system memory 12
FP with the configuration data copied to 0
GA150 configuration memory (RAM)
Download to 153. As a result, after the configuration data is transferred from the file storage device (HD) 140 to the system memory 120, it is downloaded from the system memory 120 to the configuration data memory (RAM) 153 in the FPGA 150 (FIG. 2). 201 shown in FIG. 4, step S40 shown in FIG.
2).

After the download processing, the central processing unit (CP
The U) 110 registers the downloaded configuration information in the system memory 120 (Step S403 shown in FIG. 4).

Next, the central processing unit (CPU) 110
Execute the processing operation corresponding to the downloaded function. Note that the initial function of downloading may be a function of fixing the internal state of the FPGA 150 during the period in which another function download request is determined, or may perform a processing operation (202 in FIG. 2, FIG. Step S404 shown in FIG. 4).

Next, an operation when the central processing unit (CPU) 110 receives a request for downloading another function will be described.
That is, the central processing unit (CPU) 110 transfers the configuration data from the file storage device 140 or the system memory 120 to the system memory 120, and then downloads the configuration data from the system memory 120 to the FPGA 150.

The central processing unit (CPU) 110 stores the configuration data of another function in the configuration data memory (RAM) 15 of the FPGA 150.
3 and reset the FPGA function to a predetermined function. When downloading to this FPGA 150,
The current download state of the FPGA 150 is determined by the central processing unit (CPU) 110, and control is made to which address area of the configuration data memory (RAM) 153 of the FPGA 150 to download configuration data of another function. (Corresponding to the configuration file → RAM in FIG. 3).

The above processing will be described in more detail with reference to the flowchart shown in FIG. That is, the central processing unit (CP
U) 110, upon receiving a function change request to the FPGA 150 (step S405 shown in FIG. 4),
Then, the number of the configuration data that is functioning as described above is compared with the number of the configuration data for which a function change has been requested (step S406 shown in FIG. 4).
Here, in the case of a partial function change, the FPGA 150
Assuming that the configuration data of the common function has already been downloaded, only the configuration data for which the function change request of the partial function has been requested is transferred to the system memory 120 (step S4 shown in FIG. 4).
See 10｝.

Next, the central processing unit (CPU) 110
The operation proceeds to the operation of downloading from the RAM to the FPGA. First,
The central processing unit (CPU) 110 includes the system memory 12
0 is output to the device I / F unit 13
0, the address to be changed is output to the configuration data memory (RAM) 153 of the FPGA 150, one word of the download data is output from the system memory 120 to the FPGA 150, and the download data 1 is output.
After outputting the word, the address is updated, and one download data of the next one word is output. The above operation is repeated until the download is completed, and the configuration / configuration change request for the partial function is stored in the area B (see FIG. 3) of the configuration data memory (RAM) 153.
Download the data (203 shown in FIG. 2, FIG. 4
Step S411).

Thereafter, when the download operation is completed,
The central processing unit (CPU) 110 registers the number of the downloaded configuration data (step S412 shown in FIG. 4).

The processing in steps S410 to S412 corresponds to the above-described partial function change processing from the file storage device to the FPGA.

Next, a description will be given of a process in the case where all the functions are changed in the comparison in step S406 described above.

In step S406, if all the functions are changed, it is assumed that the configuration data of the common function has not been downloaded to the FPGA 150, and the configuration data requested to change the functions of all the functions is stored in the system memory 2. (Step S407 shown in FIG. 4).

Next, the central processing unit (CPU) 110
The operation proceeds to the operation of downloading from the RAM to the FPGA. First,
The central processing unit (CPU) 110 includes the system memory 12
0 is output to the device I / F unit 13
0, the address to be changed is output to the configuration data memory (RAM) 153 of the FPGA 150, one word of the download data is output from the system memory 120 to the FPGA 150, and the download data 1 is output.
After outputting the word, the address is updated, and one download data of the next one word is output. The above operation is repeated until the download is completed, and the configuration data requested to change the functions of all the functions is downloaded to the area A (see FIG. 3) of the configuration data memory (RAM) 153 (see FIG. 2). 209, and step S408 shown in FIG. 4).

Thereafter, when the download operation is completed,
The central processing unit (CPU) 110 registers the number of the configuration data just downloaded (step S409 shown in FIG. 4).

The processing in steps S407 to S409 described above corresponds to the above-described processing for changing all functions from the file storage device to the FPGA.

Next, when the above-described configuration data registration processing is completed, the central processing unit (CPU)
110 executes a processing operation corresponding to the downloaded function (210 shown in FIG. 2, step S4 shown in FIG. 4)
13).

When the processing operation corresponding to the downloaded function is completed, the central processing unit (CPU) 11
In step S405, the process returns to step S405 to wait for the above-described function change request to the FPGA.

The above-mentioned transfer means controls the download of the FPGA configuration data stored in the device such as the file storage device (HD) 4 to the FPGA. A configuration may be adopted in which configuration data is downloaded or new data is stored in the file storage device 4.

As described above, the configuration data of the field programmable gate array (FPGA) 5 that determines the function of the predetermined hardware is stored in the configuration of the field programmable gate array (FPGA) 5 in the hardware. In a data processing device having a function of downloading to the configuration memory (RAM) 53, at the time of initialization such as when the power is turned on, the entire area of the configuration memory previously stored from the file storage device (HD) 4 is stored. The configuration data of the program A is downloaded to a configuration memory (RAM) 53 in the field programmable gate array (FPGA) 5, and after the program is downloaded, a part of the configuration memory is downloaded. The configuration data of the program is downloaded to a configuration memory (RAM) 53 in the field programmable gate array (FPGA) 5, and a field programmable gate for determining a function of a predetermined hardware is configured. The configuration data of the array (FPGA) 5 is stored in the field programmable gate array (FPGA) in the hardware.
In the data processing device having a function of downloading to the configuration memory (RAM) 53 in the configuration 5, the configuration stored in advance from the file storage device (HD) 4 or the like at initialization such as when the power is turned on. Configuration data of the program A for the entire area of the configuration memory is downloaded to the configuration memory (RAM) 53 in the field programmable gate array (FPGA) 5, and after the program A is downloaded, a plurality of prepared configurations are prepared. The configuration data of a plurality of programs in a part of the configuration memory is selected for each hardware function, and the configuration memory (R) in the field programmable gate array (FPGA) 5 is selected.
AM) 53 so that it can be downloaded to
The following effects can be obtained. (1) As a memory for storing configuration data, the system memory 2 is used and downloaded from the system memory 2 to the RAM 53 in the FPGA 5 to enhance flexibility. (2) Download configuration data, such as program data, to the FPGA 5 to prevent a reduction in speed due to data transfer of re-initialization (re-configuration) and to stabilize the circuit at power-on, and then, if necessary, Then, the configuration data of the program data for partially rewriting a part of the configuration memory (RAM) 53 in the FPGA 5 is transferred, and only the necessary part is rewritten, thereby re-initializing (re-configuring). Data transfer speed can be prevented from lowering due to data transfer or the like. (3) The configuration of the RAM 53 in the FPGA 5 from the outside of the hardware (the external storage device 7 or the like) is not sufficient because the expandability is poor only by downloading from the file storage device 4 in the hardware. By realizing the transfer of the configuration data of the program data that partially rewrites a part of the (RAM) 53, it is possible to prevent a decrease in the data transfer speed while improving the expandability.

[Second Embodiment] Next, as a second embodiment of the present invention, an image processing apparatus using a RAM-type FPGA for determining the functions of predetermined hardware will be described.

FIG. 6 is a block diagram showing the configuration of the image forming apparatus according to the second embodiment. In FIG.
Reference numeral 0 denotes a central processing unit (CPU) that executes image processing by executing various application programs developed in the system memory. A system memory 620 registers configuration data and the like. Reference numeral 630 denotes a file storage device that stores data used for various image processing described later. Reference numeral 640 denotes an image input device (hereinafter, referred to as a "reader unit"), which optically reads a document and converts it into image data. Reference numeral 650 denotes an image output device (hereinafter, referred to as a "printer unit") having a plurality of types of recording paper cassettes and outputting image data as visible images on recording paper in accordance with a print command. A computer I / F 660 receives page description language (PDL) code data from a host computer or the like (not shown). Reference numeral 670 denotes a fax unit.
1 is a telephone line. Reference numeral 680 denotes an image processing unit which has an FPGA function unit and a RAM therein, and executes various image processing based on downloaded configuration data.

Hereinafter, the details of the above-described units will be sequentially described.

<Description of Reader Unit 640> FIG. 7 is a sectional view showing the configuration of the reader unit 640 and the printer unit 650 shown in FIG. First, the configuration and operation of the reader unit 640 will be described.

In FIG. 7, originals stacked on an original feeder 701 are sequentially conveyed one by one onto a glass platen surface 702. When the documents are sequentially transported, the lamp 703 of the scanner unit is turned on, and the scanner unit 704 moves to irradiate the documents. The reflected light from the original is
After passing through a converging lens 708 sequentially through 05, 706 and 707, it is input to a CCD image sensor unit 709 (hereinafter referred to as "CCD").

FIG. 8 is a block diagram showing signal processing in image processing section 680. First, in the case of copy processing, C
The image information input to the CD 709 is photoelectrically converted and converted into an electric signal, and is subjected to A / D conversion 801, shading correction 802, resolution conversion 803, edge enhancement 804, and binarization processing 805. In the case of printer processing,
PDL received via computer I / F section 660
The code data is subjected to PDL expansion 807. Next, in the case of a fax transmission process, a binarization process 808 and an encoding 809 are performed on the image data to be transmitted, and the fax unit 670
Sent to Then, in the case of the fax receiving process, the image data input from the fax unit 670 is decoded 8
11, resolution conversion 812 is performed.

The detailed configuration and operation of the image processing unit 680 will be further described later.

<Description of Printer Unit 650> Returning to FIG. 7, the configuration and operation of the printer unit 650 will be described. The signal input to the printer unit 650 is converted into a light signal by the exposure control unit 710 according to the image signal converted into the optical signal.
Irradiate 1. The latent image generated on the photoconductor 711 by the irradiation light is developed by the developing device 712. Here, the transfer paper stacking unit 713 is combined with development and timing.
Alternatively, transfer paper is conveyed from 714, and the above-described developed image is transferred by the transfer unit 715. The transferred image is fixed on the transfer sheet by a fixing unit 716, and then discharged outside the apparatus from a paper discharge unit 717. The transfer paper output from the paper discharge unit 717 is discharged to each bin when the sort function of the sorter 720 is operating, or to the uppermost bin of the sorter when the sort function is not active. . When the sequentially read images are output on both sides of one output sheet, the output sheet fixed by the fixing unit 716 is once conveyed to the discharge unit 717, and then the conveyance direction of the sheet is reversed to switch the conveyance direction. Transfer paper loading section 7 for refeeding via member 718
Conveyed to 19. When the next original is prepared, the original image is read in the same manner as in the above-described process. However, since the transfer paper is fed from the re-feeding receiving paper stacking section 719, the same output paper is eventually obtained. Two original images are output on the front and back sides.

<Description of Computer I / F Unit 660> The computer I / F unit 660 is an interface unit connected to a computer, receives code data in a page description language (hereinafter, “PDL”) from the computer,
The code data is output to the image processing unit 680.

<Explanation of Fax Unit 670> The fax unit 670 for performing fax transmission / reception is connected to a telephone line 671, and the telephone line 671 exchanges information with an exchange installed at a telephone office or the like according to a predetermined procedure. At the time of fax transmission, the coded information output from the image processing unit 680 is modulated, and the fax information is transmitted over the telephone line 671 via an NCU (not shown). When receiving a fax,
Fax information is received from the telephone line 671 via the NCU, the information is demodulated, and encoded information is output to the image processing unit 13.

<Description of Image Processing Unit 680> The operation of each function of the image processing unit 680 will be described below in order.

FIG. 9 is a diagram showing functions of the FPGA in the image processing unit 680 in each operation of the image processing apparatus. (1) Initial operation (when power is turned on and when resetting) First, the central processing unit (CPU) 610
/ O functions 910 and 930, configuration data and through data of I / O layout data 631 stored in advance from a file storage device (HD) 630 to set a through process 920 that does not process an input signal. 632 and the configuration data of the FP via the system memory 620 and the system bus 690.
Download to RAM in GA.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. As described above, by the download of the initial operation, the function of the FPGA in the image processing unit 680 is set to the initial setting state shown in FIG. (2) Copy Operation (Image Data Read by Reader Unit 640 is Output by Printer Unit 650) Next, a procedure of the copy operation will be described following the above-described initial operation. The central processing unit (CPU) 610 compares the configuration information registered in the system memory 620 with the function of the copying operation required by the image processing unit 680, and
The blocks in the PGA that require a change in the function of the RAM are changed as follows.

As in the copying process shown in FIG. 9, the central processing unit (CPU) 610 controls the uneven light distribution of the lamp 703 and the CC.
Shading processing 80 for correcting sensitivity unevenness in D709
2. Resolution conversion (1) processing 803 for converting multivalued data into resolution, edge enhancement processing 804 for performing edge enhancement by enhancing the high-frequency components of the signal from resolution conversion (1) processing 803, multivalued (8 bits) Configuration of shading data 633 stored in advance from a file storage (HD) 630 to set a binarization process (1) 805 for converting data into binary (1 bit) data optimal for the printer unit 650 The system memory 62 stores the data, the resolution conversion (1) configuration data of the data 634a, the configuration data of the edge enhancement data 635, and the binarization processing (1) the configuration data of the data 636a.
0, download 940, 941, 942, 943 to the RAM in the FPGA via the system bus 690.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. As described above, by the download of the initial operation, the function of the FPGA in the image processing unit 680 is set to the copy processing state shown in FIG. (3) Printer output (document sent via computer I / F section 660 is output by printer section 650) Next, the procedure of the printer output operation following the above-described copying operation will be described. The central processing unit (CPU) 610 compares the configuration information registered in the system memory 620 with the function of the printer output operation required by the image processing unit 680, and determines a block that needs to change the function of the RAM in the FPGA. Change as follows.

As in the printer processing shown in FIG. 9, the central processing unit (CPU) 610 includes a computer I / F unit 660.
PDL expansion processing 807 for expanding command data such as a document file sent through the CAM into image data
In order to set the through processing 920, the configuration data of the PDL expanded data 639 and the configuration data of the through data 632 stored in advance from the file storage device (HD) 630 are stored in the system memory 620 and the system bus 690. Through the FPGA
Download 944, 945 to the RAM inside.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. As described above, by downloading the initial operation, the functions of the FPGA in the image processing unit 680 are set to the printer processing state shown in FIG. (4) Facsimile apparatus (image data read by reader section 640 is transmitted by facsimile section 670) Next, a procedure of a facsimile transmission operation following the above-described printer output operation will be described. Central processing unit (CPU)
Reference numeral 610 compares the configuration information registered in the system memory 620 with the function of the facsimile transmission operation required by the image processing unit 680, and changes the blocks in the FPGA in which the functions of the RAM need to be changed as follows.

As in the facsimile transmission processing shown in FIG. 9, a central processing unit (CPU) 610 performs shading processing 802 for correcting uneven light distribution of the lamp 703 and uneven sensitivity of the CCD 709, and resolution for converting multi-valued data into resolution. Conversion (1) processing 803, binarization processing (2) 808 for converting multi-valued (8-bit) data into binary (1 bit) data optimal for facsimile transmission, and image information MH, M
In order to set an encoding process 809 for encoding in a desired format of the R, MMR format, the file storage device (HD) 6
30 to the previously stored shading data 63
3, the configuration data of resolution conversion (1) data 634a, the configuration data of binarization processing (2) data 636b, and the configuration data of encoded data 637 The data is downloaded 946, 947, 948, 949 to the RAM in the FPGA via the memory 620 and the system bus 690.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. As described above, by downloading the facsimile transmission operation, the FPG in the image processing unit 680 is downloaded.
The function A has the facsimile transmission processing state shown in FIG. (5) Facsimile reception (image data received by facsimile unit 670 is output by printer unit 650) Next, the procedure of the facsimile reception operation following the above-described facsimile transmission operation will be described. Central processing unit (CP
U) 610 compares the configuration information registered in the system memory 620 with the function of the facsimile reception operation required in the image processing unit 680, and compares the RA in the FPGA.
Blocks that require a change in the function of M are changed as follows.

As in the facsimile reception process shown in FIG. 9, the central processing unit (CPU) 610
A decoding process 811 for decoding in a desired format of the H, MR, and MMR formats is used to convert binary (1 bit) data to multi-level (8 bi
t) Resolution conversion (2) processing 812 for converting data to data and resolution conversion for multi-valued data, and binarization processing (1) for converting multi-valued (8 bits) to binary (1 bit) data optimal for the printer unit 650. In order to set 805, the configuration data of the decoded data 638 stored in advance from the file storage device (HD) 630, the configuration data of the resolution conversion (2) data 634b, and the binarization processing (1) The configuration data of the data 636a and the configuration data of the through data 632 are downloaded 950, 951, 952, and 953 to the RAM in the FPGA via the system memory 620 and the system bus 690.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. As described above, by downloading the facsimile reception operation, the FPG in the image processing unit 680 is downloaded.
The function A has the facsimile reception processing state shown in FIG.

Hereinafter, an example of a series of processing will be described. (1) Initial Operation to Copy Operation Immediately after the power is turned on, the central processing unit (CPU) 610 reads the F stored in advance from the file storage device (HD) 630.
The configuration data of the I / O layout data 631 for setting the I / O function of the PGA and the configuration data of the through processing data 632 that does not process the input signal are transmitted via the system memory 620 and the system bus 690. FP constituting image processing unit 680
It is downloaded to the RAM in the GA, the internal functions of the FPGA are fixed, the functions of the image processing unit 680 are stabilized, and the power consumption is reduced. Thereafter, the CPU 610 registers the configuration information downloaded into the FPGA in the system memory, and enters a standby state.

Next, when the copying function is selected, the central processing unit (CPU) 610 compares the configuration information registered in the system memory 620 with the functions required by the image processing unit 680 for the copying operation. , RA in FPGA
Blocks that require a change in the function of M are changed as follows.

In this example, since the configuration information registered in the system memory 620 has the initial setting function downloaded to the FPGA, the central processing unit (CPU) 610 performs shading processing 802 necessary for the copying function and resolution conversion. (1) shading data 633 of configuration data corresponding to processing 803, edge enhancement processing 804, and binarization processing (1) 805;
Resolution conversion (1) data 634a, edge emphasis data 6
35, binarization processing (1) The configuration data is transferred from the data 636a to the system memory 620 via the system bus 690.

After the transfer to the system memory 620, the central processing unit (CPU) 610 sequentially downloads the configuration data from the system memory 620 to a predetermined RAM in the FPGA.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory.

When all downloads have been completed, central processing unit (CPU) 610 communicates with reader unit 640 and issues a document scan command. The reader unit 640 outputs image information to the image processing unit 680 when the scanner unit 704 scans a document according to this command. The reader unit 640 and the image processing unit 680 are connected by a cable, and information from the reader unit 640 is input.
The image information input to the image processing unit 680 is a multi-valued 8 bi
t is input to a buffer (not shown) through a signal line,
Input to the FPGA via the buffer circuit.

The image information input to the FPGA is an FPG
The data is input to the shading process 802 via the I / O block 910 in A, where the uneven light distribution of the lamp 703 and the uneven sensitivity of the CCD 709 are corrected. Then, the signal from the shading processing 802 is input to the resolution conversion (1) processing 803.

The magnification is changed in the sub-scanning direction according to the scanning speed of the scanner unit 704, and the resolution conversion (1) processing 8
03 performs magnification in the main scanning direction. In the resolution conversion (1) processing 803, high-resolution data can be converted in real time, so that high image quality can be maintained.

The resolution-converted image information is input to edge enhancement processing 804, and the edge enhancement processing 804 enhances the high-frequency components of the signal from the resolution conversion (1) processing 803 to obtain edge enhancement information.

Next, the signal from the edge emphasis processing 804 is input to the binarization processing (1) 805, and in the binarization processing (1) 805, the multi-valued (8b)
it) data is the optimal binary (1 bi
t) Converted to data. The binary data from the binarization processing (1) 805 is input to the through processing 920, and is output without processing the signal from the binarization processing (1) 805 in the through processing 920.

The signal from the through processing 920 is output from the FPGA via the I / O block 930. FPG
The signal from A is output from the image processing unit 680. The signal from the image processing unit 680 is input to the printer unit 650, and an image is formed as a visible image. (2) Copying Operation to Printer Operation Next, when the printer function is selected, the central processing unit (C
The PU 610 compares the configuration information registered in the system memory 620 with the function of the printer operation required by the image processing unit 680, and
Block 3 requiring a function change is changed as follows.

In this example, the configuration information registered in system memory 620 indicates that the copying function is FP.
Because it has been downloaded to GA, the central processing unit (C
PU) 610 is a PDL expansion process 80 necessary for the copy function
7, PDL expansion data 639 of configuration data corresponding to the through processing 920, and through processing data 632 are transferred to the system memory 6 via the system bus 690.
20 to transfer the configuration data.

After the transfer to the system memory 620, the central processing unit (CPU) 610 sequentially downloads the configuration data from the system memory 620 to a predetermined RAM in the FPGA.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory 620. When all the downloads are completed, the CPU 610 communicates with the computer I / F unit 660 and issues an input instruction of PDL code data such as a document file. The computer I / F unit 660 outputs PDL code data from the computer to the image processing unit 680 according to this command. Computer I / F 66
0 and the image processing unit 680 are connected by a cable, and information from the computer I / F unit 660 is input. The PDL code data input to the image processing unit 680 is F
Input to PGA.

The image information input to the FPGA is an FPG
PDL expansion processing 8 via I / O block 910 in A
07, where the code data is sequentially developed into image data. Then, the signal from the PDL expansion processing 807 is input to the through processing 920,
At 20, the signal from the PDL expansion processing 807 is output without processing.

The signal from the through processing 920 is input to the edge enhancement processing 804, and edge enhancement information is obtained by enhancing the high-frequency components of the signal from the through processing 920 in the edge enhancement processing 804. Edge enhancement processing 804
Is input to the binarization processing (1) 805,
In the binarization processing (1) 805, the multi-valued (8-bit) data from the edge enhancement processing 804 is converted into binary (1-bit) data optimal for the printer unit 650.

The binarized signal from the binarization processing (1) 805 is input to the through processing 920, and the signal from the binarization processing (1) 805 is output without being processed by the through processing 920. The signal from the through processing 920 is output from the FPGA via the I / O block 930. And F
The signal from the PGA is output from the image processing unit 680.
The signal from the image processing unit 680 is input to the printer unit 650, and an image is formed as a visible image. (3) Facsimile Transmission Operation From Printer Operation Next, when the facsimile transmission function is selected, the central processing unit (CPU) 610 transmits the configuration information registered in the system memory 620 and the facsimile transmission required by the image processing unit 680. Compare the function of operation and
Blocks that require a change in the function of the RAM in A are changed as follows.

In this example, the configuration information registered in the system memory 620 has the printer function downloaded to the FPGA, so the central processing unit (CPU) 610 performs shading processing 802 and resolution conversion necessary for the facsimile transmission function. (1) Process 803,
The shading data 633 of the configuration data corresponding to the binarization processing (2) 808 and the encoding processing 809, the resolution conversion (1) data 634a, the binarization processing (2) data 636b, and the encoded data 637 are transmitted to the system bus. The configuration data is transferred to the system memory 620 via the 690.

After the transfer to the system memory 620, the central processing unit (CPU) 610 sequentially downloads the configuration data from the system memory 620 to a predetermined RAM in the FPGA.

After that, the CPU 610 registers the configuration information downloaded to the FPGA in the system memory. When all downloads are completed, the CPU
A communication unit 610 communicates with the reader unit 640 and issues a document scanning instruction. The reader unit 640 outputs image information to the image processing unit 680 when the scanner unit 704 scans a document according to this command. Reader unit 640
And the image processing unit 680 are connected by a cable, and information from the reader unit 640 is input. Image processing unit 680
Is input to a buffer (not shown) via a multi-valued 8-bit signal line, and is input to an FPGA via a buffer circuit.

The image information input to the FPGA is an FPG
The data is input to the shading process 802 via the I / O block 910 in A, where the uneven light distribution of the lamp 703 and the uneven sensitivity of the CCD 709 are corrected. The signal from the shading process 802 is converted into a resolution conversion (1) process 803
Is input to

The magnification in the sub-scanning direction is changed according to the scanning speed of the scanner unit 704, and the resolution conversion (1) processing 8
03 performs magnification in the main scanning direction. In the resolution conversion (1) processing 803, high-resolution data can be converted in real time, so that high image quality can be maintained.

The resolution-converted image information is input to the edge enhancement processing 804, and the edge enhancement processing 804 enhances the high-frequency components of the signal from the resolution conversion (1) processing 803 to obtain edge enhancement information. The signal from the edge enhancement processing 804 is input to the binarization processing (2) 808, and the edge enhancement processing 804 is performed in the binarization processing (2) 808.
(8-bit) data is converted into binary (1-bit) data optimal for facsimile transmission. The binarization processing from the binarization processing (2) 808 is input to the encoding processing 809, and the binarization processing (2) 808 is performed by the encoding processing 809.
Is encoded in a desired format of the MH, MR, MMR system. The encoded information is output from the FPGA via the I / O block 930. The signal from the FPGA is output from the image processing unit 680.

The signal from image processing section 680 is input to facsimile section 670, which modulates the coded information so as to transmit the coded information to telephone line 671.
It is directly connected to 71 and exchanges information with an exchange installed at a telephone office or the like according to a predetermined procedure. (4) Facsimile Transmission Operation to Facsimile Reception Operation Next, when the facsimile reception function is selected, the central processing unit (CPU) 610 receives the configuration information registered in the system memory and the facsimile reception required by the image processing unit 680. The function of the operation is compared with the function of the RAM in the FPGA, and the blocks that need to be changed are changed as follows.

In this example, since the facsimile transmission function of the configuration information registered in the system memory has been downloaded to the FPGA, the central processing unit (CPU) 610 performs decoding processing 811 necessary for the facsimile transmission function. Resolution conversion (2) processing 812, binarization processing (1) 805, decoded data 638 of configuration data corresponding to through processing 920, resolution conversion (2) data 634b, binarization processing (1) data 636a , The through processing data 632 to the system bus 69.
0, the configuration data is transferred to the system memory 620.

After the transfer to the system memory 620, the central processing unit (CPU) 610 sequentially downloads the configuration data from the system memory 620 to a predetermined RAM in the FPGA. After that, CPU6
Reference numeral 10 registers the configuration information downloaded to the FPGA in the system memory 620.

When all downloads have been completed, central processing unit (CPU) 610 communicates with facsimile unit 670 and issues a facsimile reception command. Fax unit 670
Outputs the demodulated encoded information transmitted from the telephone line 671 to the image processing unit 680 according to this command. The fax unit 670 and the image processing unit 680 are connected by a cable, and information from the fax unit 670 is input. The encoded information input to the image processing unit 680 is
Input to FPGA.

The encoding information input to the FPGA is FP
Decoding process 81 via I / O block 910 in GA
1 and the signal from the I / O block 910 is M
Decoding is performed in a desired format of H, MR, and MMR.
Here, the coded information is converted as image information. The signal from the decoding processing 811 is input to the resolution conversion (2) processing 812.

In the resolution conversion (2) processing 812, magnification is changed. In the resolution conversion (2) processing 812, conversion of binary to multi-value data and resolution conversion are performed. The resolution-converted image information is input to the edge enhancement processing 804, and the edge enhancement processing 804 enhances the high-frequency component of the signal from the resolution conversion (2) processing 812 to obtain edge enhancement information.

The signal from the edge emphasis processing 804 is input to the binarization processing (1) 805, and the binarization processing (1) 80
In step 5, the multi-valued (8-bit) data from the edge enhancement processing 804 is converted into binary (1-bit) data optimal for the printer unit 650. The binarized signal from the binarization processing (1) 805 is input to the through processing 920, and the through processing 920
Then, the signal from the binarization processing (1) 805 is output without being processed.

The signal from the through processing 920 is output from the FPGA via the I / O block 930. FPG
The signal from A is output from the image processing unit 680. The signal from the image processing unit 680 is input to the printer unit 650, and an image is formed as a visible image.

As described above, in the data processing device provided with the RAM type FPGA for determining the function of the predetermined hardware, the entire area of the configuration data memory (RAM) is initialized when the power is turned on or the like. The configuration data is stored in a RAM-type FPGA memory (RA
M), and when there is a function change request from the external control device or the like to the FPGA. When downloading the configuration data, the data type that has already been configured in the memory (RAM) of the FPGA, Compares the type of data for which configuration was newly requested, and if the comparison result indicates a common function, the configuration / request for changing the function of the partial function
The flexibility can be improved by downloading the data to the corresponding RAM area of the FPGA.

The present invention can be applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), and can be applied to a single device (for example, a copier, a facsimile). Device).

Further, an object of the present invention is to supply a storage medium storing program codes of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (CPU or MP) of the system or apparatus.
It goes without saying that U) can also be achieved by reading and executing the program code stored in the storage medium.

In this case, the program code itself read from the storage medium implements the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written into a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

[0097]

As described above, according to the present invention,
The following effects can be obtained. (1) Field programmable gate array (F
PGA) and memory (RAM) for the FPGA
Since there is a mechanism for partially setting configuration data with respect to, flexibility is enhanced. (2) The file storage device has a plurality of configuration data for the entire memory area of the FPGA and configuration data for a partial memory area of the FPGA, and registers the configuration data for each function. Since it has a function, it can be efficiently managed by an additional function and an overwrite function. In other words, there is no need to have extra configuration data on the file storage device, and by partially rewriting the RAM of the FPGA, the download time can be reduced and the system performance can be improved. (3) Initial configuration data is stored in a file storage device in the hardware, and the configuration data for the entire memory area of the FPGA and the configuration data for a partial memory area of the FPGA are obtained by the expansion I / F. Since it has a function of registering data, it can be efficiently managed by an additional function and an overwrite function. That is, it is not necessary to transfer extra configuration data, the download time is shortened, and the system performance can be improved.

[0098]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration and a data flow of a data processing device according to a first embodiment.

FIG. 2 is a flowchart showing download control to the FPGA shown in FIG. 1;

FIG. 3 is a diagram showing the correspondence between configuration data and RAM.

FIG. 4 is a flowchart illustrating a process of downloading configuration data to an FPGA.

FIG. 5 is a diagram illustrating a configuration technique of a conventional data processing device.

FIG. 6 is a block diagram illustrating a configuration of an image forming apparatus according to a second embodiment.

FIG. 7 shows a reader unit 640 and a printer unit 65 shown in FIG.
FIG. 2 is a cross-sectional view showing a configuration of a zero.

FIG. 8 is a block diagram illustrating signal processing in an image processing unit 680.

FIG. 9 is an image processing unit 68 in each operation of the image processing apparatus.
FIG. 3 is a diagram showing functions of the FPGA within 0.

[Explanation of symbols]

110 Central Processing Unit (CPU) 120 System Memory 130 Device Interface (I / F) 140 File Storage (HD) 141 Configuration Data of Program A 142 Configuration Data of Program B 143 Configuration Data of Program C 144 Configuration data of program D 150 Field programmable gate array (FPGA) 152 FPGA function unit 153 Configuration memory of FPGA (R
AM) 160 Extended interface (I / F) unit 170 Host PC

Claims (9)

[Claims] 1. Data having a function of downloading configuration data of a field programmable gate array for determining a function of predetermined hardware to a configuration memory in a field programmable gate array in the hardware. In the processing device, when executing a desired data processing, a download unit for downloading only necessary configuration data to a configuration memory in the field programmable gate array according to the data processing is provided. A data processing device characterized by the above-mentioned. 2. The data processing device according to claim 1, wherein the download unit transfers only the necessary configuration data from an external device via an interface connected to the data processing device. 3. The data processing apparatus according to claim 1, wherein said data processing is image processing for processing input image data. 4. The data processing apparatus according to claim 3, wherein the download unit selects and downloads configuration data to be downloaded according to the image processing. 5. A data having a function of downloading configuration data of a field programmable gate array for determining a function of predetermined hardware to a configuration memory in a field programmable gate array in the hardware. In the processing method of the processing device, a download step of downloading only necessary configuration data to a configuration memory in the field programmable gate array according to the data processing when executing a desired data processing. A processing method for a data processing device, comprising: 6. The data processing apparatus according to claim 5, wherein in the download step, only the necessary configuration data is transferred from an external device via an interface connected to the data processing apparatus. Processing method. 7. The processing method according to claim 5, wherein said data processing is image processing for processing input image data. 8. The processing method according to claim 7, wherein in the download step, configuration data to be downloaded is selected and downloaded according to the image processing. 9. Data having a function of downloading configuration data of a field programmable gate array for determining a function of predetermined hardware to a configuration memory in a field programmable gate array in the hardware. A computer-readable storage medium storing a program code of a processing method in a processing device, wherein when performing a desired data processing, only necessary configuration data is stored in the field-programmable program according to the data processing. A storage medium having a code of a download step for downloading to a configuration memory in a gate array.