JP2000077826A - Manufacture of circuit board - Google Patents
Manufacture of circuit boardInfo
- Publication number
- JP2000077826A JP2000077826A JP10259391A JP25939198A JP2000077826A JP 2000077826 A JP2000077826 A JP 2000077826A JP 10259391 A JP10259391 A JP 10259391A JP 25939198 A JP25939198 A JP 25939198A JP 2000077826 A JP2000077826 A JP 2000077826A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- layer
- circuit board
- electrolytic
- seed layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は回路基板の製造法に
関し、更に具体的に云えば、本発明は電解メッキ手段で
所要の配線パタ−ンを形成した後、その配線パタ−ンに
損傷を与えることなくシ−ド層の不要な部分を好適に除
去することの可能な回路基板の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board. The present invention relates to a method of manufacturing a circuit board capable of suitably removing an unnecessary portion of a shield layer without giving.
【0002】[0002]
【従来の技術】セミアディティブ手法で回路基板を製作
する一手段として、図2のように所要の絶縁べ−ス材1
0の一方面にクロム等の接着性金属層12を一様に形成
し、また、その接着性金属層12の表面には銅等のシ−
ド層11を形成した後、フォトレジスト等を用いてシ−
ド層11の不要部分をマスクし、次いで電解メッキ手段
で必要部分に単層又は異種金属を積層付着させて所要の
配線パタ−ン13を形成する手法がある。2. Description of the Related Art As a means for manufacturing a circuit board by a semi-additive method, a required insulating base material 1 as shown in FIG.
0, an adhesive metal layer 12 of chromium or the like is uniformly formed on one surface thereof.
After the formation of the doped layer 11, the substrate is sealed using a photoresist or the like.
A required wiring pattern 13 is formed by masking an unnecessary portion of the doped layer 11 and then depositing a single layer or a dissimilar metal on the required portion by electrolytic plating.
【0003】このような手法で形成された配線パタ−ン
13の表面には、金等の耐腐食性金属層14を被着させ
る場合もある。In some cases, a corrosion-resistant metal layer 14 such as gold is deposited on the surface of the wiring pattern 13 formed by such a method.
【0004】[0004]
【発明が解決しようとする課題】上記の如き手法で配線
パタ−ン13を形成した後には、シ−ド層11に於ける
不要な領域部分をエッチング手段で除去するものである
が、そのシ−ド層のエッチング工程時には、図3のよう
に、配線パタ−ン13側にもサイドエッチングが進行
し、この配線パタ−ン13の基部近傍が過剰に除去され
てサイドエッチング部15を生じ、その程度によっては
配線パタ−ン13が剥離するという問題が発生する。After the wiring pattern 13 is formed by the above-described method, an unnecessary region in the shield layer 11 is removed by etching means. In the step of etching the negative layer, side etching also proceeds on the wiring pattern 13 side as shown in FIG. 3, and the vicinity of the base of the wiring pattern 13 is excessively removed to form a side etching portion 15, Depending on the degree, the problem that the wiring pattern 13 is peeled off occurs.
【0005】このような問題は、配線パタ−ン13を微
細に形成する必要がある場合には特に顕著な影響を及ぼ
すので、解決すべき重大な課題となる。Such a problem is a serious problem to be solved since it has a particularly significant effect when the wiring pattern 13 needs to be finely formed.
【0006】本発明は、そこで、電解メッキ手段で所要
の配線パタ−ンを形成した後、その配線パタ−ンに損傷
を与えることなくシ−ド層の不要な部分を好適に除去す
ることの可能な回路基板の製造法を提供するものであ
る。Accordingly, the present invention provides a method of forming a desired wiring pattern by electrolytic plating, and preferably removing unnecessary portions of a shield layer without damaging the wiring pattern. A possible method of manufacturing a circuit board is provided.
【0007】[0007]
【課題を解決するための手段】その為に本発明による回
路基板の製造法では、シ−ド層を用いた電解メッキ手段
により絶縁べ−ス材上に所要の配線パタ−ンを形成する
回路基板の製造法に於いて、前記配線パタ−ンの形成後
に電解剥離手段で前記シ−ド層の不要な部分を除去する
ものである。Therefore, in the method of manufacturing a circuit board according to the present invention, a circuit for forming a required wiring pattern on an insulating base material by electrolytic plating means using a shield layer. In the method of manufacturing a substrate, unnecessary portions of the shield layer are removed by electrolytic stripping means after the formation of the wiring pattern.
【0008】ここで、前記配線パタ−ンの表面には耐腐
食性金属層を形成しておくこともできる。Here, a corrosion-resistant metal layer may be formed on the surface of the wiring pattern.
【0009】[0009]
【発明の実施の形態】以下、図示の実施例を参照しなが
ら本発明を更に説明する。図1に示すように所要の回路
基板を製作する為には、先ず所要の絶縁べ−ス材7の一
方面にクロム等の接着性金属層6を一様に形成し、ま
た、その接着性金属層6の表面には銅等のシ−ド層5を
形成した後、フォトレジスト等を用いてシ−ド層5の不
要部分をマスクし、次いで電解メッキ手段で必要部分に
銅等の導体の単層又は異種金属を積層付着させて所要の
配線パタ−ン4を形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be further described below with reference to the illustrated embodiments. As shown in FIG. 1, in order to manufacture a required circuit board, first, an adhesive metal layer 6 such as chromium is uniformly formed on one surface of a required insulating base material 7, and the adhesive After forming a seed layer 5 of copper or the like on the surface of the metal layer 6, an unnecessary portion of the seed layer 5 is masked by using a photoresist or the like. The required wiring pattern 4 is formed by laminating a single layer or a dissimilar metal.
【0010】ここで、形成された配線パタ−ン4の表面
には金等の耐腐食性金属層3を被着形成する。Here, a corrosion-resistant metal layer 3 such as gold is formed on the surface of the formed wiring pattern 4.
【0011】この段階まで製作された回路基板は、次い
で所要の電解液2を満たした電解槽1の中に配置され、
その回路基板と対向電極8とを直流電源9に接続してシ
−ド層5の電解剥離処理に付される。The circuit board manufactured up to this stage is then placed in an electrolytic cell 1 filled with a required electrolytic solution 2,
The circuit board and the counter electrode 8 are connected to a DC power supply 9 to subject the seed layer 5 to electrolytic stripping.
【0012】この電解剥離処理工程により、シ−ド層5
の不要な部分は適切に除去され、その際に、配線パタ−
ン4の表面に金等の耐腐食性金属層3を被着形成したも
のでは、配線パタ−ン4に好ましくない損傷等を与える
虞を防止できる。By this electrolytic stripping process, the seed layer 5 is formed.
Unnecessary portions of the wiring pattern are appropriately removed,
In the case where the corrosion-resistant metal layer 3 such as gold is formed on the surface of the wiring pattern 4, it is possible to prevent the wiring pattern 4 from being undesirably damaged.
【0013】上記手法によるシ−ド層5の不要な部分の
除去処理後には、接着性金属層6の不要な部分が除去さ
れて、所要の回路基板が得られる。After the unnecessary portion of the shield layer 5 is removed by the above-described method, the unnecessary portion of the adhesive metal layer 6 is removed to obtain a required circuit board.
【0014】[0014]
【発明の効果】本発明による回路基板の製造法によれ
ば、シ−ド層を用いた電解メッキ手段により絶縁べ−ス
材上に所要の配線パタ−ンを形成する場合、配線パタ−
ンの形成後に電解剥離手段でそのシ−ド層の不要な部分
を除去するものである為、微細な配線パタ−ンの場合で
もその配線パタ−ンに損傷等を与えることなくシ−ド層
の不要な部分を好適に除去できる。According to the method of manufacturing a circuit board according to the present invention, when a required wiring pattern is formed on an insulating base material by an electrolytic plating means using a shield layer, the wiring pattern is formed.
Since unnecessary portions of the shield layer are removed by electrolytic stripping means after the formation of the pattern, even if the wiring pattern is fine, the shield layer is not damaged without damaging the wiring pattern. Unnecessary portions can be suitably removed.
【0015】従って、品質の高い回路基板を安定に製作
することができる。Therefore, a high quality circuit board can be stably manufactured.
【図1】本発明に従って回路基板のシ−ド層を電解剥離
手段で除去する工程を説明する図。FIG. 1 is a diagram illustrating a step of removing a seed layer of a circuit board by electrolytic stripping means according to the present invention.
【図2】回路基板の配線パタ−ンを電解メッキ法で形成
する為の説明図。FIG. 2 is an explanatory view for forming a wiring pattern of a circuit board by an electrolytic plating method.
【図3】シ−ド層をエッチング手段で除去する場合に発
生する問題を説明する為の図。FIG. 3 is a diagram for explaining a problem that occurs when a seed layer is removed by etching means.
1 電解槽 2 電解液 3 耐腐食性金属層 4 配線パタ−ン 5 シ−ド層 6 接着性金属層 7 絶縁べ−ス材 8 対向電極 9 直流電源 DESCRIPTION OF SYMBOLS 1 Electrolyzer 2 Electrolyte 3 Corrosion-resistant metal layer 4 Wiring pattern 5 Shield layer 6 Adhesive metal layer 7 Insulation base material 8 Counter electrode 9 DC power supply
Claims (2)
縁べ−ス材上に所要の配線パタ−ンを形成する回路基板
の製造法に於いて、前記配線パタ−ンの形成後に電解剥
離手段で前記シ−ド層の不要な部分を除去することを特
徴とする回路基板の製造法。In a method of manufacturing a circuit board, wherein a required wiring pattern is formed on an insulating base material by electrolytic plating means using a seed layer, an electrolytic plating is performed after the formation of the wiring pattern. A method of manufacturing a circuit board, comprising: removing unnecessary portions of the seed layer by a peeling means.
層を形成することを特徴とする請求項1の回路基板の製
造法。2. The method according to claim 1, wherein a corrosion-resistant metal layer is formed on a surface of said wiring pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10259391A JP2000077826A (en) | 1998-08-28 | 1998-08-28 | Manufacture of circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10259391A JP2000077826A (en) | 1998-08-28 | 1998-08-28 | Manufacture of circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000077826A true JP2000077826A (en) | 2000-03-14 |
Family
ID=17333495
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10259391A Pending JP2000077826A (en) | 1998-08-28 | 1998-08-28 | Manufacture of circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2000077826A (en) |
-
1998
- 1998-08-28 JP JP10259391A patent/JP2000077826A/en active Pending
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