JP2000068859A - Audio adaptor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To supply digital audio data to an audio device by efficiently converting a size of 1 word of the digital audio data on a computer bus. SOLUTION: Each of 8-bit data at a high-order and a middle-order of an L channel are called from an FIFO memory of a data bus, latched by a latch 112 (middle-order L channel), a latch 113 (high-order L channel), 8-bit data of the low-order L channel and 8-bit data of high-order R channel are called from the memory and latched by a latch 111 (low-order L channel), a latch 116 (high-order R channel) and of 8-bit data of the middle-order R channel and 8-bit data of low-order R channel are called from the memory and latched by a latch 114 (low-order R channel), a latch 115 (middle-order R channel). Then, the 8-bit data latched in the latches 114 (high L), 112 (middle L), 111 (low L), 116 (high R), 115 (middle R), 114 (low R) are read simultaneously and become parallel 24-bit data of the L, R channels, which are fed to parallel serial conversion circuits 12L, 12R, where they are respectively converted into L, R channel audio serial data and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an audio adapter for converting bits of a data word of a digital audio signal.

[0002]

2. Description of the Related Art In recent years, as data words of a digital audio signal have increased to 8 bits, 16 bits, 20 bits, and 24 bits, bit conversion has been performed between data words of each size to obtain another size. Conversion into data words has conventionally been performed in various forms. Under such a trend, for example, a technique of dividing 20 bits into upper 16 bits and lower 4 bits is known (Japanese Patent Laid-Open No. Hei 5
182363). In this example, 4 bits are stored in 16 bits. Therefore, two words of 16 bits make 20 words.
Bits are restored. Alternatively, for 4 bits, four channels are collectively stored in 16 bits. Also, for example,
There is known a technique in which 24 bits are divided into 16 bits and 8 bits for recording (JP-A-10-49998). In this example, a pseudo 16-bit data word is formed by 16 bits out of 24 bits, and the remaining 8 bits and 8 bits of other data words are combined to form a pseudo 16-bit data word. .

[0003]

By the way, in the above-mentioned conventional bit conversion technology, conversion of audio data on a computer bus into an audio interface format of an audio device and taking it out to the outside was not considered much.

However, in the information age, as hard disks connected to computers have increased in capacity and reduced in cost, it has been required to store and read enormous amounts of audio data on a hard disk like a conventional cassette tape. In addition, these audio data are about to become mainly 24 bits.

[0005] However, the above conventional technique has a problem in that it is not possible to supply a 24-bit data word audio signal to an audio device from a 16-bit computer bus. The reason is that there is no commonality in the data words to be handled between the general audio interface standard provided in the audio device and the bus with FIFO memory of the computer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to efficiently convert the size of one word of digital audio data on a computer bus to an audio device. The purpose is to provide an audio adapter that can be supplied.

[0007]

To achieve the above object, a first aspect of the present invention is an audio adapter for converting audio data on a 16-bit data bus with a FIFO memory into 24-bit audio data. First holding means for calling and holding the upper 8 bits of audio data of the L channel and the middle 8 bits of audio data from the FIFO memory;
Second holding means for calling and holding lower 8 bits of audio data of the L channel and upper 8 bits of audio data of the R channel from the IFO memory;
Third holding means for retrieving and holding middle 8-bit audio data of the R channel and 8-bit audio data of the same lower order from the I-FO memory; and holding the L channel from the first holding means and the second holding means. Top, middle,
First parallel-serial conversion means for converting lower 8-bit audio data into audio serial data by simultaneously calling and inputting the data, and upper and lower R channels from the second holding means and the third holding means; There is provided a second parallel-serial conversion means for converting the audio parallel data into audio serial data by simultaneously calling and inputting the middle and lower 8-bit audio parallel data.

According to the first aspect, the FIFO memory of the 16-bit data bus stores the upper 8 bits of the L channel.
8 bit audio data, the lower 8 bit audio data of the L channel, the upper 8 bit audio data of the R channel, and the lower 8 bit audio data of the R channel. A total of 48 bits of 8-bit audio data,
24-bit L and R channel audio data are stored in a first-in first-out manner. Therefore, the FIFO
The upper 8-bit audio data of the L channel and the middle 8-bit audio data are called and held from the memory, and the lower 8-bit audio data of the L channel and the upper 8-bit audio data of the R channel are called. It holds and stores the middle 8-bit audio data and the lower 8-bit audio data of the R channel, and then converts the upper, middle, and lower 8-bit audio data of the L channel into parallel data. At a time, and converting this to serial data, 24-bit L-channel audio serial data is obtained. At the same time, the upper, middle, and lower 8-bit audio data of the R channel are converted into parallel data. Is called at a time and converted to serial data. Audio serial data of the R channel is obtained. Thus, the audio data on the 16-bit width computer bus is converted into 24-bit audio data.

The second invention is characterized in that the conversion operations of the first parallel-serial conversion means and the second parallel-serial conversion means are alternately performed, and the first parallel-serial conversion means and the second parallel-serial conversion means are operated in parallel. An object is to output the L channel and R channel serial data output from the serial conversion means alternately as a series of data.

A third feature of the present invention is that a first D / D converter for converting L-channel audio serial data output from the first parallel-serial conversion means into an analog signal.
An A conversion circuit and a second D / A conversion circuit for converting R channel audio serial data output from the second parallel / serial conversion means into an analog signal are provided.

According to the third aspect, audio data on the 16-bit computer bus is converted into 24-bit audio data, which is further converted into an analog audio signal and output.

A fourth aspect of the present invention is an audio adapter for converting audio data on a 16-bit data bus with a FIFO memory into 24-bit or 16-bit audio data.
The first 8-bit audio data of the same middle order as the upper 8-bit audio data of the channel is called and held.
Holding means for calling and holding the lower 8 bits of audio data of the L channel and the upper 8 bits of audio data of the R channel from the FIFO memory.
Holding means for calling and holding middle 8-bit audio data of the R channel and 8-bit audio data of the same lower order from the FIFO memory, and the first holding means and the second holding means. First parallel-serial conversion means for converting the audio data into audio serial data by simultaneously calling and inputting the upper, middle, and lower 8-bit audio data of the L channel from the holding means; Second parallel-serial conversion means for converting audio parallel data by simultaneously calling and inputting upper, middle, and lower 8-bit audio parallel data of the R channel from the third holding means, and the FIFO memory From the upper 8 bits of audio data of the L channel
Fourth holding means for calling and holding the bit audio data, and fifth holding means for calling and holding the middle 8-bit audio data and the lower 8-bit audio data of the R channel from the FIFO memory. A third parallel / serial conversion means for converting the data into audio serial data by simultaneously calling and inputting the upper and middle 8-bit audio parallel data of the L channel from the fourth holding means, and From the fifth holding means, the middle and lower 8
A fourth parallel-serial converting means for converting the audio serial data into audio serial data by simultaneously calling and inputting the audio parallel data of 1 bit. To obtain 24-bit audio serial data, the first, second, and In order to operate the holding means of No. 3 and the first and second parallel-serial converting means to obtain 16-bit audio serial data, the fourth and fifth holding means and the third and fourth holding means Operating the parallel / serial conversion means, and using the first and third parallel conversion means as one parallel conversion means, and using the second and fourth parallel / serial conversion means as one And the parallel conversion means.

According to the fourth aspect, the audio data on the 16-bit computer bus is converted into 24-bit or 16-bit audio data.

According to a fifth aspect of the present invention, the dual-purpose parallel-serial conversion means includes a first clock system for driving a circuit element for converting 8-bit parallel data, and a circuit element for converting 16-bit parallel data. An output unit for extracting serial data to the outside is set separately from the second clock system to be driven and at the 16th and 24th bits of the serial data.

According to the fifth aspect, if the first clock system and the second clock system are connected in common and a bit clock is input, a 24-bit output portion of the serial data outputs a 24-bit serial data. The audio serial data is output, and the 16-bit output unit outputs 16-bit audio serial data. If a bit clock is input only to the second clock system, 16-bit audio serial data is output from the 24th bit output unit. As a result, the parallel-serial conversion means can be set to 16
Bits and 24 bits can be shared.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the audio adapter of the present invention. The audio adapter 1 has 8-bit latches 111 to 1
A 48-bit latch circuit 11 formed by assembling sixteen 16-bit latches, a serial conversion circuit 12L for converting parallel data held in the latches 111 to 113 of the latch circuit 11 into 24-bit serial data, and a latch 114
And a parallel-to-serial conversion circuit 12R for converting the data held in .about.116 into 24-bit serial data.

FIG. 2 is a block diagram showing an interface system of the SID standard using the audio adapter shown in FIG. In this interface system, the audio adapter 1 is connected to a 16-bit wide FIFO of a computer.
It is configured to be inserted between the data bus with memory 2 and the buffer 3. The audio adapter 1 converts the 16-bit audio data supplied from the data bus 2 into 24-bit audio serial data 100L,
After conversion to 00R, a clock 200 is attached, and these are output via a buffer 3 to a digital audio device (not shown) or the like. At this time, the operation clock 50, that is, FIFOREAD, 12SFS, RDn (n) is transmitted from the clock generation circuit 4 to the audio adapter 1 and the data bus 2.
= 1 to 3), CLK-IN is supplied. SRLOA
D and CLK-IN are supplied to CLK1 and CLK2.
RD1 is above and during latch L in FIG. 1, RD2 is below L, R
Up, RD3 is provided below R in latch R of FIG.

Next, the operation of the present embodiment will be described with reference to the timing chart of FIG. Data bus 2
Is, for example, ISA (PCI) with FIFO memory-
A BOARD computer bus uses a 16-bit width. The FIFO memory outputs 16-bit parallel data to the latch circuit 11 every time one clock is input.

First, with the first pulse of the FIFO-READ shown in FIG. 3, the data of the upper 8 bits and the data of the middle 8 bits of the first channel (L channel) are transmitted to the FIFO.
The read signal R shown in FIG.
D1 causes the latches 112 and 113 of the latch circuit 11 to
Latched.

Then, the FIFO-RE shown in FIG.
The second pulse of AD causes the lower 8
Bits of data, upper 8 bits of data of the second channel (R channel) are called from the FIFO memory,
The latch circuit 11 receives the read signal RD2 shown in FIG.
Are latched by the latches 111 and 116 of FIG.

Next, the FIFO-REA shown in FIG.
The middle 8 bits data and the lower 8 bits data of the second channel are called from the FIFO memory by the third pulse of D, and the latches 114 and 115 of the latch circuit 11 are read by the read signal RD3 shown in FIG. Latched.

As described above, the FIFO-READ and the read signal RD are used alternately (for calling), and the latch by the latch circuit 11 is performed in the 1 fs section (one cycle 9).
6K) three times, and 48-bit audio parallel data that is three times 16 bits is latched by the latch circuit 11.

Thereafter, the SLOAD of FIG.
The 8-bit data 1, 112, and 113 are simultaneously read out, become 24-bit L-channel parallel data, are input to the parallel-to-serial conversion circuit 12L, and are output to the remaining latches 114, 115, and 116. The 8-bit data is simultaneously read out, and becomes R-channel parallel data of a total of 24 bits, which is input to the parallel-serial conversion circuit 12R.

The parallel-to-serial conversion circuit 12
The data input to the L and 12R are converted into 24-bit serial data, and then the L CHOUT shown in FIG.
Then, the L-channel audio data 100L converted into serial data is RCHOUT shown in FIG. 3, and the R-channel audio data is output to the buffer 3.

According to the present embodiment, the upper 8 bits of data of the L channel and the middle 8 bits of data of the L channel are latched by the latch 11 from the 16-bit data bus 2, and then the lower 8 bits of the L channel are latched. Bit data and the upper 8 bits of data of the R channel are latched in the latch 11, and
Middle 8 bits of data for channel and lower 8 for R channel
After latching the bit data in the latch 11, the latch 1
The upper, middle, and lower 8-bit data of the L channel are simultaneously called to form 24-bit parallel data.
The lower 8 bits of data are simultaneously called to form 24-bit parallel data, and the parallel data is converted into serial data and output, so that the audio data on the 16-bit computer bus can be efficiently converted into 24-bit audio serial data. It can be converted with a simple configuration.

FIG. 4 is a block diagram showing a second embodiment of the audio adapter of the present invention. In this example,
The latch 11 is connected to the parallel / serial conversion circuits 12L and 12R.
In loading the 24-bit parallel data from the, the SLOAD-L and SLOAD-R signals are used, and the SLOAD is first placed at the top of the row in the fs section shown in FIG.
-L, the upper, middle, and lower 8-bit data of the L channel are simultaneously called from the latches 111, 112, and 113 to form 24-bit parallel data, which is loaded into the parallel-serial conversion circuit 12L and And outputs it to the OR circuit 15.

Next, at the top of the high level in the fs section shown in FIG.
The upper, middle, and lower 8-bit data of the R channel are simultaneously called from 116 to generate 24-bit parallel data, which is loaded into the parallel-serial conversion circuit 12R and converted into 24-bit audio serial data. Output to OR circuit 15.

According to the present embodiment, the OR circuit 15 outputs 24-bit L and R channel audio serial data alternately and as a series of data. Other configurations are the same as those of the first embodiment, and have the same effects.

FIG. 6 is a block diagram showing a third embodiment of the audio adapter of the present invention. In this example, the parallel-serial converters 12L and 12R have clock inputs CLK1 and CLK2, respectively, and have switches (SW1 to SW1).
The clock and the output are selected by W3). When the switches (SW1 to SW4) are switched to the 24 bits on the a side, the latch operates as follows, and the 24-bit audio serial data is supplied to the OR circuit 15 as in the above-described second embodiment. Output from

That is, as shown in FIG. 7, the upper 8 bits and the middle 8 bits of the data of the L channel are transmitted on the L and L levels of the latch.
Is latched in, then the lower 8 bits of the L channel and the upper 8 bits of the R channel are latched, and the lower 8 bits and the lower 8 bits of the R channel are latched. , Is latched below R. Thereafter, the latch data on the latches L, L, and L are simultaneously read out, and output as 24-bit parallel data from OUT1. At the same time, they are read out and output from OUT2 as 24-bit parallel data. Incidentally, the upper and lower portions of the latches L, L and L are the latches 113, 112 and 11 in FIG.
1, the upper, lower, and lower latches R are latches 116 of FIG.
115 and 114 are supported.

On the other hand, when the switches (SW1 to SW4) are switched to 16 bits on the b side, as shown in FIG. 8, the upper 8 bits of the 16 bits of the first channel (L channel) are read from the FIFO memory of the data bus. Bit and the middle 8 bits are called, and the latch signal L
Above, latched in L. Also, the middle 8 bits and the lower 8 bits of the 16 bits of the second channel (R channel) are called from the FIFO memory of the data bus, and are latched below and in the latch R by the read signal RD3.

On these latches L, 8 latched during L
The bit data is simultaneously converted into 16-bit L-channel parallel data from OUT1 and input to the parallel-serial conversion circuit 12L, where it is converted to 16-bit L-channel serial data and output from OUT1 to the OR circuit 16. Is done.

In the next cycle, in the latch R, the 8-bit data latched below R is simultaneously converted into 16-bit parallel data of the R channel and input from OUT2 to the parallel-serial conversion circuit 12R. R of the bit
Is converted to serial data of the channel and
6 is output. At this time, the switch (SW4) is switched to the 16-bit on the b side, and 16-bit L and R channel audio serial data is output.

FIG. 9 is a circuit diagram showing a configuration example of the parallel-serial conversion circuit shown in FIG. Clock system is CL
K1 and CLK2, and the clock system CLK1
N0 to IN7 drive clocks and a clock system CL
K2 is a drive clock from IN7 to IN23. OUTPUT2 is a 16-bit output from IN0 to IN15, and OUTPUT1 is a 24-bit output from IN0 to IN23. When the clock systems CLK1 and CLK2 are commonly connected and a bit clock is input, OUTP
16-bit serial data from IN0 to IN15 is obtained from UT2, and 24-bit serial data from IN0 to IN23 is obtained from OUTPUT1. When a bit clock is input only to the clock system CLK2, 16-bit serial data from IN8 to IN23 is obtained in OUTPUT1.

According to the present embodiment, one audio adapter 1 converts audio data on the 16-bit computer data bus 2 into 24-bit audio serial data or 16-bit audio serial data and outputs it. be able to. Other configurations are the same as those of the second embodiment shown in FIG. 2, and have the same effects. Of course, the OR circuits 15 and 16 may be omitted, and 16-bit or 24-bit audio parallel data may be output.

FIG. 10 is a block diagram showing a fourth embodiment of the audio adapter of the present invention. In this example,
The clock supplied to the parallel-to-serial converters 12L and 12R is set to one of the clock systems CLK1 and CLK2 to output 16-bit or 24-bit parallel audio data. That is, the switch (SW1)
To SW4) switch to the terminal a side, the L channel and R
The 24-bit parallel data of the channel is output to the OR circuit 15.
Are input to the D / A conversion circuit 13 sequentially, and the analog audio signals 13L and 13L of the L channel and the R channel are input.
It is output as R. In addition, switches (SW1 to SW
When 4) is switched to the terminal b side, 16-bit parallel data of the L channel and the R channel are sequentially input to the D / A conversion circuit 14 via the OR circuit 16, and the L channel and the R
It is output as analog audio signals 14L and 14R of the channel.

FIG. 11 is a block diagram showing a configuration example of an audio interface system of the AES / EBU standard using the audio adapter shown in FIG. The audio interface system is configured by inserting an audio adapter 1 between a data bus 2 with a 16-bit FIFO memory of a computer and an audio circuit 5.

After converting the 16-bit audio data supplied from the data bus 2 into 24-bit audio serial data 100L and 100R, these are supplied to the D / A conversion circuit 13 via the OR circuit 15 and are converted to L / L. Channel, R channel analog audio signal 13L, 1
The signal is converted to 3R and output to the analog audio circuit 5. Also, after converting the 16-bit audio data into 16-bit audio serial data 200L and 200R, these are supplied to the D / A conversion circuit 14 via the OR circuit 16 to supply the L-channel and R-channel analog audio signals 14L. , 14R, and outputs the result to the analog audio circuit 5. At this time, an operation clock 50 is supplied from the clock generation circuit 4 to the audio adapter 1 and the data bus 2.

According to the present embodiment, 16-bit audio data from the data bus 2 is converted into 24-bit audio parallel data or 16-bit audio parallel data, and then D / A converted to analog audio data. The audio signal can be supplied from the data bus 2 of the computer to an audio device that can be output as a signal and can only input an analog audio signal.

[0040]

As described above in detail, according to the audio adapter of the present invention, the size of one word of digital audio data on a computer bus can be efficiently converted and supplied to audio equipment.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an audio adapter according to the present invention.

FIG. 2 is a diagram showing an S using the audio adapter shown in FIG. 1;
FIG. 2 is a block diagram showing an interface system of the ID standard.

FIG. 3 is a timing chart illustrating an operation of the audio adapter shown in FIG. 1;

FIG. 4 is a block diagram showing a second embodiment of the audio adapter of the present invention.

FIG. 5 is a timing chart for explaining the operation of the audio adapter shown in FIG. 4;

FIG. 6 is a block diagram showing a third embodiment of the audio adapter of the present invention.

FIG. 7 is a diagram illustrating an operation when outputting 24-bit audio data by the audio adapter shown in FIG. 6;

FIG. 8 is a diagram illustrating an operation when 16-bit audio data is output by the audio adapter shown in FIG. 6;

FIG. 9 is a circuit diagram showing a configuration example of a parallel-serial conversion circuit shown in FIG. 6;

FIG. 10 is a block diagram showing a fourth embodiment of the audio adapter of the present invention.

11 is a block diagram showing a configuration example of an audio interface system of the AES / EBU standard using the audio adapter shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Audio adapter 2 Data bus 3 Buffer 4 Clock generation circuit 5 Audio circuit 11 Latch circuit 12L, 12R Parallel-serial conversion circuit 13, 14 D / A conversion circuit 15, 16 OR circuit 111-116 Latch

Claims (5)

[Claims] 1. An audio adapter for converting audio data on a 16-bit data bus with a FIFO memory into 24-bit audio data, comprising: First holding means for calling and holding bit audio data, and second holding means for calling and holding lower 8 bit audio data of the L channel and upper 8 bit audio data of the R channel from the FIFO memory. Third holding means for calling and holding middle 8-bit audio data and lower 8-bit audio data of the R channel from the FIFO memory; and the first holding means and the second holding means. From the upper, middle and lower 8 bits of the L channel First parallel-to-serial conversion means for converting data into audio serial data by simultaneously calling and inputting the data; upper, middle, and lower eight channels of the R channel from the second holding means and the third holding means; A second parallel-to-serial conversion means for converting the audio parallel data into audio serial data by simultaneously calling and inputting the audio parallel data of 1 bit 2. The conversion operation of the first parallel-serial conversion means and the conversion operation of the second parallel-serial conversion means are performed alternately, and output from the first parallel-serial conversion means and the second parallel-serial conversion means is performed. 2. The audio adapter according to claim 1, wherein the L channel and the R channel serial data are output alternately as a series of data. 3. A first D / A conversion circuit for converting L-channel audio serial data output from the first parallel-serial conversion means into an analog signal, and an output from the second parallel-serial conversion means. R
2. The audio adapter according to claim 1, further comprising a second D / A conversion circuit for converting channel audio serial data into an analog signal. 4. An audio adapter for converting audio data on a 16-bit data bus with a FIFO memory to 24-bit or 16-bit audio data, wherein the audio data is the same as the upper 8 bits of audio data of the L channel from the FIFO memory. First holding means for calling and holding audio data of 8 bits, and 8 bits of audio data of lower 8 bits of the L channel and upper 8 bits of audio data of the R channel from the FIFO memory. Holding means for calling and holding, from the FIFO memory, middle 8-bit audio data of the R channel and 8-bit audio data of the same lower order; and the first holding means and the second holding means. From the upper, middle and lower 8 bits of the L channel First parallel-serial conversion means for converting the audio data into audio serial data by simultaneously calling and inputting the audio data, and the upper, middle, and lower R channels from the second holding means and the third holding means. Second parallel-serial conversion means for converting the 8-bit audio data into audio serial data by simultaneously calling and inputting the 8-bit audio data, and the middle 8-bit audio data of the upper 8 bits of the L channel from the FIFO memory Fourth holding means for calling and holding the audio parallel data of the above; and fifth holding means for calling and holding the middle 8-bit audio data and the lower 8-bit audio data of the R channel from the FIFO memory. From the fourth holding means to the top of the L channel. Third parallel-serial conversion means for converting the 8-bit audio parallel data of the middle order into audio serial data by simultaneously calling and inputting the data; and the middle and lower order of the R channel from the fifth holding means. A fourth parallel-serial converting means for converting 8-bit audio parallel data into audio serial data by simultaneously calling and inputting the 8-bit audio parallel data. To obtain 24-bit audio serial data, In order to operate the third holding means and the first and second parallel-serial conversion means and obtain 16-bit audio serial data, the fourth and fifth holding means and the third and fourth And the first and third parallel converting means are operated as one parameter. An audio adapter characterized in that it is shared by a rel conversion unit and that the second and fourth parallel-serial conversion units are shared by a single parallel conversion unit. 5. The dual-purpose parallel-to-serial conversion means includes a first clock system for driving a circuit element for converting 8-bit parallel data, and a second clock for driving a circuit element for converting 16-bit parallel data. 5. The audio adapter according to claim 4, wherein an output unit for extracting the serial data to the outside is set separately to the 16th bit and the 24th bit of the serial data.