JP2000068506A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a state wherein impurities thrust through a gate electrode to a gate insulating film even if the gate electrode is made a thin film. SOLUTION: On a p-type semiconductor region 102 and an n-type semiconductor region 103 formed on a semiconductor substrate 100, an n-type polycrystalline silicon film 107 and a p-type polycrystalline silicon film 109 are respectively formed. Thereafter, dry etching is performed for the n-type polycrystalline silicon film 107 and the p-type polycrystalline filicon film 109. Thus, a thin- filmed n-type polycristalline silicon film 107A and a p-type polycrystalline silicon film 109A are formed. On the n-type polycrystalline silicon thin film 107A and p-type polycrystalline film 109A, a titanium nitride film 110, a tungsten film 111, and a silicon nitride film 112 are deposited. Thereafter, the n-type gate electrode comprising the thinned n-type polycrystalline silicon film 107A, the titanium nitride film 110 and the tungsten film 111 and the p-type gate electrode comprising the p-type thin polycrystalline 109A, the titanium nitride film 110, and the tungsten film 111 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a gate electrode with a small thickness and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the recent miniaturization of semiconductor integrated circuit devices, in semiconductor integrated circuit devices having MOS transistors, the distance between adjacent MOS transistors has been reduced. MO
It is required that the minimum value of the pitch between the S transistors be reduced to 0.35 μm and the minimum value of the space between the MOS transistors be reduced to about 0.22 μm.

In a semiconductor device in which the distance between MOS transistors is reduced as described above, adjacent MOS transistors
Since the aspect ratios of the insulating film buried between the gate electrodes of the transistors and the contact holes formed in the insulating film are increased, the step of depositing the insulating film and the step of filling the contact holes become difficult. For this reason,
Since the miniaturization of the semiconductor integrated circuit device is restricted, in order to realize further miniaturization of the semiconductor integrated circuit device, the thickness of the gate electrode is reduced and the aspect ratio of the insulating film and the contact hole is reduced. It is desired.

In order to realize the miniaturization, high integration and low voltage of a semiconductor device having a MOS transistor, an n-type gate electrode made of an n-type polycrystalline silicon film and a p-type polycrystalline silicon There is a need for a MOS transistor having a dual gate electrode having a p-type gate electrode made of a film. As described above, in order to form a dual gate electrode composed of polycrystalline silicon films of different conductive types, impurities having different conductive types are ion-implanted into the polycrystalline silicon film, and the polycrystalline silicon films having different conductive types are ion-implanted. Is required.

[0005] Further, from the demand for lowering the resistance of the gate electrode,
The gate electrode is often formed of a laminated film of a low-resistance metal silicide layer and a polycrystalline silicon film or a laminated film of a low-resistance refractory metal film and a polycrystalline silicon film. To realize a thinner gate electrode made of such a stacked film without increasing the resistance value, it is necessary to reduce the thickness of the polycrystalline silicon film having a relatively large resistance value.

In a gate electrode comprising a laminated film of a refractory metal film and a polycrystalline silicon film, diffusion of impurities in the polycrystalline silicon film into the refractory metal film or suppression of the refractory metal film and the polycrystalline silicon film are performed. For the purpose of improving the adhesion to the silicon film and the like, a three-layer structure of a refractory metal film / barrier metal film / polycrystalline silicon film is used. As the barrier metal film, for example, a titanium nitride film formed by a sputtering method or A tungsten nitride film is used.

Further, for process reasons, it is desired to form the gate electrode and the load element of the MOS transistor formed on the semiconductor substrate in the same step.

Hereinafter, as a first conventional example, a method of manufacturing a semiconductor device having a dual gate electrode will be described with reference to FIG.
This will be described with reference to (a) to (c) and FIGS. 14 (a) to (c).

First, as shown in FIG. 13A, after an element isolation insulating film 11 is formed on the surface of a semiconductor substrate 10,
An n-channel MOS transistor formation region (the left region in FIGS. 13 and 14) of the semiconductor substrate 10 has a p.
In addition to forming the type semiconductor region 12, a p-channel MOS transistor forming region in the semiconductor substrate 10 (FIG. 13)
And an n-type semiconductor region 1 in the right region of FIG.
Form 3 Then, after a silicon oxide film 14 serving as a gate insulating film is formed on the p-type semiconductor region 12 and the n-type semiconductor region 13, a 250 nm film serving as a gate electrode is formed over the entire surface of the silicon oxide film 14. A thick non-doped polycrystalline silicon film 15 is deposited by a CVD method.

Next, as shown in FIG. 13B, after forming a first resist pattern 16 in a p-channel MOS transistor formation region on a non-doped polycrystalline silicon film 15, the first resist is formed. Using the pattern 16 as a mask, for example, phosphorus as an n-type impurity is 20 keV
Ions are implanted at an implantation energy of 4 × 10 ¹⁵ / cm ² and an n-type polycrystalline silicon film 17 is formed.

Next, as shown in FIG. 13C, after a second resist pattern 18 is formed in the n-channel MOS transistor formation region on the non-doped polysilicon film 15, the second resist pattern 18 is formed. Using the pattern 18 as a mask, boron as a p-type impurity is, for example, 20 ke.
Ions are implanted at an implantation energy of V and a dose of 4 × 10 ¹⁵ / cm ² to form a p-type polycrystalline silicon film 19.

Next, as shown in FIG. 14A, an n-type polycrystalline silicon film 17 and a p-type polycrystalline silicon film 19 are formed.
A titanium nitride film 20 having a thickness of 20 nm serving as a barrier metal film, a tungsten film 21 having a thickness of 80 nm serving as a high melting point metal film, and a 50 nm film thickness serving as a protective film. A silicon nitride film 22 is sequentially deposited.

Next, as shown in FIG. 14B, a third gate electrode forming region is formed on the silicon nitride film 22.
After the resist pattern 23 is formed, etching is performed using the third resist pattern 23 as a mask,
In an n-channel MOS transistor formation region, an n-type gate electrode 24 composed of an n-type polycrystalline silicon film 17, a titanium nitride film 20, and a tungsten film 21 and a gate insulating film 14A composed of a silicon oxide film 14 are formed. A p-type polycrystalline silicon film 19, a p-type gate electrode 25 composed of a titanium nitride film 20 and a tungsten film 21, and a gate insulating film 14A composed of a silicon oxide film 14 are formed in the channel MOS transistor formation region.

Next, as shown in FIG. 14C, an n-type impurity is ion-implanted into the p-type semiconductor region 12 using the n-type gate electrode 24 as a mask to form an n-type low-concentration impurity region 26. At the same time, a p-type impurity is ion-implanted into the n-type semiconductor region 13 using the p-type gate electrode 25 as a mask to form a p-type low-concentration impurity region 27.
Thereafter, the n-type gate electrode 24 and the p-type gate electrode 2
After the sidewalls 28 are formed on the p-type semiconductor region 12, an n-type impurity is ion-implanted into the p-type semiconductor region 12 using the n-type gate electrode 24 and the sidewalls 28 as a mask to form an n-type high-concentration impurity region 29. At the same time, a p-type impurity is ion-implanted into the n-type
A high concentration impurity region 30 of a mold is formed.

Next, although not shown, if an interlayer insulating film, a contact, a metal wiring, and the like are formed by a known method, a semiconductor device having a dual gate electrode can be obtained.

Hereinafter, as a second conventional example, a semiconductor device having a gate electrode having a three-layer structure of a refractory metal film / barrier metal film / polycrystalline silicon film and a method of manufacturing the same will be described.
This will be described with reference to FIGS. FIGS. 15A to 15C show cross-sectional structures in the gate width direction.

First, as shown in FIG. 15A, after an element isolation insulating film 41 is formed on the surface of a semiconductor substrate 40,
An n-type semiconductor region is formed in a p-channel MOS transistor formation region of a semiconductor substrate. Then n
After a silicon oxide film 43 serving as a gate insulating film is formed on the type semiconductor region 42, a boron-doped polycrystalline silicon film having a thickness of 80 nm serving as a part of a gate electrode is formed over the entire surface of the silicon oxide film 43. A crystalline silicon film 44 is deposited by a CVD method.

Next, as shown in FIG. 15B, a titanium nitride film 45 having a thickness of 40 nm serving as a barrier metal film and a refractory metal are formed over the entire surface of the boron-doped polycrystalline silicon film 44. A tungsten film 46 having a thickness of 80 nm is sequentially deposited as a film.

Next, as shown in FIG. 15C, the tungsten film 46, the titanium nitride film 45, the boron-doped polycrystalline silicon film 44 and the silicon oxide film 43 are selectively etched to form a p-channel. In the MOS transistor formation region, a p-type gate electrode 47 composed of a polycrystalline silicon film 44, a titanium nitride film 45 and a tungsten film 46, and a gate insulating film 4 composed of a silicon oxide film 43
Form 3A.

Hereinafter, as a third conventional example, a semiconductor device having a gate electrode of a MOS transistor and a load element on a semiconductor substrate and a method of manufacturing the same will be described with reference to FIGS.
This will be described with reference to (d) and FIGS. 17 (a) to (c).

As shown in FIG. 16A, the semiconductor substrate 5
After separating the MOS transistors from each other and forming an element isolation insulating film 51 serving as a load element formation region on the surface of the semiconductor substrate 50, an n-type semiconductor region 52 is formed in the p-channel MOS transistor formation region of the semiconductor substrate 50. Then, after a silicon oxide film 53 serving as a gate insulating film is formed on the n-type semiconductor region 52, a non-doped polycrystalline silicon film 54 is formed on the entire surface of the semiconductor substrate 50 by CV.
It is deposited by the D method.

Next, as shown in FIG. 16 (b), for example, boron is ion-implanted as a p-type impurity to form a p-type polycrystalline silicon film 55, and annealing is performed to form a p-type polycrystalline silicon film 55. The impurities implanted in the polycrystalline silicon film 55 are diffused.

Next, as shown in FIG. 16C, after a silicon nitride film 56 is deposited over the entire surface of the p-type polycrystalline silicon film 55, a load element is formed on the silicon nitride film 56. A first resist pattern 57 is formed in the region.

Next, as shown in FIG. 16D, the silicon nitride film 5 is formed using the first resist pattern 57 as a mask.
6 is subjected to dry etching to pattern the silicon nitride film 56 into the shape of a load element.

Next, as shown in FIG. 17A, a titanium nitride film 58 serving as a barrier metal film and a tungsten film serving as a high melting point metal film are formed over the entire surface of the p-type polycrystalline silicon film 55. After sequentially depositing 59, a second resist pattern 60 is formed on the tungsten film 59.

Next, as shown in FIG. 17B, using the second resist pattern 60 as a mask, the tungsten film 59, the titanium nitride film 58 and the p-type polycrystalline silicon film 5 are used.
5 is dry-etched to obtain a p-channel M
In the OS transistor formation region, the tungsten film 5
9, titanium nitride film 58 and p-type polycrystalline silicon film 55
A p-type gate electrode 61 made of
And a p-type polycrystalline silicon film 55 in the load element formation region.
And a pair of terminal electrodes 63 made of a tungsten film 59 are formed.

Next, as shown in FIG. 17C, a p-type impurity is ion-implanted into the n-type semiconductor region 52 using the p-type gate electrode 61 as a mask to form a p-type low-concentration impurity region 63. To form After that, the p-type gate electrode 61,
After a sidewall 64 is formed on the load element 62 and the pair of terminal electrodes 63, a p-type impurity is ion-implanted into the n-type semiconductor region 52 using the p-type gate electrode 61 and the sidewall 64 as a mask. Of the high concentration impurity region 65 is formed.

[0028]

By the way, in the semiconductor device having the dual gate electrode shown as the first conventional example, in order to form the dual gate electrode made of the polycrystalline silicon film, it is necessary to form the polycrystalline silicon film. Implantation of impurity ions is indispensable, but when the polycrystalline silicon film is thinned, the impurities implanted in the ion implantation step penetrate through the gate electrode and reach the gate insulating film, so that the reliability of the gate insulating film is reduced. A problem of deterioration occurs.

FIG. 18 shows an impurity profile when boron is ion-implanted at a dose of 2 × 10 ¹⁵ / cm ² into the polycrystalline silicon film serving as a gate electrode. As can be seen from FIG. When boron is ion-implanted at an implantation energy of 5 keV, the boron concentration becomes 1 × 1
The region of 0 ¹⁶ / cm ³ extends from the surface to a region exceeding 100 nm. Therefore, if the concentration of boron is 1
In order to keep the region of × 10 ¹⁶ / cm ³ at a portion shallower than 100 nm from the surface, it is necessary to implant boron with a low implantation energy of about 3 keV or less.

However, low implantation energy of 3 keV or less
Energy and high dose (2 × 10 ^Fifteen/ Cm^TwoLess than
Above), ion implantation of impurities into polycrystalline silicon film
Doing so is not practical in terms of throughput.

The above problem becomes more prominent as the thickness of the polycrystalline silicon film forming the gate electrode is reduced.

Therefore, it is desired to prevent a situation in which impurities penetrate the gate electrode and reach the gate insulating film even when the gate electrode is thinned.

The refractory metal film shown as the second conventional example /
In a semiconductor device having a gate electrode having a three-layer structure of a barrier metal film / polycrystalline silicon film, the following problems occur.

FIGS. 19 (a) and (b) correspond to FIG.
3C, the film thickness T of the polycrystalline silicon film 44 in the gate electrode 47 having a laminated structure of the polycrystalline silicon film 44, the titanium nitride film 45, and the tungsten film 46, and the region under the gate electrode 47. 19A shows the relationship with the height H of the substrate step formed by the element isolation insulating film 41 formed in FIG. 19A. FIG. 19A shows the case where T≫H, and FIG. ≒ H is shown.

As shown in FIG. 19A, when the thickness T of the polycrystalline silicon film 44 is sufficiently larger than the height H of the substrate step, the step formed on the polycrystalline silicon film 44 is formed. If the thickness of the polycrystalline silicon film 44 is substantially equal to the height H of the substrate step portion, although the gradient of the portion (the ratio of the height of the step portion to the bottom side) is small, the polycrystalline silicon film 44 is formed. The gradient of the step portion becomes large. Polycrystalline silicon film 4
When the gradient of the step portion of No. 4 increases, the gradient of the step portion of the titanium nitride film 45 necessarily increases.

Since the titanium nitride film 45 has a higher resistance value than the tungsten film 46, the titanium nitride film 4
5 needs to be thinned.

However, the titanium nitride film 45 has poor step coverage and is easily cracked. For this reason, as shown in FIG. 19B, when the gradient of the step portion in the polycrystalline silicon film 44 and thus the titanium nitride film 45 is increased, the titanium nitride film 45 is cracked and the titanium nitride film 45 is disconnected. This causes a problem.

Therefore, it is desired that the titanium nitride film 45 does not crack even if the thickness of the polycrystalline silicon film 44 forming the gate electrode 47 is reduced.

In the semiconductor device in which the gate electrode and the load element of the MOS transistor described as the third conventional example are formed in the same step, the contact resistance between the load element 62 and the terminal electrode 63 is large and the p-type Gate electrode 6
When the p-type polycrystalline silicon film 55 constituting 1 is thinned, a problem occurs that the resistance value of the load element 62 increases.

In view of the above, a first object of the present invention is to prevent a situation in which impurities penetrate the gate electrode and reach the gate insulating film even when the gate electrode is thinned,
The second object is to prevent disconnection of the barrier metal film even if the gate electrode composed of the refractory metal film / barrier metal film / polycrystalline silicon film and extending over the step portion of the substrate is thinned.
The third object is to reduce the contact resistance between the load element and the terminal electrode.

[0041]

In order to achieve the second object, a first semiconductor device according to the present invention comprises: a semiconductor substrate having a substrate step portion adjacent to a MOS transistor formation region; An impurity-containing silicon film formed over the MOS transistor formation region and the substrate step portion on the substrate and having a step portion on the substrate step portion, a barrier metal film formed on the impurity-containing silicon film,
And a gate electrode made of a high melting point metal film formed on the barrier metal film, and the ratio of the height to the bottom of the step portion of the impurity-containing silicon film is 0.6 or less. .

According to the first semiconductor device, the height ratio of the stepped portion of the impurity-containing silicon film to the bottom at the step is 0.1 mm.
Since it is 6 or less, disconnection of the barrier metal film can be suppressed even if both the thickness of the impurity-containing silicon film and the thickness of the barrier metal film are small.

In order to achieve the third object, a second semiconductor device according to the present invention comprises an element isolation insulating film formed on a surface portion of a semiconductor substrate and an element isolation insulating film provided on the element isolation insulating film. A linear resistance portion formed of a portion having a relatively large thickness in the conductive film, and a pair of electrode connections formed of portions having a relatively small thickness formed on both end sides of the resistance portion in the conductive film. And a pair of terminal electrodes made of a refractory metal film formed so as to extend over each end of the resistor portion and each of the pair of electrode connection portions.

According to the second semiconductor device, the terminal electrode made of the refractory metal film is formed so as to straddle the end of the resistance portion of the load element having a large thickness and the electrode connection portion of the load element having a small thickness. Therefore, the terminal electrode is in contact with the upper surface of the end of the resistor, the wall surface between the end of the resistor and the electrode connector, and the upper surface of the electrode connector, respectively. And the contact area with the metal becomes large.

In order to achieve the first object, a first method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate; A silicon film deposition step of depositing a silicon film on the silicon film, an ion implantation step of forming an impurity-containing silicon film by ion-implanting an impurity into the silicon film, and thinning by removing a surface portion of the impurity-containing silicon film. The method includes a thinning step of forming an impurity-containing silicon film, and a patterning step of forming a gate electrode by patterning the thinned impurity-containing silicon film into a predetermined shape.

According to the first method of manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film deposited on a gate insulating film, and then the surface of the impurity-containing silicon film is removed. Since the gate electrode is formed by patterning the thinned impurity-containing silicon film by removing and thinning, impurities can be ion-implanted into a silicon film having a large thickness, so that the implantation energy for ion implantation is large. However, the impurity does not penetrate into the gate insulating film, and the thickness of the gate electrode can be reduced because the gate electrode is made of a thinned impurity-containing silicon film.

In order to achieve the first object, a second method for manufacturing a semiconductor device according to the present invention comprises the steps of: forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate; A silicon film deposition step of depositing a silicon film on the silicon film, an ion implantation step of forming an impurity-containing silicon film by ion-implanting an impurity into the silicon film, and thinning by removing a surface portion of the impurity-containing silicon film. A thinning step of forming an impurity-containing silicon film, a patterning step of forming a gate electrode by patterning the thinned impurity-containing silicon film into a predetermined shape, and forming a refractory metal silicide layer on the surface of the gate electrode Forming a silicide layer.

According to the second method for manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film deposited on a gate insulating film, and then the surface of the impurity-containing silicon film is removed. Since the gate electrode is formed by patterning the thinned impurity-containing silicon film by removing and thinning, impurities can be ion-implanted into a silicon film having a large thickness, so that the implantation energy for ion implantation is large. However, the impurity does not penetrate into the gate insulating film, and the thickness of the gate electrode can be reduced because the gate electrode is made of a thinned impurity-containing silicon film.

Further, since a silicide layer forming step of forming a high melting point metal silicide layer on the surface of the gate electrode is provided, a gate made of a laminated film of a low melting point high melting point metal silicide layer and a polycrystalline silicon film is provided. Electrodes can be formed.

In order to achieve the above first and second objects, a third method for manufacturing a semiconductor device according to the present invention comprises:
An insulating film forming step of forming a gate insulating film in a MOS transistor forming region of a semiconductor substrate having a substrate step in a portion adjacent to the S transistor forming region; and depositing a silicon film on the MOS transistor forming region and the substrate step A silicon film deposition step, an ion implantation step of ion-implanting an impurity into the silicon film to form an impurity-containing silicon film, and forming a thinned impurity-containing silicon film by removing a surface portion of the impurity-containing silicon film A thinning step, a metal film depositing step of sequentially depositing a barrier metal film and a high melting point metal film on the thinned impurity containing silicon film, and a high melting point metal film, a barrier metal film and the thinned impurity containing silicon film. By patterning the film into a predetermined shape, the film is formed over the MOS transistor formation region and the substrate step portion. And a patterning step of forming a building gate electrode.

According to the third method of manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film deposited on a gate insulating film, and then the surface of the impurity-containing silicon film is removed. To remove and thin
Since impurities can be ion-implanted into a silicon film having a large thickness, even if the implantation energy for ion implantation is large, the impurities do not penetrate into the gate insulating film.

Further, after a barrier metal film and a high melting point metal film are deposited on the impurity-containing silicon film formed on the MOS transistor formation region and the substrate step portion of the semiconductor substrate and reduced in thickness, the thickness is reduced. Since the gate electrode is formed by patterning the laminated film including the impurity-containing silicon film, the barrier metal film, and the high-melting-point metal film, the ratio of the height of the impurity-containing silicon film to the bottom of the step portion is reduced. Even if the thickness of the barrier metal film formed on the step portion of the film is small, disconnection of the barrier metal film can be suppressed.

To achieve the first object, a fourth method of manufacturing a semiconductor device according to the present invention comprises forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate, and then forming the gate insulating film on the gate insulating film. A silicon film deposition step of depositing a silicon film on the silicon film, an ion implantation step of forming an impurity-containing silicon film by ion-implanting an impurity into the silicon film, and thinning by removing a surface portion of the impurity-containing silicon film. A thinning step of forming an impurity-containing silicon film, a metal film depositing step of depositing a refractory metal film on the thinned impurity-containing silicon film, and an element isolation groove in an element isolation insulating film formation region on the semiconductor substrate. After forming
An element isolation insulating film forming step of forming an element isolation insulating film by embedding an insulating film in the element isolation groove; and forming a gate electrode by patterning a high melting point metal and a thinned impurity-containing silicon film into a predetermined shape. Patterning step.

According to the fourth method for manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film deposited on a gate insulating film, and then the surface of the impurity-containing silicon film is removed. Since the gate electrode is formed by patterning the thinned impurity-containing silicon film by removing and thinning, impurities can be ion-implanted into a silicon film having a large thickness, so that the implantation energy for ion implantation is large. However, the impurity does not penetrate into the gate insulating film, and the thickness of the gate electrode can be reduced because the gate electrode is made of a thinned impurity-containing silicon film.

Further, prior to the step of forming an element isolation insulating film by embedding an insulating film in an element isolation groove formed on a semiconductor substrate, a thinning step of thinning the impurity-containing silicon film is performed. It is possible to reduce the thickness of a flat impurity-containing silicon film formed on a simple semiconductor substrate.

In order to achieve the first and third objects, a fifth method of manufacturing a semiconductor device according to the present invention comprises:
An insulating film forming step of forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate having an S transistor forming region and a load element forming region, and a silicon film in a load element forming region on the gate insulating film and the semiconductor substrate; A silicon film deposition step of depositing, an ion implantation step of forming an impurity-containing silicon film by ion-implanting impurities into the silicon film, and a surface portion of the impurity-containing silicon film leaving a resistance portion forming region of a load element forming region. A thinning step of forming an impurity-containing silicon film thinned by removing, a metal film depositing step of depositing a high-melting-point metal film on the thinned impurity-containing silicon film, a high-melting-point metal film and a thin film The refractory metal film and the thinned impurity are patterned by patterning the Forming a gate electrode made of a silicon-containing silicon film, and forming a linear resistance portion composed of a non-thinned portion of the impurity-containing silicon film, and a thinned impurity-containing silicon film formed on both ends of the resistance portion, respectively; A patterning step of forming a load element composed of a pair of electrode connections, and forming a pair of terminal electrodes made of a refractory metal film straddling over each end of the resistor and each of the pair of electrode connections; and It has.

According to the fifth method of manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film deposited on a gate insulating film, and then the surface portion of the impurity-containing silicon film is removed. To remove and thin
Since impurities can be ion-implanted into a silicon film having a large thickness, even if the implantation energy for ion implantation is large, the impurities do not penetrate into the gate insulating film.

Further, the thinned impurity-containing silicon film and the high-melting-point metal film are patterned into a predetermined shape while leaving the resistance portion-forming region of the load element formation region, and the high-melting-point metal film and the thinned impurity-containing silicon film are formed. Load element having a gate electrode made of a film, a linear resistance portion made of a non-thinned portion of an impurity-containing silicon film, and an electrode connection portion made of a thinned impurity-containing silicon film, and a resistance portion of the load element In order to form a terminal electrode extending over the end portion and the electrode connection portion, a gate electrode composed of a refractory metal film and a thinned impurity-containing silicon film, a load element composed of a thinned impurity-containing silicon film, and A terminal electrode made of a melting point metal film can be formed at the same time, and the end portion of the resistor portion having a large thickness and the electrode connecting portion having a small thickness are straddled. , It is possible to reliably form the terminal electrode contact area is large and the load device.

In the first to fifth methods of manufacturing a semiconductor device, the MOS transistor formation region is an n-channel MOS
The ion implantation step includes a transistor formation region and a p-channel MOS transistor formation region. The ion implantation step includes a step of ion-implanting an n-type impurity into a gate electrode formation region of the n-channel MOS transistor formation region in the silicon film; Ion-implanting a p-type impurity into the gate electrode formation region of the MOS transistor formation region.

In the first to fifth methods of manufacturing a semiconductor device, the silicon film deposition step includes a step of depositing a silicon film having a thickness of 200 nm or more, and the thinning step includes: It is preferable to include a step of removing the surface portion of the impurity-containing silicon film so that the thickness of the silicon film becomes 100 nm or less.

[0061]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a semiconductor device and a method for manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (c) and 2 (a) to 2 (a). This will be described with reference to (c) and FIGS. 3 (a) and 3 (b).

First, as shown in FIG. 1A, after an element isolation insulating film 101 is formed on the surface of a semiconductor substrate 100, an n-channel MOS transistor forming region (left side in FIGS. 1 to 3) on the semiconductor substrate 100 is formed. Area)
Forming the semiconductor region 102 and the semiconductor substrate 10
In the p-channel MOS transistor formation region at 0 (the right region in FIGS. 1 to 3), an n-type semiconductor region 103 is formed.
To form Thereafter, a silicon oxide film 104 serving as a gate insulating film is formed on the p-type semiconductor region 102 and the n-type semiconductor region 103, and then a non-doped type having a thickness of 200 nm is entirely formed on the silicon oxide film 104. Is deposited by a CVD method.

Next, as shown in FIG. 1B, after a first resist pattern 106 is formed in a p-channel MOS transistor forming region on the non-doped polycrystalline silicon film 105, the first resist is formed. Pattern 106
Is used as a mask and, for example, phosphorus is
Ion implantation is performed at an implantation energy of eV and a dose of 4 × 10 ¹⁵ / cm ² to form an n-type polycrystalline silicon film 107 which becomes a part of the gate electrode.

Next, as shown in FIG. 1C, a second resist pattern 108 is formed in the n-channel MOS transistor forming region on the non-doped polycrystalline silicon film 105, and then the second resist pattern 108 is formed. Pattern 108
Is used as a mask, and boron as a p-type impurity is
Ion implantation is performed at an implantation energy of keV and a dose of 4 × 10 ¹⁵ / cm ² to form a p-type polycrystalline silicon film 109 which is to be a part of the gate electrode.

Next, as shown in FIG. 2A, after removing the second resist pattern 108, annealing is performed at a temperature of 800 ° C. for about 30 minutes, for example.
The impurities implanted in the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film 109 are diffused.

Next, as shown in FIG. 2B, an n-type polycrystalline silicon film 107 and a p-type polycrystalline silicon film 10 are formed.
9 is subjected to dry etching using plasma composed of, for example, chlorine gas, bromine gas or oxygen gas, thereby removing the surface portions of the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film 109 by 100 nm. Then, a thinned n-type polycrystalline silicon film 107A having a thickness of 100 nm and a p-type polycrystalline silicon film 10 are formed.
9A is formed.

Next, as shown in FIG. 2C, a barrier metal film is formed over the entire surface of the thinned n-type polycrystalline silicon film 107A and p-type polycrystalline silicon film 109A. A titanium nitride film 110 having a thickness of 20 nm,
A tungsten film 111 having a thickness of 80 nm as a refractory metal film and a silicon nitride film 112 having a thickness of 50 nm serving as a protective film are sequentially deposited.

Next, as shown in FIG. 3A, a third gate electrode forming region is formed on the silicon nitride film 112.
After the formation of the resist pattern 113, dry etching is performed using the third resist pattern 113 as a mask to form an n-channel MOS transistor formation region.
A thinned n-type polycrystalline silicon film 107A, an n-type gate electrode 114 composed of a titanium nitride film 110 and a tungsten film 111, and a gate insulating film 104A composed of a silicon oxide film 104 are formed.
In the OS transistor formation region, a thinned p-type polycrystalline silicon film 109A, a p-type gate electrode 115 made of a titanium nitride film 110 and a tungsten film 111, and a gate insulating film 104A made of a silicon oxide film 104 are formed.

Next, as shown in FIG. 3B, an n-type impurity is ion-implanted into the p-type semiconductor region 102 using the n-type gate electrode 114 as a mask to form an n-type low-concentration impurity region 116. And an n-type semiconductor region 103
P-type impurity is ion-implanted using p-type gate electrode 115 as a mask to
To form Then, after forming a sidewall 118 on the n-type gate electrode 114 and the p-type gate electrode 115, the n-type gate electrode 1 is formed on the p-type semiconductor region 102.
An n-type impurity is ion-implanted using the mask 14 and the side wall 118 as a mask to form an n-type high-concentration impurity region 119, and the p-type gate electrode 115 and the side wall 118 are masked with respect to the n-type semiconductor region 103. Then, a p-type impurity is ion-implanted to form a p-type high-concentration impurity region 120.

Next, although not shown, if an interlayer insulating film, a contact, a metal wiring and the like are formed by a known method, a tungsten film 111 having a thickness of 80 nm,
A semiconductor device having a 200 nm-thick dual gate electrode made of a 0 nm titanium nitride film 110 and a 100 nm-thick n-type polycrystalline silicon film 107A (p-type polycrystalline silicon film 109A) is obtained. .

According to the first embodiment, an impurity is ion-implanted into a non-doped polycrystalline silicon film 105 having a large thickness, and an n-type polycrystalline silicon film 107 serving as a gate electrode and a p-type Since the polycrystalline silicon film 109 is formed, even if the impurity ions are implanted with relatively high implantation energy, the impurity does not penetrate into the silicon oxide film 104 serving as the gate insulating film.

When a dual gate electrode having a thickness of, for example, 200 nm is formed by the method shown in the first conventional example, it is necessary to implant boron ions into a non-doped polycrystalline silicon film having a thickness of 100 nm. Therefore, in order to prevent boron from penetrating into a silicon oxide film serving as a gate insulating film, ion implantation must be performed at an implantation energy of 3 keV or less. For this reason, there has been a problem that the throughput is reduced due to the reduction of the ion current density and the ion implantation efficiency.

On the other hand, according to the first embodiment,
Even if boron is ion-implanted into the non-doped polycrystalline silicon film 105 having a thickness of 200 nm with an implantation energy of 20 keV, the boron silicon oxide film 104
No penetration into the silicon oxide film 104 occurs.
The reliability of the gate insulating film 104A made of is not impaired.

The n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film
9 is thinned, and the n-type polycrystalline silicon film 1 is thinned.
07A and p-type polycrystalline silicon film 109A.
Since the gate electrode 114 of the p-type and the gate electrode 115 of the p-type are formed, the thickness of the dual gate electrode can be reliably reduced.

In the first embodiment, 200n
n-type polycrystalline silicon film 107 having a thickness of m and p
Although the surface portion of the polycrystalline silicon film 109 is removed by a thickness of 100 nm by performing dry etching, a thinner dual gate electrode can be obtained by increasing the thickness of the surface portion to be removed. it can.

In the dry etching process for the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film 109, if the ion / radical ratio in the plasma is made larger than 0.1, for example, the n-type polycrystalline silicon film Since the difference between the etching rate for the silicon film 107 and the etching rate for the p-type polycrystalline silicon film 109 is reduced, the thinned n-type polycrystalline silicon film 107 is formed.
A film thickness of A and thinned p-type polycrystalline silicon film 109
The difference from the film thickness of A can be reduced.

In the first embodiment, the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon
09 was subjected to dry etching to remove the surface portion. Alternatively, for example, wet etching using hydrofluoric nitric acid, chemical mechanical polishing (CMP), or sputtering using argon ions, for example, was used.
The surface portions of the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film 109 may be removed.

In the step of thinning the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon film 109, the n-type polycrystalline silicon film 107 and the p-type polycrystalline silicon When the film thickness of the film 109 is measured by, for example, an optical method, and the etching time is determined based on the measured film thickness value and the etching rate,
Variations in gate electrode thickness due to variations in thickness of the thinned n-type polycrystalline silicon film 107A and p-type polycrystalline silicon film 109A can be suppressed.

(First Modification of First Embodiment) Hereinafter,
A method for manufacturing a semiconductor device according to a first modification of the first embodiment of the present invention will be described with reference to FIGS.

As in the first embodiment, as shown in FIG. 1A, a non-doped polycrystalline silicon film 105 having a thickness of 200 nm serving as a gate electrode is deposited. Thereafter, as shown in FIG. 4A, BSG (Boron-doped Silicate Glas) containing about 6% boron over the entire surface of the non-doped polycrystalline silicon film 105.
s) After depositing the film 130, a first resist pattern 106 is formed in the p-channel MOS transistor formation region on the BPG film 130, and the BPG film 130 is etched using the first resist pattern 106 as a mask. Then, the BSG film 130 is left only in the p-channel MOS transistor formation region.

Next, as shown in FIG. 4B, the semiconductor substrate 100 is annealed at a temperature of, for example, 800 ° C. for about 30 minutes to remove boron contained in the BPG film 130 into a non-doped type. Is diffused into the polycrystalline silicon film 105 to form a p-type polycrystalline silicon film 109 which becomes a part of the gate electrode.

Next, as shown in FIG. 4C, the non-doped polycrystalline silicon film 105 is
Is used as a mask and, for example, phosphorus is
Ion implantation is performed at an implantation energy of eV and a dose of 4 × 10 ¹⁵ / cm ² to form an n-type polycrystalline silicon film 107 which becomes a part of the gate electrode.

Next, as in the first embodiment, FIG.
By performing the steps shown in FIGS. 3B and 3C and FIGS. 3A and 3B, a semiconductor device having a structure similar to that of the first embodiment can be obtained.

In the first modification, the p-type polycrystalline silicon film 109 is formed by the thermal diffusion of boron. Instead, the n-type polycrystalline silicon film 107 is formed by the thermal diffusion of phosphorus. It may be formed.

In the first embodiment and the first modification, the refractory metal film constituting the gate electrode is
The tungsten film 111 was used, but instead of this, Mo
A film, a Co film, a Ti film or a silicide film of Mo, Co or Ti can be used, and a tungsten nitride film or the like can be used as the barrier metal film instead of the titanium nitride film 110. When a barrier metal film is not required, a two-layer structure of a high melting point metal film / polycrystalline silicon film may be used.

(Second Modification of First Embodiment) Hereinafter,
A method for manufacturing a semiconductor device according to a second modification of the first embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 2B, the n-type polycrystalline silicon film 107A and the p-type polycrystalline silicon film 1 are thinned in the same manner as in the first embodiment or the first modification.
After the formation of the resist pattern 09A, a third resist pattern 113 is formed on the n-type polycrystalline silicon film 107A and the p-type polycrystalline silicon film 109A as shown in FIG. Thereafter, dry etching is performed using third resist pattern 113 as a mask, and n-type gate electrode 141 and silicon oxide film 104 made of thinned n-type polycrystalline silicon film 107A are formed in the n-channel MOS transistor formation region. Of the p-type gate electrode 142 and the silicon oxide film 104 made of the thinned p-type polycrystalline silicon film 109A in the p-channel MOS transistor formation region.
The gate insulating film 104A made of is formed.

Next, as shown in FIG. 5B, an n-type impurity is ion-implanted into the p-type semiconductor region 102 using the n-type gate electrode 141 as a mask. And an n-type semiconductor region 103
P-type impurities are ion-implanted using p-type gate electrode 142 as a mask.
To form Then, after forming sidewalls 118 on the n-type gate electrode 141 and the p-type gate electrode 142, the n-type gate electrode 1 is formed on the p-type semiconductor region 102.
N-type impurities are ion-implanted using the mask 41 and the sidewalls 118 as a mask to form an n-type high-concentration impurity region 119, and the p-type gate electrode 142 and the sidewalls 118 are masked with respect to the n-type semiconductor region 103. Then, a p-type impurity is ion-implanted to form a p-type high-concentration impurity region 120.

Next, as shown in FIG. 5C, the n-type gate electrodes 141 and p are formed by a well-known salicide process.
Gate electrode 142, n-type high concentration impurity region 119
After a refractory metal silicide layer 143 made of a cobalt silicide layer or a titanium silicide layer is formed on each surface of the p-type high-concentration impurity region 120, although not shown, the interlayer is formed by a known method. When an insulating film, a contact, a metal wiring, and the like are formed, a semiconductor device having a dual gate electrode composed of a thinned n-type polycrystalline silicon film 107A and a p-type polycrystalline silicon film 109A having a thickness of 100 nm is obtained. .

In the second modification, the wiring resistance of the gate electrode is larger than that of the first embodiment, but the gate electrode can be made thinner.

(Second Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention will be described.
This will be described with reference to FIGS. 6A to 6C and FIGS. 7A and 7B. 6 (a) to 6 (c) and FIG.
(A) and (b) show cross-sectional structures in the gate width direction.

First, as shown in FIG. 6A, an element isolation insulating film 201 is formed on the surface of a semiconductor substrate 200, and an n-type semiconductor region 202 is formed on a p-channel MOS transistor forming region of the semiconductor substrate 200. I do.
Thereafter, a silicon oxide film 203 serving as a gate insulating film is formed on the n-type semiconductor region 202, and a non-doped polycrystalline silicon film 204 having a thickness of 200 nm is entirely formed on the silicon oxide film 203. Is deposited by a CVD method. On the surface of the semiconductor substrate 200, a substrate step is formed by projecting the element isolation insulating film 201 by 100 nm from the surface of the semiconductor substrate 200, so that the element isolation insulating film 201 of the non-doped polycrystalline silicon film 204 is formed. A step is also formed on the end (on the substrate step), and the length x1 of the bottom of the step is 170 nm and the height y1 is 100 nm.

Next, as shown in FIG. 6B, for example, boron is ion-implanted as a p-type impurity at an implantation energy of 20 keV and a dose of 4 × 10 ¹⁵ / cm ² .
After forming the p-type polycrystalline silicon film 205, for example, 8
By performing annealing for about 30 minutes at a temperature of 00 ° C., the impurities implanted in the p-type polycrystalline silicon film 205 are diffused.

Next, as shown in FIG. 6C, anisotropic dry etching is performed on the p-type polycrystalline silicon film 205 using, for example, a plasma of chlorine gas, bromine gas or oxygen gas. 120 nm surface area
Only to remove the thinned p having a thickness of 80 nm.
A type polycrystalline silicon film 205A is formed. Thus, the p-type polycrystalline silicon film 205A having a reduced thickness is formed.
Is the length x1: 170 nm of the bottom of the step and the height y
The film thickness becomes 80 nm while maintaining 1: 100 nm.

Next, as shown in FIG. 7A, a titanium nitride film having a thickness of 20 nm serving as a barrier metal film is formed on the entire surface of the thinned p-type polycrystalline silicon film 205A. 206 and a tungsten film 207 having a thickness of 80 nm as a refractory metal film are sequentially deposited.

Next, a tungsten film 207, a titanium nitride film 206, and a thinned p-type polycrystalline silicon film 205 are formed.
A and the silicon oxide film 203 are selectively etched to form a p-type polycrystalline silicon film 205A, a titanium nitride film 206 and a tungsten film 207 comprising a thinned p-type polysilicon film 205 in the p-channel MOS transistor formation region.
A gate electrode 208 and a gate insulating film 203A made of a silicon oxide film 203 are formed.

According to the second embodiment, the p-type polycrystalline silicon film 205 having a large thickness is subjected to anisotropic dry etching to obtain a thinned p-type polycrystalline silicon film 205A. Therefore, as shown in FIG.
Element isolation insulating film 201 in p-type gate electrode 208
The length x1 of the bottom of the step formed on the substrate (on the substrate step) is 170 nm, and the height y1 of the step is 100 n.
m, the height ratio (gradient) of the step portion of the p-type gate electrode 208 to the bottom of the step portion of the p-type polycrystalline silicon film 205 is 100/170 (≒ 0.5).
9).

By the way, the length of the bottom of the step is x (n
m), the slope at the surface of the polycrystalline silicon film (assuming conformal deposition) having a height of y (nm) and a thickness of t (nm) deposited by the CVD method, (Y / x) can be approximated as {y / (2ty)} ^1/2 . When the polycrystalline silicon film is thinned and the thickness t of the polycrystalline silicon film is smaller than the height y of the step (y>
t) is a gradient (y /
Since x) has a value of 1 or more, disconnection is likely to occur in the barrier metal film formed on the step portion of the polycrystalline silicon film by the sputtering method.

On the other hand, according to the second embodiment,
A thick polycrystalline silicon film (t = 200 nm)
Deposition by VD method, gradient at step (y / x)
Is set to 0.6 or less, the thickness of the polycrystalline silicon film is reduced by anisotropic etching, so that the gradient (y / x) at the step portion is small despite the small thickness of the polycrystalline silicon film. 0.6 or less. For this reason, even if the thickness of the barrier metal film is reduced, disconnection of the barrier metal film can be suppressed, so that the thickness of the barrier metal film can be reduced to about 20 nm or less.

In the second embodiment, the p-type gate electrode 20 is formed in the p-channel MOS transistor formation region.
Although the case of forming the gate electrode 8 has been described, the case where an n-type gate electrode is formed in the n-channel MOS transistor formation region by ion-implanting, for example, phosphorus as an n-type impurity into the non-doped polycrystalline silicon film 204 is also described. The same effect can be obtained.

(Third Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described.
8 (a) to 8 (c), FIGS. 9 (a) to 9 (d) and FIG.
This will be described with reference to (a) to (c).

First, as shown in FIG. 8A, a p-type semiconductor region 301 is formed in an n-channel MOS transistor formation region (region on the left side in FIGS. 8 to 10) of a semiconductor substrate 300, and the semiconductor substrate 300 P-channel MOS transistor formation region in FIG.
An n-type semiconductor region 302 is formed in the region on the right side of FIG. Thereafter, a silicon oxide film 303 serving as a gate insulating film is formed on the p-type semiconductor region 301 and the n-type semiconductor region 302.
Is formed, a non-doped polycrystalline silicon film 304 having a thickness of 200 nm is deposited over the entire surface of the silicon oxide film 303 by a CVD method.

Next, as shown in FIG. 8B, after a first resist pattern 305 is formed in a p-channel MOS transistor formation region on the non-doped polycrystalline silicon film 304, the first resist is formed. Pattern 305
Is used as a mask and, for example, phosphorus is
Ion implantation is performed at an implantation energy of eV and a dose of 4 × 10 ¹⁵ / cm ² to form an n-type polycrystalline silicon film 306 which becomes a part of the gate electrode.

Next, as shown in FIG. 8C, after a second resist pattern 307 is formed in the n-channel MOS transistor formation region on the non-doped polycrystalline silicon film 304, the second resist pattern 307 is formed. Pattern 307
Is used as a mask, and boron as a p-type impurity is
Ion implantation is performed at an implantation energy of keV and a dose of 4 × 10 ¹⁵ / cm ² to form a p-type polycrystalline silicon film 308 which is to be a part of the gate electrode.

Next, as shown in FIG. 9A, after removing the second resist pattern 307, annealing is performed at a temperature of 800 ° C. for about 30 minutes, for example.
After diffusing the impurities implanted in the n-type polycrystalline silicon film 306 and the p-type polycrystalline silicon film 308, n
By performing, for example, a CMP method on the p-type polycrystalline silicon film 306 and the p-type polycrystalline silicon film 308,
The surface portion is removed by 150 nm to form a thinned n-type polycrystalline silicon film 306A and a p-type polycrystalline silicon film 308A having a thickness of 50 nm.

Next, as shown in FIG. 9B, a 20 nm-thick barrier metal film is formed on the thinned n-type polycrystalline silicon film 306A and p-type polycrystalline silicon film 308A. A titanium nitride film 309 is deposited.

Next, as shown in FIG. 9C, a third insulating film having an opening in an element isolation region is formed on the titanium nitride film 309.
After the formation of the resist pattern 310, the p-type semiconductor region 3 is formed using the third resist pattern 310 as a mask.
01, an n-type semiconductor region 302, a silicon oxide film 303,
By selectively etching the thinned n-type polycrystalline silicon film 306A, the thinned p-type polycrystalline silicon film 308A and the titanium nitride film 309, an n-channel made of the p-type semiconductor region 301 is formed. Active region of MOS transistor, active region of p-channel MOS transistor including n-type semiconductor region 302, and element isolation trench 311
To form

Next, as shown in FIG. 9D, an isolation film is buried in the isolation trench 311 to form an isolation insulating film 312.

Next, as shown in FIG. 10A, a tungsten film 313 having a thickness of 80 nm as a high melting point metal film and a 50 nm film serving as a protective film are formed over the entire surface of the titanium nitride film 309. Silicon nitride film 31 having a thickness
4 are sequentially deposited, and a fourth resist pattern 315 is formed in the gate electrode formation region on the silicon nitride film 314.
To form

Next, as shown in FIG. 10B, dry etching is performed using the fourth resist pattern 315 as a mask, and a thinned n-type polycrystalline silicon film is formed in the n-channel MOS transistor formation region. 306A, n composed of a titanium nitride film 309 and a tungsten film 313
Gate electrode 316 and a gate insulating film 303A made of a silicon oxide film 303 are formed, and a thinned p-type polycrystalline silicon film 308A, a titanium nitride film 309, and a tungsten film 313 are formed in a p-channel MOS transistor formation region. Gate electrode 317 made of p-type and gate insulating film 303 made of silicon oxide film 303
Form A.

Next, as shown in FIG. 10C, an n-type impurity is ion-implanted into the p-type semiconductor region 301 using the n-type gate electrode 316 as a mask. And an n-type semiconductor region 30
A p-type impurity is ion-implanted into p-type low-concentration impurity region 31 using p-type gate electrode 317 as a mask.
9 is formed. Thereafter, the n-type gate electrode 316 and p-type
After the sidewall 320 is formed on the gate electrode 317 of the n-type, an n-type impurity is ion-implanted into the p-type semiconductor region 301 using the gate electrode 316 of the n-type and the sidewall 320 as a mask to perform high-concentration n-type impurity. Area 321
Is formed, and a p-type impurity is ion-implanted into the n-type semiconductor region 302 using the p-type gate electrode 317 and the sidewall 320 as a mask to form a p-type high-concentration impurity region 322.

Next, although not shown, if an interlayer insulating film, a contact, a metal wiring, and the like are formed by a known method, a tungsten film 313 having a thickness of 80 nm,
0 nm titanium nitride film 309 and thinned film thickness 50
A semiconductor device having a 150 nm-thick dual gate electrode made of an n-type polycrystalline silicon film 306A (p-type polycrystalline silicon film 308A) is obtained.

According to the third embodiment, before forming the element isolation insulating film 312, the n-type polycrystalline silicon film 306 is formed.
In addition, since the p-type polycrystalline silicon film 308 is thinned by the CMP method, the CMP method can be performed on the flat n-type polycrystalline silicon film 306 and the p-type polycrystalline silicon film 308. Therefore, since the thinned n-type polycrystalline silicon film 306A and p-type polycrystalline silicon film 308A do not have pattern dependency, high-precision CMP is performed.
Method can be performed, so that n
A polycrystalline silicon film 306A of a type and a polycrystalline silicon film 308A of a p-type can be obtained.

(Fourth Embodiment) Hereinafter, a semiconductor device and a method of manufacturing the same according to a fourth embodiment of the present invention will be described.
This will be described with reference to FIGS. 11 (a) to (d) and FIGS. 12 (a) to (c). First, as shown in FIG.
After the MOS transistors are separated from each other on the surface of the semiconductor substrate 400 and an element isolation insulating film 401 serving as a load element formation region is formed, the n-type semiconductor region 4 is formed in the p-channel MOS transistor formation region of the semiconductor substrate 400.
02 is formed. After that, a silicon oxide film 403 serving as a gate insulating film is formed on the n-type semiconductor region 402, and then 200 nm over the entire surface of the semiconductor substrate 400.
-Doped polycrystalline silicon film 404 having a thickness of
Is deposited by a CVD method.

Next, as shown in FIG. 11B, for example, boron as a p-type impurity is implanted into the non-doped polycrystalline silicon film 404 at an implantation energy of 20 keV and a dose of 4 × 10 ¹⁵ / cm ² . Ion implantation with the amount
After the formation of the polycrystalline silicon film 405 of
By performing annealing at a temperature of 0 ° C. for about 30 minutes, the impurities implanted in the p-type polycrystalline silicon film 405 are diffused.

Next, as shown in FIG. 11C, 50 nm is formed over the entire surface of the p-type polycrystalline silicon film 405.
After depositing a silicon nitride film 406 having a film thickness of about a degree, a first resist pattern 407 is formed on the silicon nitride film 406 in a resistance portion forming region of a load element.

Next, as shown in FIG. 11D, the silicon nitride film 406 and the p-type polycrystalline silicon film 405 are dry-etched using the first resist pattern 407 as a mask to form a silicon nitride film. By patterning 406 into the shape of the resistance portion of the load element and removing the surface portion (thickness 100 nm) of the p-type polycrystalline silicon film 405 while leaving the resistance portion formation region of the load element, the resistance of the load element is reduced. In a region other than the portion forming region, a p-type polycrystalline silicon film 405A (thickness 100 n
m).

Next, as shown in FIG. 12A, a 20 nm-thickness film serving as a barrier metal film is formed over the entire surface of the partially thinned p-type polycrystalline silicon film 405A. Titanium nitride film 408 and 8 as a refractory metal film
After sequentially depositing a tungsten film 409 having a thickness of 0 nm, a second resist pattern 410 is formed on the tungsten film 409.

Next, as shown in FIG. 12B, using the second resist pattern 410 as a mask, the tungsten film 409, the titanium nitride film 408, and the thinned p-type polycrystalline silicon film 405A are formed. Patterning is performed by dry etching. By this patterning step, in the p-channel MOS transistor formation region,
A tungsten film 409, a titanium nitride film 408, and a thinned p-type polycrystalline silicon film 405A.
A p-type gate electrode 411 having a thickness of nm is formed, and a gate insulating film 4 made of a silicon oxide film 403 is formed.
Form 03A. Further, by this patterning step, the load element formation region is formed of a portion of the p-type polycrystalline silicon film 405A that is not thinned.
a linear resistance portion 412a having a thickness of 10 nm, and a thinned p-type polycrystalline silicon film 405A formed on both ends of the linear resistance portion 412a.
A load element 412 composed of a pair of electrode connection parts 412b having a thickness of 0 nm is formed, and a resistance part 41 is formed.
A pair of terminal electrodes 413 made of a step-like tungsten film 409 are formed over each end of 2a and each of the pair of electrode connection portions 412b.

Next, as shown in FIG. 12C, a p-type impurity is ion-implanted into the n-type semiconductor region 402 using the p-type gate electrode 411 as a mask to form a p-type low-concentration impurity region 413. To form Then, after forming a sidewall 414 on the p-type gate electrode 411, the load element 412, and the pair of terminal electrodes 413, the n-type semiconductor region 40 is formed.
2 is ion-implanted with a p-type impurity using the p-type gate electrode 411 and the side wall 414 as a mask.
A high-concentration impurity region 415 is formed.

Next, although not shown, if an interlayer insulating film, a contact, a metal wiring, and the like are formed by a known method, a p-channel MOS transistor having a 200 nm-thick p-type gate electrode 411 is formed. 200nm thickness
And a load element 412 composed of a pair of electrode connection portions 412b having a thickness of 100 nm.

According to the fourth embodiment, the p-channel MO
The resistance value of the p-type gate electrode 410 of the S transistor is
The sheet resistance is 2 compared to the p-type polycrystalline silicon film 405.
Since it is determined by the tungsten film 409 which is about an order of magnitude smaller, the p-type gate electrode 411 is a thinned p-type polycrystalline silicon film 405A obtained by removing the surface of the p-type polycrystalline silicon film 405. Is used, there is almost no variation in the resistance value of the p-type gate electrode 411.

The resistance section 412a of the load element 412
Is composed of a p-type polycrystalline silicon film 405 whose surface has not been removed, that is, has a cross-sectional shape as it is deposited by the CVD method, so that the variation in resistance value is small.

Therefore, according to the fourth embodiment, in a semiconductor device in which the p-type gate electrode 411 of the p-channel MOS transistor and the load element 412 are formed in the same step, the p-type gate electrode 411 can be made thinner. It is possible to achieve both suppression of variation in the resistance value of the load element 412.

The terminal electrode 413 is connected to the load element 412
The terminal electrode 413 is formed in a stepped shape over the end portion of the resistance portion 412a and the electrode connection portion 412b.
Is connected to the load element 412 on both the bottom surface and the side surface, so that the load element 412 and the terminal electrode 413
The contact resistance with the load element 412 is greatly reduced, whereby the resistance value of the load element 412 can be accurately controlled.

In the fourth embodiment, the tungsten film 409, the titanium nitride film 408, and the thinned p
A p-type gate electrode 411 made of a polycrystalline silicon film 405A is formed, but instead of this, as in the second modification of the first embodiment described with reference to FIG. 5C. Alternatively, a gate electrode having a refractory metal silicide layer on the surface may be formed. That is, as shown in FIG. 11D, p-type polycrystalline silicon film 405A partially thinned is
In the channel MOS transistor formation region, a p-type gate electrode composed of the thinned p-type polycrystalline silicon film 405A is formed, and in the load element formation region, the p-type polycrystalline silicon film 405A is reduced in thickness. And a pair of electrode connection portions 412b formed of a thinned p-type polycrystalline silicon film 405A formed on both ends of the linear resistance portion 412, respectively. Is formed. Thereafter, after forming a sidewall on the p-type gate electrode, a cobalt film or a titanium film or the like is deposited over the entire surface, and thereafter, a heat treatment is performed so that the surface portion of the gate electrode and the electrode connection portion 412 b of the load element 412 are formed. Alternatively, a high melting point metal silicide layer made of a cobalt silicide layer or a titanium silicide layer may be formed.

In this case, the resistance portion 4 of the load element 412
A step of forming a terminal electrode 413 having a stepped shape extending over the end portion of the electrode 12a and the electrode connection portion 412b is separately required, but the titanium nitride film 408 is formed by the resistance portion 41 of the load element 412.
In order to prevent silicidation of the load element 412, the resistance of the resistance portion 412a of the load element 412 is avoided, while the resistance of the electrode connection section 412b of the load element 412 can be reduced. The contact resistance at the electrode connection portion 412b can be reduced.

[0128]

According to the first semiconductor device, since the height ratio of the stepped portion of the impurity-containing silicon film to the bottom is 0.6 or less, the impurity-containing silicon film formed on the substrate stepped portion and having the stepped portion is formed. Even if the thickness of the silicon film and the thickness of the barrier metal formed on the step portion of the impurity-containing silicon film are reduced, the barrier metal is not easily disconnected. Therefore, disconnection of the barrier metal can be prevented even if the thickness of the impurity-containing silicon film and the barrier metal having relatively large resistance values are reduced to reduce the resistance of the gate electrode.

According to the second semiconductor device, the terminal electrode is
The contact area between the load element and the terminal electrode is large because it is in contact with the upper surface of the end of the resistor of the load element, the wall surface between the end of the resistor and the electrode connection, and the upper surface of the electrode connection. Therefore, the contact resistance between the load element and the terminal electrode can be reduced.

According to the first to fifth methods for manufacturing a semiconductor device, an impurity-containing silicon film is formed by ion-implanting an impurity into a large-thickness silicon film deposited on a gate insulating film. Since the impurity-containing silicon film is thinned to form a gate electrode, even if the implantation energy for ion implantation is large, impurities do not penetrate into the gate insulating film and the thickness of the gate electrode is reduced. Therefore, a thin gate electrode can be reliably formed on a highly reliable gate insulating film.

In particular, according to the second method for fabricating a semiconductor device, it is possible to form a gate electrode composed of a laminated film of a low-resistance refractory metal silicide layer and a thinned polycrystalline silicon film. Even if the gate electrode is thinned,
An increase in the resistance value of the gate electrode can be suppressed.

In particular, according to the third method for fabricating a semiconductor device, the barrier metal film and the high-impurity layer are formed on the impurity-containing silicon film which is thinned after being deposited on the MOS transistor formation region of the semiconductor substrate and the substrate step. In order to form a gate electrode by depositing a melting point metal film and patterning a laminated film including the thinned impurity-containing silicon film, barrier metal film, and high-melting-point metal film, the height of the impurity-containing silicon film relative to the bottom at the step portion is reduced. The ratio of
Even if the thickness of the barrier metal film is small, disconnection of the barrier metal film can be suppressed. Accordingly, disconnection of the barrier metal can be prevented even if the thickness of the impurity-containing silicon film and the barrier metal film having relatively large resistance values are reduced to reduce the resistance of the gate electrode.

In particular, according to the fourth method of manufacturing a semiconductor device, a flat impurity-containing silicon film formed on a flat semiconductor substrate is thinned, so that the impurity thinned with high precision can be obtained. Since a silicon-containing silicon film can be obtained, the thickness of the impurity-containing silicon film having a relatively large resistance value is greatly reduced, and a gate electrode formed of a laminated film of a refractory metal and an impurity-containing silicon film is reduced in resistance. The thickness can be reduced without increasing.

In particular, according to the fifth method of manufacturing a semiconductor device, according to the gate electrode made of a high melting point metal film and a thinned impurity-containing silicon film, a load element made of a thinned impurity-containing silicon film, and a high melting point A terminal electrode made of a metal film can be formed at the same time, and the terminal electrode extends over an end portion of the resistor portion having a large thickness and an electrode connection portion having a small thickness, so that the contact area with the load element increases. Therefore, the contact resistance between the load element and the terminal electrode can be reduced.

In the first to fifth methods for manufacturing a semiconductor device, the MOS transistor formation region is formed of an n-channel MOS.
A transistor formation region and a p-channel MOS transistor formation region;
Ion implantation of an n-type impurity into the gate electrode formation region of the S transistor formation region and ion implantation of a p-type impurity into the gate electrode formation region of the p-channel MOS transistor formation region. A MOS transistor having a dual gate electrode can be reliably formed.

In the first to fifth methods for manufacturing a semiconductor device, after an impurity-containing silicon film is formed by ion-implanting an impurity into a silicon film having a thickness of 200 nm or more, the impurity-containing silicon film is formed to a thickness of 100 nm. When the thickness is reduced as follows, it is possible to reliably prevent impurities from penetrating into the gate insulating film, and to form a gate electrode having an extremely small thickness.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIGS. 3A and 3B are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. FIGS.

FIGS. 4A to 4C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a first modification of the first embodiment of the present invention. FIGS.

FIGS. 5A to 5C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second modification of the first embodiment of the present invention. FIGS.

FIGS. 6A to 6C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 7A and 7B are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

FIGS. 8A to 8C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 9A to 9D are cross-sectional views illustrating steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 10A to 10C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIGS. 11A to 11D are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. FIGS.

FIGS. 12A to 12C are cross-sectional views illustrating respective steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 13A to 13C are cross-sectional views showing steps of a method of manufacturing a semiconductor device in the first conventional example.

FIGS. 14A to 14C are cross-sectional views illustrating respective steps of a method of manufacturing a semiconductor device in the first conventional example.

FIGS. 15A to 15C are cross-sectional views illustrating respective steps of a method of manufacturing a semiconductor device in a second conventional example.

FIGS. 16A to 16D are cross-sectional views showing steps of a method of manufacturing a semiconductor device according to a third conventional example.

FIGS. 17A to 17C are cross-sectional views illustrating respective steps of a method of manufacturing a semiconductor device according to a third conventional example.

FIG. 18 is a diagram for explaining a problem of the method of manufacturing a semiconductor device according to the first conventional example, and is a diagram illustrating a relationship between a depth from a surface and a distribution of boron.

FIGS. 19A and 19B are cross-sectional views illustrating a problem of a method of manufacturing a semiconductor device according to a second conventional example.

DESCRIPTION OF SYMBOLS 100 semiconductor substrate 101 element isolation insulating film 102 p-type semiconductor region 103 n-type semiconductor region 104 silicon oxide film 104A gate insulating film 105 polycrystalline silicon film 106 first resist pattern 107 n-type polycrystalline silicon film 107A Thinned n-type polycrystalline silicon film 108 Second resist pattern 109 P-type polycrystalline silicon film 109A Thinned p-type polycrystalline silicon film 110 Titanium nitride film 111 Tungsten film 112 Silicon nitride film 113 Third resist pattern 114 n-type gate electrode 115 p-type gate electrode 116 n-type low concentration impurity region 117 p-type low concentration impurity region 118 sidewall 119 n-type high concentration impurity region 120 p-type high concentration Impurity region 130 BSG film 141 n -Type gate electrode 142 p-type gate electrode 143 refractory metal silicide layer 200 semiconductor substrate 201 element isolation insulating film 202 n-type semiconductor region 203 silicon oxide film 203A gate insulating film 204 non-doped polycrystalline silicon film 205 p-type poly Crystalline silicon film 205A thinned p-type polycrystalline silicon film 206 titanium nitride film 207 tungsten film 208 p-type gate electrode 300 semiconductor substrate 301 p-type semiconductor region 302 n-type semiconductor region 303 silicon oxide film 303A gate insulating film 304 Non-doped polycrystalline silicon film 305 First resist pattern 306 N-type polycrystalline silicon film 307 Second resist pattern 308 P-type polycrystalline silicon film 309 Titanium nitride film 310 Third resist pattern 311 Element isolation trench 312 Element isolation insulating film 313 Tungsten film 314 Silicon nitride film 315 Fourth resist pattern 316 N-type gate electrode 317 P-type gate electrode 318 n-type low-concentration impurity region 319 p-type low-concentration impurity region 320 Side wall 321 n-type high-concentration impurity region 322 p-type high-concentration impurity region 400 semiconductor substrate 401 element isolation insulating film 402 n-type semiconductor region 403 silicon oxide film 403A gate insulating film 404 non-doped polycrystalline silicon film 405 p-type polycrystalline Silicon film 405A Thinned p-type polycrystalline silicon film 406 Silicon nitride film 407 First resist pattern 408 Titanium nitride film 409 Tungsten film 410 Second resist pattern 411 P-type gate electrode 412 Load element 412a Resistance section 412b electrode connection portion 413 terminal electrode 414 sidewall 415 p-type high concentration impurity region

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DA06 DB03 DB10 EC01 EC02 EC04 EC07 EC13 EC28 EF02 EF11 EH02 EK05 FA03 FA17 FA18 FA19 FB02 FB04 FC00 FC10 FC19 5F048 AA07 AC03 AC10 BA01 BB06 BB07 BB08 BB09 BB03 DA19 DA20 DA21

Claims (9)

[Claims] A semiconductor substrate having a substrate step in a portion adjacent to a MOS transistor formation region; a semiconductor substrate formed on the semiconductor substrate so as to extend over the MOS transistor formation region and the substrate step; Semiconductor device comprising: an impurity-containing silicon film having a stepped portion, a barrier metal film formed on the impurity-containing silicon film, and a gate electrode made of a refractory metal film formed on the barrier metal film. 2. The semiconductor device according to claim 1, wherein a ratio of a height of the step portion of the impurity-containing silicon film to a bottom is 0.6 or less. 2. An element isolation insulating film formed on a surface portion of a semiconductor substrate; and a line-shaped insulating film provided on the element isolation insulating film and having a relatively large thickness in a conductive film. A load element comprising: a resistance portion; and a pair of electrode connection portions formed at both end sides of the resistance portion in the conductive film and each having a relatively small thickness, and each end of the resistance portion. And a pair of terminal electrodes made of a refractory metal film formed so as to extend over each of the pair of electrode connection portions. 3. A silicon film depositing step of forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate and then depositing a silicon film on the gate insulating film, and ion-implanting impurities into the silicon film. An ion-implanting step of forming an impurity-containing silicon film by removing the surface portion of the impurity-containing silicon film to form a thinned impurity-containing silicon film; and A patterning step of forming a gate electrode by patterning a film into a predetermined shape. 4. A step of forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate, and then depositing a silicon film on the gate insulating film, and ion-implanting impurities into the silicon film. An ion-implanting step of forming an impurity-containing silicon film by removing the surface portion of the impurity-containing silicon film to form a thinned impurity-containing silicon film; and A semiconductor device, comprising: a patterning step of forming a gate electrode by patterning a film into a predetermined shape; and a silicide layer forming step of forming a refractory metal silicide layer on a surface portion of the gate electrode. Production method. 5. An insulating film forming step of forming a gate insulating film in the MOS transistor forming region of a semiconductor substrate having a substrate step in a portion adjacent to the MOS transistor forming region; A silicon film deposition step of depositing a silicon film thereon; an ion implantation step of ion-implanting impurities into the silicon film to form an impurity-containing silicon film; and thinning by removing a surface portion of the impurity-containing silicon film. A thinning step of forming a doped impurity-containing silicon film; a metal film deposition step of sequentially depositing a barrier metal film and a high melting point metal film on the thinned impurity-containing silicon film; By patterning the barrier metal film and the thinned impurity-containing silicon film into a predetermined shape, the MO The method of manufacturing a semiconductor device characterized by and a patterning step of forming a gate electrode extending across over the transistor forming region and the substrate step portion. 6. A silicon film depositing step of forming a gate insulating film in a MOS transistor forming region on a semiconductor substrate and then depositing a silicon film on the gate insulating film, and ion-implanting impurities into the silicon film. An ion-implanting step of forming an impurity-containing silicon film by removing the surface portion of the impurity-containing silicon film to form a thinned impurity-containing silicon film; and A metal film deposition step of depositing a high melting point metal film on the film; forming an element isolation groove in an element isolation insulating film forming region on the semiconductor substrate; and embedding an insulating film in the element isolation groove. An element isolation insulating film forming step of forming a film, and patterning the refractory metal and the thinned impurity-containing silicon film into a predetermined shape. The method of manufacturing a semiconductor device characterized by and a patterning step of forming a gate electrode by. 7. An insulating film forming step of forming a gate insulating film in the MOS transistor forming region on a semiconductor substrate having a MOS transistor forming region and a load element forming region; A silicon film deposition step of depositing a silicon film in a load element formation region; an ion implantation step of forming an impurity-containing silicon film by ion-implanting an impurity into the silicon film; and loading the surface portion of the impurity-containing silicon film with the load. A thinning step of forming a thinned impurity-containing silicon film by removing the element forming region while leaving a resistance portion forming region; and depositing a high melting point metal film on the thinned impurity-containing silicon film. A metal film deposition step; and patterning the refractory metal film and the thinned impurity-containing silicon film into a predetermined shape. By grayed, the high to form a refractory metal layer and a gate electrode made of thinned impurity-containing silicon film, linear resistive portion made of the thinned portion not of the impurity-containing silicon film,
And forming a load element comprising a pair of electrode connecting portions formed of the thinned impurity-containing silicon film formed on both ends of the resistance portion, respectively, and each end of the resistance portion and the pair of electrodes. A patterning step of forming a pair of terminal electrodes made of the refractory metal film over each of the connection portions. 8. The semiconductor device according to claim 1, wherein the MOS transistor formation region is n
Channel MOS transistor formation region and p-channel MO
An S-transistor formation region, wherein the ion implantation step includes a step of ion-implanting an n-type impurity into a gate electrode formation region of the n-channel MOS transistor formation region in the silicon film; and a step of forming a p-channel MOS transistor in the silicon film. 8. The method of manufacturing a semiconductor device according to claim 3, further comprising: ion-implanting a p-type impurity into a gate electrode formation region of the region. 9. 9. The method according to claim 1, wherein the step of depositing the silicon film has a thickness of 20
A step of depositing a silicon film having a thickness of 0 nm or more, wherein the step of thinning comprises removing a surface portion of the impurity-containing silicon film so that the thickness of the thinned impurity-containing silicon film becomes 100 nm or less. The method of manufacturing a semiconductor device according to claim 3, further comprising: