JP2000068413A - Electronic circuit device having multilayer substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit device that can restrain the degradation of electrical characteristics for improving heat radiation. SOLUTION: A concave 24 is provided in a multilayer substrate 21. A ground conductor layer 30 is provided so that the bottom surface 25 of the concave 24 is included. An FET 2 is positioned in the concave 24. The source electrode of the FET 2 is connected to the ground conductor layer 30 in the concave 24 using a wire 29. A through-hole 39 is formed in the dielectric layer 36 under the FET 2 and filled with a conductor 41 having satisfactory heat radiating property. First and second dielectric layer 34, 35 are disposed on the ground conductor layer 30. A low-power FET 1, strip line conductor layers 9a, 10a, etc., and disposed on the first dielectric layer 34. A bias power conductor or the like is provided limitedly on the surface of the second dielectric layer 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device having a structure in which a semiconductor element such as a field effect transistor is mounted on a multilayer substrate.

[0002]

2. Description of the Related Art A high frequency power amplifier having a structure in which a field effect transistor is mounted on a multilayer substrate is disclosed in, for example, Japanese Patent Application Laid-Open No. 10-13 / 1998.
For example, it is known in JP-A-163 No.

[0003]

By the way, when a power semiconductor element is mounted on the upper surface of a multilayer substrate, heat dissipation is deteriorated and miniaturization is hindered. To solve this problem, a through hole is provided in the multilayer substrate, the lower side of the through hole is covered with a heat sink or a heat dissipation layer, and the semiconductor element is arranged in the through hole and the semiconductor element is fixed to the heat sink or the heat dissipation layer. There is a possible configuration. However, if a semiconductor element mounting hole is provided so as to penetrate the entire dielectric layer (insulator layer) of the multilayer substrate,
Not only is it difficult to achieve stable mechanical support of the semiconductor element easily, but also the wires for connecting the semiconductor element become longer and the high-frequency characteristics deteriorate.

Accordingly, an object of the present invention is to provide an electronic circuit device capable of improving heat dissipation while suppressing a decrease in electrical characteristics.

[0005]

In order to achieve the above object, the present invention has a multi-layer substrate and a semiconductor element, and the multi-layer substrate includes a high-frequency signal transmission path conductor layer, a ground conductor layer, and the semiconductor element. Wherein the multilayer substrate has at least first, second, and third dielectric layers, and the high-frequency signal transmission line conductor layer has the first conductive layer. The bias voltage supply circuit conductor layer is disposed between the first and second dielectric layers, and the ground conductor layer is disposed on the second and third dielectric layers. A concave portion provided on one main surface of the multilayer substrate so as to penetrate the first and second dielectric layers, wherein the semiconductor element is provided on the ground conductor layer exposed on a bottom surface of the concave portion; To the electronic circuit device located above It is a bad guy. As described in claim 2, it is possible to form a through hole in the dielectric layer between the bottom of the concave portion and the back surface (the other main surface) of the multilayer substrate, and fill the hole with a conductor having good heat conductivity. it can. Further, the semiconductor element can be fixed to the bottom of the concave portion, and the electrode on the surface of the semiconductor element can be connected to the ground conductor layer at the bottom of the concave portion. Further, an insulating protrusion can be provided between the semiconductor element fixing region at the bottom of the concave portion and the wire connection region (bonding pad).

[0006]

According to the invention of each claim, since the semiconductor element is arranged in the concave portion of the multilayer substrate, it is possible to prevent the semiconductor element from projecting from the surface of the multilayer substrate or to suppress the amount of projection. Not only can it be made thinner,
The thickness of the dielectric layer between the semiconductor element and the other main surface (back surface) of the multilayer substrate is reduced, and heat dissipation is improved. Claim 1
According to the invention, the ground conductor layer is disposed between the second and third dielectric layers. As a result, the first and second dielectric layers are interposed between the high-frequency signal transmission path conductor layer (for example, a stripline conductor layer) on the surface of the first dielectric layer and the ground conductor layer, and the distance between the two layers is reduced. Relatively long. As described above, when the distance between the two is long, the width of the conductor layer (strip line conductor layer) of the high-frequency signal transmission line can be increased when the impedance of the high-frequency signal transmission line is constant. When the width of the conductor layer of the high-frequency signal transmission line is increased in this manner, the electric loss of the transmission line is reduced, and the high-frequency characteristics are improved. According to the invention of claim 2, a through hole is provided in the dielectric layer between the bottom of the concave portion and the other main surface of the multilayer substrate,
Since the through conductor having good heat dissipation is filled here, the heat dissipation of the semiconductor element mounted in the recess can be enhanced. According to the third aspect of the present invention, since the connection of the electrode on the surface of the semiconductor element to the ground is made to the ground on the bottom of the recess, the length of the wire can be shortened, and the high-frequency characteristics are improved. According to the invention of claim 4, the adhesive or the bonding material for mounting the semiconductor element can be prevented from flowing out to the wire connection region by the protruding portion, and the connection of the wire can be reliably performed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a high-frequency power amplifier for a radio communication device as an electronic circuit device having a multilayer substrate according to an embodiment of the present invention will be described with reference to FIGS.

As shown in FIG. 1, the high-frequency power amplifier of this embodiment has a first FET (field effect transistor) 1 for low power, a second FET 2 for high power, and an input terminal 3.
Output terminal 4, first and second drain power terminals 5, 6, gate bias power terminal 7, first, second, and third matching circuits 8, 9, 10, and first and second 2, microstrip lines 11 and 12, lumped-parameter capacitors 13, 14, 15, and 16 and lumped-parameter resistors 17,
18 and 19. The first FET 1 has capacitors C1, C2, C3 and a resistor R1 in addition to the element body 1a.
Built-in.

FIG. 2 is a plan view schematically showing a geometric configuration of the high-frequency power amplifier having the circuit configuration of FIG. 1, and FIG. 3 is a cross-sectional view of a part of a line AA in FIG. FIG. One main surface 2 of the ceramic multilayer substrate 21 of the present embodiment
2, a first FET 1, three well-known matching circuits 8, 9, 10, various lumped-constant elements 23 collectively shown in one block, and the like are arranged as shown in FIG. 2. . Further, a concave portion 24 is provided in the first main surface 22. The recess 24 is formed by a first recess 24 a and a second recess 2.
4b. The second concave portion 24b is the first concave portion 24a.
And is formed shallower than the first concave portion 24a.

A second F is provided on the bottom surface 25 of the first concave portion 24a.
ET2 is fixed, and this drain electrode D is
6 is connected to the bottom surface of the second concave portion 24b, that is, the drain connection conductor layer 28 of the step portion 27. Also, FET2
The source electrode S is connected to the first concave portion 24a by the wire 29.
Is connected to the ground conductor layer 30 on the bottom surface 25. F
The gate electrode G of ET2 is connected to the gate connection conductor layer 32 of the step 27 by the wire 31. F in a plan view
The protrusions 33 formed so as to surround the three directions of the ET2 are formed by printing an insulating paint, and flow to form an adhesive layer 34a between the second FET 2 and the ground conductor layer 30. This is to prevent the adhesive from flowing from the fixing region of the FET 2 to the connection region of the wire 29 when an adhesive having properties is applied on the ground conductor layer 30.

The multilayer substrate 21 has first, second and third dielectric layers 34, 35 and 36 as shown in FIG. First
The surface of the dielectric layer 34 forms one main surface 22 of the substrate 21 shown in FIG. In FIG. 3, only the first FET 1 and the microstrip line conductor layers 9a and 10a included in the second and third matching circuits 9 and 10 are illustrated on the surface of the first dielectric layer 34 for explanation. I have. The microstrip line conductor layers 9a and 10a and various wiring conductor layers not shown are the first conductor layers of the multilayer substrate 21.

A first dielectric layer 34 and a second dielectric layer 35
And the second F as the second conductor layer of the multilayer substrate 21.
A drain connection conductor layer 28 for ET2, a gate connection conductor layer 32, and a conductor layer for forming the microstrip lines 11 and 12 shown in FIG. 1 are provided. Therefore, only the second conductor layer is locally disposed on the surface of the second dielectric layer 35. A first ground conductor layer 30 is formed on most of the surface of the third dielectric layer 36 as a third conductor layer of the multilayer substrate 21, and a second ground layer is formed on most of the back surface of the third dielectric layer 36. Ground conductor layer 37
Are formed. The first on the surface side of the third dielectric layer 36
The ground conductor layer 30 and the second ground conductor layer 37 on the back side are connected by conductors 40 and 41 filled in through holes 38 and 39 of the third dielectric layer 36. The through hole 39 is arranged below the fixing region of the second FET 2, and is filled with a metal having a higher thermal conductivity than that of the third dielectric layer 36. Therefore,
The conductor 41 of the through hole 39 functions as a heat radiator of the power FET 2.

The high-frequency power amplifier having the structure of this embodiment has the following effects. (1) Since the FET 2 is arranged in the concave portion 24, a reduction in thickness is achieved and heat dissipation is improved. (2) The ground conductor layer 30 is formed on the third dielectric layer 3 without providing a large-area ground conductor layer on the second dielectric layer 35.
6 and the drain connection conductor layer 28, the gate connection conductor layer 32, and the conductor layers for the microstrip lines 11 and 12 are locally provided on the surface of the second dielectric layer 35. A matching circuit 8 on the surface of the dielectric layer 34,
9, 10 strip line conductor layers 9a, 10a and the first
The conductor layer on the surface of the second dielectric layer 35 hardly hinders the microstrip line function based on the ground conductor layer 30 of the first and second dielectric layers 35, 35.
Effectively function as a dielectric layer of the microstrip line. Compared with the conventional case where the first ground conductor layer is provided on the surface of the second dielectric layer 35, the dielectric layer of the microstrip line is thicker, and the strip line conductor layer 9
In the case where the impedances based on a and 10a are kept the same, the width of the strip line conductor layers 9a and 10a can be widened, and the loss here can be reduced to improve the high frequency characteristics. (3) The concave portion 24 is provided in the multilayer substrate 21,
And the source electrode S is connected to the ground conductor layer 30 on the bottom surface 25 of the concave portion 24 by the wire 29. Therefore, the length of the connection conductor between the source electrode S and the ground, that is, the wire 29 is reduced, and the loss is reduced. In addition, unnecessary inductance is reduced, and high-frequency characteristics are improved. (4) A dam-like projection 33 is provided between the fixing region of the FET 2 on the bottom surface 25 of the recess 24 and the bonding region of the wire 29.
Is provided, it is possible to prevent the adhesive for fixing the FET 2 from flowing out into the bonding region, and it is possible to reliably achieve the bonding of the wire 29. (5) A through-hole 39 is provided below the fixing region of the FET 2,
Since the conductor 41 having a high thermal conductivity is filled here, heat dissipation is improved.

[0014]

Another Embodiment Next, a high-frequency power amplifier according to another embodiment will be described with reference to FIG. However, in FIG. 4, substantially the same parts as those in FIGS. 1 to 3 are denoted by the same reference numerals, and description thereof is omitted. In the embodiment of FIG. 4, the dielectric layers 34, 35,
Reference numeral 36 denotes a glass epoxy resin, that is, an epoxy resin mixed with glass. That is, each dielectric layer 3 in FIG.
Reference numerals 4, 35, and 36 denote printed circuit boards, and each layer is bonded with an adhesive (not shown). In FIG. 4, the first FET 1 also has a recess 50 formed similarly to the recess 24a.
Is disposed on the ground conductor layer 30 at the bottom of the
The emitter is connected to a pad 52 of the ground conductor layer 30 by a wire 51. Also,
A dam-shaped protrusion 33 is provided between the pad 52 and the first FET 1.
a is provided. First FET1 and second FET2
Only the second dielectric layer 35 remains between them, and is used for connecting the first and second FETs 1 and 2. According to the embodiment of FIG. 4, the same operation and effects as those of the embodiment of FIGS. 1 to 3 can be obtained.

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) A plurality of semiconductor elements (for example, both a drive stage FET and an output stage FET) can be arranged in the recess 24. (2) More than two dielectric layers and conductor layers are arranged above the first ground conductor layer 30, and more than one dielectric layer and conductor are arranged below the first ground conductor layer 30. Layers can be arranged. (3) Another semiconductor element such as a bipolar transistor can be arranged instead of the FETs 1 and 2.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a high-frequency power amplifier according to an embodiment of the present invention.

FIG. 2 is a plan view schematically showing a high-frequency power amplifier according to an embodiment.

FIG. 3 is a cross-sectional view showing a part of a line AA in FIG. 2;

FIG. 4 is a sectional view showing a high-frequency power amplifier according to another embodiment, similarly to FIG.

[Explanation of symbols]

 1, 2 FET 3 Input terminal 4 Output terminal 9a, 10a Strip line conductor layer 21 Multilayer substrate 24 Depression 30, 37 Ground conductor layer 33 Projection

Claims (4)

[Claims] An electronic circuit having a multilayer substrate and a semiconductor element, wherein the multilayer substrate has a high-frequency signal transmission line conductor layer, a ground conductor layer, and a bias voltage supply circuit conductor layer for the semiconductor element. In the apparatus, the multilayer substrate has at least first, second, and third dielectric layers, the high-frequency signal transmission line conductor layer is disposed on a surface of the first dielectric layer, and the bias voltage supply circuit A conductor layer disposed between the first and second dielectric layers; a ground conductor layer disposed between the second and third dielectric layers; An electronic circuit device, wherein a concave portion is provided so as to penetrate the first and second dielectric layers, and the semiconductor element is disposed on the ground conductor layer exposed on a bottom surface of the concave portion. 2. An electronic circuit device comprising: a multi-layer substrate including a plurality of dielectric layers and a plurality of conductor layers; and a semiconductor element mounted on the multi-layer substrate, wherein the multi-layer substrate has one main surface. A concave portion, the concave portion is formed so as to penetrate at least one of the plurality of dielectric layers, the semiconductor element is disposed at the bottom of the concave portion, and the bottom of the concave portion and the multilayer substrate An electronic circuit device, wherein the dielectric layer between the other main surface has a through hole, and the through hole is filled with a conductor having better thermal conductivity than the dielectric layer. 3. An electronic circuit device comprising: a multilayer substrate including a plurality of dielectric layers and a plurality of conductor layers; and a semiconductor element mounted on the multilayer substrate, wherein the multilayer substrate has one main surface. A concave portion, wherein the concave portion is formed so as to penetrate at least one of the plurality of dielectric layers, a ground conductor layer is provided at a bottom of the concave portion, and the ground conductor at a bottom of the concave portion is provided. An electronic circuit device, wherein the semiconductor element is fixed to a layer, and a ground conductor layer at a bottom of the concave portion and an electrode on a surface of the semiconductor element are connected by a wire. 4. The semiconductor device according to claim 3, wherein an insulating protrusion is provided between a fixing region of the semiconductor element on a ground conductor layer at a bottom of the concave portion and a connection region of the wire. Electronic circuit device.