JP2000056734A - Display control system of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a high quality picture by improving the contrast of a screen and preventing the generation of interference fringes or EMI. SOLUTION: The system is provided with a liquid crystal panel 1, which is equally divided into upper and lower screens, a line driver 2, upper and lower screen data drivers 3a and 3b, which sum the coincidence number between the display data value on the line electrodes of scanning electrode groups that are applied with a selection voltage to data electrodes and the orthogonal function data value given to the line electrodes for every line electrode group and apply the data voltage in accordance with the sum, a data memory 62, which stores display data 7 supplied from a liquid crystal display system main body 9, and a power supply circuit 10 which divides the display data into upper and lower screen data based on various clock signals 8, generates the power supply voltage for a display controller 6, the line driver 2 and the data drivers 3a and 3b and supplies these voltage groups to the drivers. Then, plural line electrodes constituting each dividing line electrode group are selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control system for a liquid crystal display device, and more particularly to a display control system for a simple matrix type liquid crystal display device having improved frame response and contrast.

[0002]

2. Description of the Related Art A liquid crystal display device using a liquid crystal panel is widely used as a display device of various information processing terminals and television receivers. In this type of liquid crystal display device,
A simple matrix type in which a pixel is selected by a pair of electrodes crossing each other with a liquid crystal layer interposed therebetween and an active matrix type in which an image is displayed by selectively turning on / off a switching element corresponding to each pixel are known. Have been.

[0003] In particular, those using a simple matrix type liquid crystal panel have the advantage of low cost because of their simple structure.

A driving method of a liquid crystal display device having a simple matrix type liquid crystal panel is described in "Liquid Crystal Device Handbook" 395-P. 399, the voltage averaging method is widely adopted. In this method, a selection scanning voltage is sequentially applied to scanning electrodes (scanning signal electrodes, line electrodes, or common electrodes) corresponding to rows of a liquid crystal panel one by one for one scanning period, and all the scanning voltages are applied for one frame period. When the scanning electrode is scanned, the same operation is repeated again.

A data voltage corresponding to the display data value is applied to data electrodes (segment electrodes, video signal electrodes) corresponding to the columns of the liquid crystal panel, centering on the non-selection scanning voltage level. Further, an alternating operation for inverting the polarity of the liquid crystal applied voltage at regular intervals is performed.

On the other hand, another driving method of a liquid crystal display device having a simple matrix type liquid crystal panel is disclosed in
There is a multiple line selection drive system described in Japanese Patent No. 67628. In this method, a selection scanning voltage corresponding to an orthogonal function (for example, a Walsh function) is sequentially applied to scanning electrodes corresponding to the rows of the liquid crystal panel in a plurality of rows, and the scanning electrodes are all displayed in one frame period for displaying one screen. When the scanning electrode is scanned, the same operation is repeated again to display an image.

As described above, as a driving method of a simple matrix type liquid crystal display, a voltage averaging method, so-called Hi, has conventionally been used.
-Fas driving method or high addressing driving method is known.

FIG. 9 is a block diagram for explaining a display control system of a simple matrix type liquid crystal display device. The liquid crystal panel 1 has a large number of data electrodes in a vertical direction (up and down direction) and a large number of scanning electrodes (hereinafter also referred to as line electrodes) in a horizontal direction (left and right direction), and each intersection of the data electrode and the scanning electrode. Constitute one pixel. The scanning electrode is vertically divided into two equal parts, and pixels (dots) are displayed based on screen display data applied to the data electrode from the data driver 3 at the intersection of the scanning electrode and the data electrode selected by the line driver 2. .

The data driver 3 includes a display controller 6
, And the line driver 2 is applied with a clock signal such as a frame clock and a line clock generated by the display controller 6. The data driver 3 supplies display data to predetermined data electrodes in synchronization with the pixel clock generated by the display controller 6.

The display controller 6 has a driver control circuit 61 and a data memory 62. Based on display data 7 and a clock signal 8 from the display system body 9, screen display data 4 and a frame clock, a line clock,
A clock signal such as a pixel clock is generated. The power supply 10 generates and supplies various voltages required for each of the above-described components.

[0011]

FIG. 10 is an explanatory diagram of a driving method of a liquid crystal display device using a voltage averaging method or a Hi-Fas driving method. In this driving method, the screen is divided equally into upper and lower parts. In the figure, the lines are 1-2n
, Lines 1 to n are displayed on the upper screen, lines n + 1 to 2n
Is the lower screen.

In this drive, the upper screen and the lower screen are sequentially and simultaneously scanned from line 1 of the upper screen and line n + 1 of the lower screen, with six lines as one unit. In the drawing, one cell indicates one pixel, and pixels indicated by hatching indicate pixels to be displayed.

FIG. 11 is an explanatory diagram of a driving method of a liquid crystal display device using a high addressing driving method. In this driving method, the screen is equally divided into upper and lower parts as in FIG. 10 and display is performed for each three pixels in the line direction.

FIG. 12 is a waveform diagram showing a frame response in the driving method shown in FIGS. 10 and 11, wherein the horizontal axis represents time (mS) and the vertical axis represents luminance (voltage value V measured using a luminance meter). ).

As can be seen from the frame response waveform shown in the figure, since the period from the selection pulse (pixel selection pulse) to the next selection pulse is long, the luminance decay period is long and the pixel is turned on (ON: dot display). The average luminance of the pixel decreases. On the other hand, the OFF (non-display) waveform is increased by the selection pulse, and the OFF average luminance is slightly increased.

Therefore, the brightness of the screen as a whole did not increase, and it was difficult to improve the contrast. Further, interference fringes in halftone display may appear due to mismatching with the driver control circuit.

FIG. 13 is a main part configuration diagram of a liquid crystal panel for explaining a method of taking display data into a data driver in a conventional liquid crystal display device. In the figure, 1 is a liquid crystal panel, SEG Dr-1 to SEG Dr-10 are data drivers, BA is a buffer amplifier, DTL is a data line, CLL is a clock line, and D [7 ... 0] is display data (screen). Display data), CLCK (CL1, CL
2) is a clock (CL1 is a line clock, CL2 is a pixel clock).

A conventional data driver (segment driver) uses a plurality of data drivers (driver chips) SE arranged along the long side of the liquid crystal panel.
Display data necessary for each driver is fetched sequentially from the data driver SEG Dr-1 on the left side of the screen among the GDr-1 to SEG Dr-10 along the long side of the liquid crystal panel.

For example, when a driver chip (segment driver (SEG Dr)) with SVGA (600 × 2400 dots) and 8-bit data input / 240 output is used, first, the left-side data driver SEG Dr-1 is 8 bit × CL2 24 in the first 30 clocks (0 to 30)
Then, the second data driver SEG Dr-2 from the left takes in 240 bits of data at 30 clocks (31 to 60) of 8 bits × the next pixel clock, and the rightmost data Driver SEGDr-10
Is finally 8 bits × CL2 30 clocks (271 to 3)
00).

In this case, the pixel clock CL2 necessary for taking in the data is 3 in one horizontal period (scanning time of one line).
Therefore, the frequency of the pixel clock CL2 must be at least 300 times the frequency of the line clock CL1.

FIG. 14 is a waveform diagram of the pixel clock. When the frequency of the pixel clock increases, the reflection noise NZ is superimposed on the pixel clock as shown in FIG. If the count threshold value _VTH of the driver chip is exceeded, a mounting error occurs and an image flickers. When the pixel clock has a high frequency, so-called EMI noise is generated.

Further, if the driving frequency is increased, the frame response can be suppressed and the contrast can be increased, but it is difficult to increase the driving frequency due to the input limit of the clock AC characteristic driver.

An object of the present invention is to solve the above-mentioned problems of the prior art, to improve the contrast of the screen, to obtain interference fringes, shadowing, pixel clock reflection noise, or E.
It is an object of the present invention to provide a display control system of a liquid crystal display device which can display a high quality image by preventing the occurrence of MI.

[0024]

In order to achieve the above object, the present invention divides a display screen of a liquid crystal panel into upper and lower equal parts, and simultaneously and sequentially selects two lines each of an upper screen and a lower screen. . Alternatively, the upper and lower sides of the upper screen are simultaneously and sequentially selected one by one, and the lower screen is sequentially scanned by selecting even lines before odd lines. Or,
The upper and lower sides of the upper screen are simultaneously and sequentially selected one by one, and the lower screen selects even lines before the odd lines and scans them sequentially. Replaced on the screen.

Further, according to the present invention, the input screen display data is divided on the left and right sides of the screen, and the right half and the left half data are simultaneously taken into the data driver.

That is, the present invention provides the following (1) to
The feature is that the configuration described in (4) is adopted.

(1) A large number of scanning electrodes which are equally divided into an upper screen and a lower screen, a liquid crystal panel in which a pixel is formed at each intersection of a large number of data electrodes intersecting with the scanning electrodes, and Scanning voltage driving means for applying a two-level selection voltage having positive and negative polarities centered on a non-selection voltage in accordance with the value of orthogonal function data to the electrodes, and applying the selection voltage to the data electrodes The number of matches between the display data value on each scan electrode of the scan electrode group and the orthogonal function data value given to each scan electrode is totaled for each scan electrode group, and the data voltage corresponding to the total value is calculated. , A data memory for storing display data supplied from the liquid crystal display system body, and dividing the display data into upper screen data and lower screen data based on various clock signals. A display controller including a driver control circuit for generating a frame clock, a line clock, and a pixel clock, voltages of the number of levels required to drive the liquid crystal panel, the scanning voltage driving unit, and the data voltage driving unit And a power supply unit for generating a power supply voltage for the scan voltage driving means and the data voltage driving means for supplying these voltage groups to the scanning voltage driving means and the data voltage driving means. The method is characterized in that a plurality of scanning electrodes constituting a divided scanning electrode group by being divided into groups are simultaneously and sequentially selected and applied.

According to the configuration (1), the frame response is improved, the contrast of the screen is increased, and the occurrence of interference fringes and shadowing is prevented, so that a high quality screen display can be obtained.

(2) The scanning electrodes selected simultaneously and sequentially in (1) are two scanning electrodes which are vertically adjacent to each other in each of the scanning electrode groups.

(3) Each of the upper screen and the lower screen in (1) is further divided into an upper subdivision scanning electrode group and a lower subdivision scanning electrode group subdivided equally into upper and lower parts. In the upper scan electrode group, the scan electrodes selected are odd numbers of the upper subdivided scan electrode group, and the lower scan electrode groups are even even numbers of the lower subdivided scan electrode group. And

According to the above configurations (2) and (3), the contrast of the screen is improved, interference fringes and shadowing are prevented, and a high-quality screen display can be obtained.

(4) In each of the frame clocks in (3), the odd-numbered and even-numbered surfaces of the upper subdivided scan electrode group and the lower subdivided scan electrode group are referred to as the upper scan electrode group and the lower scan electrode group. And is replaced by

With this configuration, the frame frequency can be increased, the reflection noise can be prevented from being superimposed on the pixel clock, and the occurrence of EMI noise can be prevented.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

FIG. 1 is a block diagram illustrating a display control system of a liquid crystal display device according to the present invention. As described above, the liquid crystal panel 1 has a large number of data electrodes in the vertical direction (vertical direction) and a large number of scanning electrodes (hereinafter, also referred to as line electrodes or simply lines) in the horizontal direction (horizontal direction). One pixel is formed at each intersection of the data electrode and the scanning electrode. The data driver includes an upper screen data driver 3a and a lower screen data driver 3b, and applies display data to the upper screen and the lower screen, respectively.

The scanning electrodes are vertically divided into two equal parts. At the intersection of the scanning electrodes and the data electrodes selected by the line driver 2, the upper screen data driver 3a and the lower screen data driver 3b respectively connect the upper and lower data electrodes. Pixels (dots) are displayed based on the applied screen display data.

The upper screen data driver 3a receives upper screen display data 4a from the display controller 6, and the lower screen data driver 3b receives lower screen display data 4b from the display controller 6. Line driver 2
, A clock signal 5 such as a frame clock and a line clock generated by the display controller 6 is also applied. The upper screen data driver 3a and the lower screen data driver 3b are supplied with display data to predetermined data electrodes in synchronization with the pixel clock generated by the display controller 6.

The display controller 6 has a driver control circuit 61 and a data memory 62. Based on the display data 7 and the clock signal 8 from the display system main body 9, the upper screen display data 4a, the lower screen display data 4b, the frame clock, It generates clock signals such as a line clock and a pixel clock. The power supply 10 generates and supplies various voltages required for each of the above-described components.

FIG. 2 is an explanatory diagram of a first embodiment of the display control system of the liquid crystal display device according to the present invention. In this embodiment, each of the upper screen and the lower screen is simultaneously and sequentially selected by two lines. The number of lines of the entire screen is 1 to 2n, the lines 1 to n are the upper screen, and the lines n + 1 to 2n are the lower screen.

That is, the scanning electrodes 1 to 2n constituting the upper screen and the lower screen are equally divided into scanning electrode groups 1 to n and n + 1 to 2
n, and a plurality of scan electrodes constituting divided scan electrode groups 1 to n on the upper screen, and divided scan electrode groups n + 1 to 2 on the lower screen
A plurality of scanning electrodes constituting n are simultaneously and sequentially selected for every two lines and applied.

In the figure, lines 1 and 2 on the upper screen,
And simultaneously scan (select) lines n + 1 and n + 2 on the lower screen, and then simultaneously scan lines 3 and 4 on the upper screen and lines n + 3 and n + 4 on the lower screen in order, and so on. The screen and the lower screen are scanned simultaneously and sequentially. Hereinafter, this scanning pattern is referred to as pattern a.

By performing the scanning in this manner, the frequency of selecting the line electrode is doubled, and the influence of the frame response is reduced as compared with the related art. Therefore, the average ON luminance increases and the average OFF luminance decreases.

FIG. 3 is a waveform diagram showing a frame response in the driving method shown in FIG. 2, and the horizontal axis represents time (mS).
The vertical axis indicates luminance (voltage value V measured using a luminance meter).

As can be seen from the frame response waveform shown in the figure, the frame frequency is twice that of the conventional one shown in FIG. 12, and since the period from one selection pulse to the next selection pulse is shortened, the luminance decay period is reduced. And the decrease in the average luminance of the turned-on pixels is reduced. On the other hand, the off waveform also becomes smaller. Therefore, the brightness of the screen is increased as a whole, and the contrast is improved.

FIG. 4 is an explanatory diagram of a second embodiment of the display control system of the liquid crystal display device according to the present invention. In this embodiment, the upper screen and the lower screen are simultaneously and sequentially selected by two lines in the same manner as in the previous embodiment. The number of lines in the entire screen is 1 to 2n, the lines 1 to n are the upper screen, the line n +
1 to 2n as the lower screen, and the upper screen as lines 1 to n /
2 and (n / 2) +1 to n, the lower screen is line n + 1 to (3
n / 2) and (3n / 2) +1 to 2n, each of which is divided into an upper subdivided scan electrode group and a lower subdivided scan electrode group, and the scan electrodes selected simultaneously and sequentially in the first embodiment. The upper scanning electrode group of the upper and lower screens is an even number of the continuous upper subdivided scan electrode group, and the lower scan electrode group is an even number of the continuous lower subdivided scan electrode group. Hereinafter, this scanning pattern is referred to as a pattern b.

Also in this embodiment, as shown in FIG. 3, the frame frequency is twice that of the conventional one shown in FIG. 12, and the period from one selection pulse to the next selection pulse is shortened. Becomes shorter, and the decrease in the average luminance of the turned-on pixels is reduced. On the other hand, the off waveform also becomes smaller. Therefore, the brightness of the screen is increased as a whole, and the contrast is improved.

FIG. 5 is an explanatory view of a display control system for a liquid crystal display device according to a third embodiment of the present invention. In this embodiment, a line that continues one of the upper and lower screens (the upper screen in FIG. 5) is selected line-sequentially (hereinafter, this scanning pattern is referred to as a pattern c), and the other screen (the lower screen in FIG. 5) is selected. This is performed using the pattern b described in FIG. 4, and the pattern b and the pattern c are exchanged for each frame pulse and scanning is performed.
Note that FLMC in the figure is a 1/2 frame pulse.

Similarly, in this embodiment, the frame frequency is twice that of the prior art, and the period of time from one selection pulse to the next selection pulse is shortened, so that the luminance decay period is shortened. Is less reduced. On the other hand, the off waveform also becomes smaller. Therefore, the brightness of the screen is increased as a whole, and the contrast is improved.

FIG. 6 is an explanatory diagram of a display control system for a liquid crystal display device according to a fourth embodiment of the present invention. In this embodiment, the screen is divided in the same manner as in FIG. 5, and the pattern b and the pattern c are switched every frame pulse and scanned for each output of each line driver.

Similarly, in this embodiment, the frame frequency is twice that of the prior art, and the period of time from one selection pulse to the next selection pulse is shortened, so that the luminance decay period is shortened. Is less reduced. On the other hand, the off waveform also becomes smaller. Therefore, the brightness of the screen is increased as a whole, and the contrast is improved.

According to each of the above-described embodiments, as shown in FIG. 3, the frequency of line selection is twice that of the conventional example, so that the influence of the frame response is smaller than that of the conventional example, and the average ON luminance is reduced. The average brightness off and up is reduced, and the contrast is greatly improved. Further, the halftone FRC pattern (time-division control display pattern for halftone display) by the display controller has a display defect due to interference by line-sequential selection such as a voltage averaging method or Hi-FAS drive commonly used in the market. And the scanning pattern of the above embodiment has a simple configuration similar to line-sequential selection.
The vertical and horizontal flickering of the screen caused by the interference with the RC pattern is avoided, and a high-quality display screen can be obtained.

FIG. 7 is a diagram showing a main part of a liquid crystal panel for explaining a method of taking display data into a data driver for explaining a fifth embodiment of the display control system for a liquid crystal display device according to the present invention. In the figure, 1 is a liquid crystal panel, SEG
Dr-1 to SEGDr-5 are data drivers for the left screen, SEG Dr-6 to SEG Dr-10 are data drivers for the right screen, BA is a buffer amplifier, DTL-L
Is a data line for the left screen, DTL-R is a data line for the right screen, CLL is a clock line, LD [7...
0] is display data for the left screen (screen display data), RD
[7 ... 0] is display data (screen display data) for the right screen, CL1 is a line clock, and CL2 is a pixel clock.

FIG. 8 is a timing chart for explaining a data fetching method of a data driver for explaining a fifth embodiment of the display control system of the liquid crystal display device according to the present invention. In this embodiment, the data driver (segment driver) is divided into a left half (SEG Dr-1 to SEGDr-5) and a right half (SEG Dr-6 to SEGDr-10) of the screen, and the clocks CL1 and CL2 simultaneously. Capture data.

In this embodiment, the data lines (DTL-L, DTL-R) for the left screen and the right screen are routed on the printed circuit board on which the data driver is mounted, and the display controller 6 transfers the display data to the left and right screens. And input to the buffer amplifier BA.

With this configuration, since data is simultaneously input to the left and right sides of the screen, the pixel clock CL
2 is half the conventional value, and the frequency of the pixel clock CL2 is reduced to half. For this reason, it is possible to reduce the occurrence of reflection noise and EMI caused by a high-speed drive product (mainly the buffer amplifier BA), and the buffer amplifier and the like can be used as a medium-speed drive component. In addition, AC of the clock signal
The problem that the driving frequency cannot be increased due to the limit of the characteristic driver input can be solved.

In the above embodiment, an SVGA liquid crystal panel has been described as an example.
Needless to say, the present invention can be similarly applied to the liquid crystal panel A.

[0057]

As described above, according to the present invention,
LCD that improves frame response and screen contrast, improves screen contrast, and enables high-quality image display by preventing interference fringes, shadowing, pixel clock reflection noise, or EMI. A display control system for a display device can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a display control system of a liquid crystal display device according to the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of a display control system for a liquid crystal display device according to the present invention.

FIG. 3 is a waveform chart showing a frame response in the driving method shown in FIG. 2;

FIG. 4 is an explanatory diagram of a second embodiment of the display control system of the liquid crystal display device according to the present invention.

FIG. 5 is an explanatory diagram of a third embodiment of the display control system of the liquid crystal display device according to the present invention.

FIG. 6 is an explanatory diagram of a display control system for a liquid crystal display device according to a fourth embodiment of the present invention.

FIG. 7 is a main part configuration diagram of a liquid crystal panel explaining a method of taking in display data into a data driver for explaining a fifth embodiment of the display control system of the liquid crystal display device according to the present invention.

FIG. 8 is a timing chart for explaining a data fetching method of a data driver for explaining a fifth embodiment of the display control system of the liquid crystal display device according to the present invention.

FIG. 9 is a block diagram illustrating a display control system of a simple matrix type liquid crystal display device.

FIG. 10 is an explanatory diagram of a driving method of a liquid crystal display device using a voltage averaging method or a Hi-Fas driving method.

FIG. 11 is an explanatory diagram of a driving method of a liquid crystal display device using a high addressing driving method.

FIG. 12 is a waveform chart showing a frame response in the driving method shown in FIGS. 10 and 11;

FIG. 13 is a main part configuration diagram of a liquid crystal panel for explaining a method of taking display data into a data driver in a conventional liquid crystal display device.

FIG. 14 is a waveform diagram of a pixel clock.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 Line driver 3 Data driver 4a Upper screen display data 4b Lower screen display data 5 Clock signal 6 Display controller 61 Driver control circuit 62 Data memory 7 Display data 8 Clock signal 9 Display system body 10 Power supply circuit.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Toshimitsu Matsudo 3300 Hayano, Mobara-shi, Chiba F-term in the Electronic Devices Division, Hitachi, Ltd. 2H093 NA22 NA43 NA44 NC03 NC09 NC15 ND04 5C006 AC02 AC23 AC25 AF42 AF44 AF71 BB12 BB14 BC03 BC20 BF02 BF25 FA22 FA24 FA32 FA54

Claims (4)

[Claims] 1. A liquid crystal panel having a plurality of scan electrodes divided equally into an upper screen and a lower screen, a liquid crystal panel having a pixel at each intersection of a plurality of data electrodes intersecting the scan electrodes, and Scanning electrode driving means for applying a two-level selection voltage having positive and negative polarities centered on a non-selection voltage in accordance with the value of orthogonal function data; and scanning in which the selection voltage is applied to the data electrodes. The number of matches between the display data value on each scan electrode of the electrode group and the orthogonal function data value given to each scan electrode is totaled for each scan electrode group, and a data voltage corresponding to the total value is applied. Data electrode driving means, a data memory for storing display data supplied from the liquid crystal display system main body, and dividing the display data into upper screen data and lower screen data based on various clock signals, A display controller comprising a driver control circuit for generating a frame clock, a line clock, and a pixel clock; voltages of the number of levels required for driving the liquid crystal panel; and power supplies for the scanning voltage driving means and the data voltage driving means. A power supply unit for generating a voltage and supplying these voltage groups to the scanning voltage driving unit and the data voltage driving unit, wherein each of the scanning electrodes constituting the upper screen and the lower screen is a scanning electrode group equally divided A display control system for a liquid crystal display device, wherein a plurality of scan electrodes constituting a divided scan electrode group are divided and selected simultaneously and sequentially and applied. 2. The liquid crystal display device according to claim 1, wherein the simultaneously and sequentially selected scanning electrodes are two scanning electrodes which are vertically adjacent to each other in each of the scanning electrode groups. Display control system. 3. The method according to claim 1, wherein each of the upper screen and the lower screen is further divided into an upper subdivided scanning electrode group and a lower subdivided scan electrode group, which are subdivided equally into upper and lower parts. The electrode is an odd number of the upper subdivided scan electrode group in the upper scan electrode group, and is an even number of the lower subdivided scan electrode group in the lower scan electrode group. Display control system for a liquid crystal display device according to item 1. 4. The method according to claim 1, wherein an odd-numbered surface and an even-numbered surface of the upper subdivided scan electrode group and the lower subdivided scan electrode group are replaced by the upper scan electrode group and the lower scan electrode group for each frame clock. The display control system for a liquid crystal display device according to claim 3, wherein: