JP2000055759A - Manufacture of semiconductor pressure sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve practicality by using electrochemical stop etching for forming a cavity and at the same time for forming a cavity in closed structure by film formation. SOLUTION: A P well region 4 and an N well region 5 are formed on the surface-layer part of a silicon substrate 3 where the face orientation on the surface is (100), a trench 26 that is continuously or discontinuously extended in either the <110> or <100> direction of the silicon substrate and is fed through the N well region 5 is formed at the N well region 5, a potential difference is generated between the well regions 4 and 5 through aluminum wiring 20 and 21, at the same time a monocrystalline silicon substrate at the lower side of the N well region 5 is etched by injecting an anisotropic etching liquid through a trench 26, etching is stopped at the interface part of the well regions 4 and 5, and a cavity 7 with the N well region 5 as a diaphragm is formed. After aluminum wiring 20 and 21 is eliminated, a film for sealing is formed to block the trench 26.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor pressure sensor.

[0002]

2. Description of the Related Art Along with the recent miniaturization and high accuracy of a semiconductor sensor chip, a diaphragm serving as a sensing unit has been reduced in size, thickness, and accuracy. The applicant is Japanese Patent Application No. Hei 9
-295678 No.
A method for manufacturing a sensor having a thin diaphragm is proposed. As one of them, as shown in FIG. 27, while performing anisotropic silicon etching from micro holes 51 arranged in an X-shape or cross on the surface of a silicon substrate 50,
A potential difference is generated between the respective regions 52 and 53 of the double diffusion region formed in the surface layer portion of the silicon substrate 50 to perform electrochemical stop etching to form a cavity 54 serving as a reference pressure chamber. 51 is vacuum-sealed to form a sensing unit.

When vacuuming the microhole 51, the pressure is reduced (L
P) When a thin film for sealing is formed by the CVD method, excellent embedding properties can be obtained and high reliability can be obtained. However, the following problems remain.

That is, the thickness of the diaphragm is stably controlled by using electrochemical stop etching.
In order to achieve a good yield, it is important not to have a potential gradient over the entire surface of the wafer. For this reason, it is simple in terms of process design to take a means of extending aluminum metal wiring so that a potential gradient is not generated as much as possible in all chips arranged on the wafer.

However, after electrochemical stop etching using aluminum wiring, sealing by the reduced pressure CVD cannot be performed. This is because there is no match between the wiring using aluminum whose melting temperature is about 600 ° C. and the low pressure CVD method for forming a film at about 600 ° C. to 800 ° C.

In general, the formation of an aluminum wiring for electrochemical stop etching and the formation of an aluminum wiring for a gauge resistor and an integrated circuit portion with a built-in chip are generally performed simultaneously using the same aluminum pattern mask. For this reason, it has not been possible to use a manufacturing method such as the above-described sealing by the low pressure CVD method.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique which is highly practical as a technique for forming a cavity using electrochemical stop etching and for forming a closed structure in the cavity by film formation. It is an object of the present invention to provide a method for manufacturing a semiconductor pressure sensor that can be used.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor pressure sensor, comprising:
An impurity diffusion region of a conductivity type opposite to that of the surrounding conductivity type is formed in the surface layer portion of the single crystal silicon substrate on the (00) plane. And
<110> of a single crystal silicon substrate in the impurity diffusion region
A trench extending continuously or intermittently in the direction or <100> direction and penetrating the impurity diffusion region is formed. Further, while generating a potential difference between the impurity diffusion region and the surrounding region through a wiring electrically connected to at least one of the impurity diffusion region and the surrounding region on the surface of the single crystal silicon substrate,
The single crystal silicon substrate below the impurity diffusion region is etched by injecting the anisotropic etchant through the trench, and the etching is stopped at the interface of the impurity diffusion region, and the impurity diffusion region is connected to the diaphragm. To form a cavity. Then, after removing the wiring, a sealing film is formed to close the trench.

As described above, after removing the wiring,
Since the sealing film is formed to close the trench, problems due to wiring at the time of film formation can be avoided. Here, as described in claim 2, it is practically preferable that the wiring for the gauge arranged on the diaphragm is performed after the trench is closed.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor pressure sensor, the impurity diffusion region of the conductivity type opposite to the surrounding conductivity type is formed in the surface layer of the single crystal silicon substrate having the (100) plane orientation. To form The <110> direction or <10> direction of the single crystal silicon substrate is formed in the impurity diffusion region.
A trench extending continuously or intermittently in the 0> direction and penetrating the impurity diffusion region is formed. Further, the surface of the single crystal silicon substrate is electrically connected to at least one of the impurity diffusion region and its surrounding region, and the wiring is made of a metal having a melting point higher than the film forming temperature of the sealing film. While generating a potential difference between the impurity diffusion region and the surrounding region, the single crystal silicon substrate below the impurity diffusion region is etched by injecting an anisotropic etchant through the trench, and the impurity diffusion is performed. Etching is stopped at the interface between the regions to form a cavity having the impurity diffusion region as a diaphragm. Thereafter, a film for sealing is formed to close the trench.

As described above, electrochemical stop etching is performed using a metal having a melting point higher than the film forming temperature of the sealing film (high melting point metal) as a wiring, and thereafter, the sealing film is formed. Therefore, the problem caused by wiring at the time of film formation can be avoided.

Here, it is practically preferable that the film for sealing is formed by a low pressure CVD method.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a semiconductor pressure sensor according to the present embodiment, in which an upper side shows a plane and a lower side shows an A-A cross section thereof. More specifically,
This shows a state after dicing is performed on each chip from a wafer state. In addition, the upper plan view shows the trench etching mask 6 in the AA sectional view for easy understanding.
And a state where the sealing member 10 is removed.

On the silicon substrate 1, an N-type silicon substrate 3 is bonded via a buried oxide film (bonding oxide film) 2. This silicon substrate 3 is thinned to a thickness of about 15 μm to form an SOI layer. As the silicon substrate 3, a silicon substrate having a (100) plane orientation is used. In the center of the SOI layer 3, a double diffusion region of a deep P well region 4 and a shallow N well region 5 is formed in the surface layer. The planar shape of the double diffusion regions 4 and 5 is a quadrangle.

A trench etching mask 6 is formed on SOI layer 3, and trench etching mask 6 has a number of through holes 8. N-well region 5 in SOI layer 3
Is formed with a through hole 9 having the same shape and the same size as the through hole 8.
Cavity 7 is formed between N well region 5 and buried oxide film 2 in SOI layer 3. The cavity 7 is formed by anisotropic etching of silicon by introducing an etching solution through the through holes 8 and the through holes 9. More specifically, the cavity 7 is formed at the interface between the P well region 4 and the N well region 5. This is formed by so-called electrochemical stop etching for stopping the etching. One shape of the through hole 8 and the through hole 9 is a square shape, and the entire arrangement of each through hole 8 and the through hole 9 is as follows.
<110> direction or <100> of single crystal silicon substrate 3
> Are arranged side by side at predetermined intervals in the direction.

The cavity 7 has a rectangular shape in plan view, and has a vertical cross-section that is widest at a predetermined position in the depth direction and gradually narrows on the upper and lower sides. As described above, the cavity 7 has the upper surface formed at the PN interface, the lower surface formed by the buried oxide film 2, and the side wall 7a having the shape of a square.

A diaphragm 11 is formed in the N-well region 5 above the cavity 7. Further, the through hole 8 and the through hole 9 are closed by the sealing member 10, and the inside of the cavity 7 is evacuated. In this way, the inside of the cavity 7 becomes a vacuum chamber and serves as a reference pressure chamber in the absolute pressure sensor.

In the N-well region 5 constituting the diaphragm 11, four P-type impurity diffusion regions (piezoresistive elements) 12a, 12b, 12c and 12d as gauge resistors are formed. These four gauge resistors 12a to 12d
A Wheatstone bridge is configured.

In the sensor chip shown in FIG. 1, an integrated circuit portion 13 is formed on the outer peripheral side of the diaphragm 11, and the output signal of the Wheatstone bridge is amplified in the integrated circuit portion 13. Further, a large number of bonding pads 14 are provided in the peripheral portion of the sensor chip, and application of a predetermined potential, extraction of signals, and the like are performed by the pads 14.

Next, a method of manufacturing the semiconductor pressure sensor thus configured will be described with reference to FIGS. First, as shown in FIG. 2, the surface orientation of the surface is (1) on a silicon substrate 1 via a buried oxide film (bonded oxide film) 2.
The N-type single-crystal silicon substrate 3 of the (00) plane is bonded. Further, the silicon substrate 3 is thinned to a thickness of about 15 μm by polishing or the like. Then, the SOI layer 3 of this SOI wafer
On the other hand, a double diffusion region of P-well region 4 and N-well region 5 is formed in the surface layer. The P-well region 4 and the N-well region 5 are formed by using a general semiconductor manufacturing method such as photolithography, ion implantation, or diffusion.

Then, the gauge resistors 12a to 12d and the integrated circuit section 13 are applied to the SOI layer 3 of the SOI wafer.
(See FIG. 1) is formed by a general semiconductor manufacturing method.
However, the gauge resistors 12a to 12d and the integrated circuit unit 13
Is not performed here, but in a later step.

Subsequently, as shown in FIG.
, An oxide film 6 is formed as a trench etching mask, and a contact hole is formed at a necessary portion, and aluminum wirings 20 and 21 are patterned thereon. Aluminum interconnection 20 is electrically connected to N well region 5 and aluminum interconnection 21 is electrically connected to P well region 4. These aluminum wirings 20 and 21 are necessary for performing electrochemical stop etching from the surface in a later process. Thus, the aluminum wirings 20, 21
Thus, a voltage can be applied to each of the P well region 4 and the N well region 5.

Then, as shown in FIG.
A protective film 22 is formed on 0,21. This film 22
This is for protecting the aluminum wirings 20 and 21 from being etched when performing electrochemical stop etching from the surface in a later process. As the surface protection film 22, a SiN-based film or a SiO ₂ -based film is used.

Subsequently, as shown in FIG. 5, the oxide film (mask material) 6 and the protective film 22 are patterned by dry etching to form through holes (micro holes) 23.
Specifically, as shown in FIG. 11, the rectangular through holes 23 are arranged in an X shape (or a cross shape). That is, the through hole 23
In the <110> direction of the single crystal silicon substrate or <10>
They are arranged side by side at predetermined intervals in the 0> direction. The vertical and horizontal dimensions of the through holes (micro holes) 23 are about several μm.

Then, as shown in FIG. 6, the protective film 22 is patterned by using general photolithography and etched to form predetermined regions 24,
25 is opened. Accordingly, when performing electrochemical stop etching from the surface in the post-process, the opening 2
A voltage can be applied to the aluminum wirings 20, 21 exposed from the wirings 4, 25.

Further, as shown in FIG. 7, trench etching is performed on the SOI layer 3 to form a trench 26 reaching the buried oxide film 2. As the etching method, dry etching of general silicon is used. For example, as shown by a solid line in FIG. 12, RIE (reactive ion etching) in which the angle of the side wall is substantially perpendicular to the substrate surface is used.

As shown by a dashed line in FIG.
Etching or the like may be performed so that the trench sidewall has a forward taper. The trench 26 does not necessarily have to reach the buried oxide film 2. The reason why the trench 26 reaches the buried oxide film 2 is to maximize the interval between the adjacent trenches 26. This will be described later.

Subsequently, as shown in FIG. 8, the SOI layer 3 is immersed in a wet etching solution and
Is etched to form a cavity 7 serving as a reference pressure chamber.
In performing this etching, electrochemical stop etching is used. This means that a positive potential is applied to the N well region 5 and an arbitrary potential is applied to the P well region 4 (or floating). Thus, when the etching proceeds to the vicinity of the PN junction, an anodic oxide film is generated, and the etching is stopped. Using this electrochemical stop etching, the etching is stopped near the interface of the N-well region 5, whereby the diaphragm 11 composed of the N-well region 5 is formed.

Here, the reason that the vicinity of the interface between the N well regions 5 is described is that the two well regions 4 and 5 are formed at the PN junction between the N well region 5 and the P well region 4 in the method using the electrochemical stop etching. This is because the depletion layer is expanded and the etching is stopped, so that the portion of the P well region 4 where the depletion layer is expanded remains. The remaining amount varies depending on the well concentration and the voltage application condition, but is about 0.2 to 0.3 μm.

The side wall 7a of the cavity 7 is stopped at the (111) plane due to the anisotropic etching characteristic of silicon, and is formed in a "<" shape. In addition, since the bottom surface of the cavity 7 has the buried oxide film 2, the etching is stopped at the oxide film 2 and formed.

As an etchant, an alkaline etchant having selectivity with respect to the surface protective film 22 is used. Specifically, for example, KOH is used, or TMAH (tetramethylammonium hydroxide) or the like is used when there is a concern about contamination of a surface circuit or a manufacturing apparatus.

Subsequently, as shown in FIG. 9, the aluminum wires 20 and 21 for electrochemical stop etching are removed before vacuum sealing in a later step. Specifically, first, the surface protection film 22 is removed by dry etching, and then the aluminum wirings 20, 21 are removed by dry or wet etching.

Then, as shown in FIG.
A film which becomes 0 is formed by using a low pressure CVD method, patterning is performed, each trench 26 is closed, and vacuum sealing is performed.
Is the reference pressure chamber. Specifically, a polysilicon film, a SiO ₂ -based film, or the like is used as the sealing film 10. The deposition thickness of the sealing film 10 is more than half of the hole diameter of the trench 26. For example, if the hole diameter is 2 μm, the deposition thickness of the sealing film 10 is slightly more than 1 μm.
Further, by closing the trench 26 by using low pressure CVD excellent in embedding property, the sealing film 10 is formed on the inner wall surface of the cavity 7.
Adheres.

Thereafter, aluminum wires (not shown) for the gauge resistors 12a to 12d and the integrated circuit portion 13 are formed. Finally, a surface protection film (not shown) is formed. Thus, the sensor shown in FIG. 1 is manufactured.

In this way, a diaphragm having a high thickness accuracy by electrochemical stop etching is provided, and
The reference pressure chamber of the sensing part has a low pressure (L
P) Since vacuum sealing can be performed with a thin film using a CVD method, high reliability can be obtained.

Next, as shown in FIGS. 13 and 14, trenches 26 are formed in the silicon layers 4 and 3 under the N well region 5.
The advantage of forming the trench 26 will be described by comparing the manufacturing method of forming the trench 26 with the manufacturing method of not forming the trench 26 as shown in FIGS. here,
The drawing scale of FIGS. 13 and 14 is equal to the drawing scale of FIGS.

In FIG. 15, which is a comparative example, the N well region 5 of the SOI layer (bonded substrate) 3 is patterned, and as shown in FIG.
Layer 3 is etched. At this time, the interval W between the through holes 9 in the N-well region 5 is set to a predetermined value. In this case,
Etching stops in a state where the inverted quadrangular pyramid 17 composed of the (111) plane is formed. That is, the interval W between the through holes 9
Is simply the length a 'of a diagonal line of a rhombus formed at the corners of the rectangular through-hole 9 when only a mask pattern is used.
If the W value is not smaller than the above, the adjacent inverted quadrangular pyramid 17 does not connect and the etching does not proceed.

On the other hand, in FIG. 13, a trench 26 penetrating through the P well region 4 and reaching the buried oxide film 2 is formed. At this time, the interval W between the trenches 26 is set to a value equal to that of FIG. From this state, anisotropic etching of silicon is performed as shown in FIG. As the etching progresses, a rhombic cavity 16 is formed as a cross-sectional shape,
Adjacent rhombic cavities 16 communicate with each other at a predetermined depth. Thereafter, the etching is continuously performed, and the cavity 7 serving as the reference pressure chamber can be formed.

In this case, the depth of the trench 26 shown in FIG.
If the diameter and the interval of the trench 26 are referred to, assuming that the diameter of the trench 26 is “a”, the interval (pitch) of the trench 26 is “W”, and the depth of the trench 26 is “D”, W = a + 2D is satisfied. Then, as shown in FIG. 14, the distal ends of the rhombic cavities 16 can communicate with each other. For example, if D = 10 μm and a = 5 μm, W = 25 μm
m.

In other words, the method shown in FIG.
As can be seen from the comparative example shown in FIG. 11, the positions of the through holes 23 of the mask 6 in FIG. 11 are changed so that the inverted quadrangular pyramids 17 in FIG. Is determined, in the comparative example, the through hole 2
It is necessary to narrow the pitch W of No. 3 and the number of the through holes 23 for manufacturing a reference pressure chamber having the same area increases. On the other hand, by forming the trench of FIG. 13 as in the present embodiment, the number of the through holes 23 of the mask 6 for manufacturing the reference pressure chamber having the same area can be reduced.

Further, since the trench processing reaches the buried oxide film 2, the interval between the trenches 26 can be maximized, and as shown in FIG. 17, as shown in FIG. (31)
1) The angle of the surface is reduced, and the etching is finally stopped to form the above-described cavity (reference pressure chamber) 7.

If the semiconductor pressure sensor is manufactured as described above, the distance between the adjacent through holes 8 can be widened, and the sealing member 10 which adversely affects the sensing characteristics can be reduced. As a result, unstable elements of the sealing shape are reduced, and the sensing characteristics can be further improved.

In the above description, FIGS.
As shown in FIG. 1, the trenches (9, 23) are square in shape and are arranged side by side at predetermined intervals, but may be continuous. That is, the trench 26 in FIG. 7 is a trench that extends intermittently in the <110> direction or the <100> direction of the silicon substrate 3, but may be a trench 26 that extends continuously.

As described above, this embodiment has the following features. (A) As shown in FIG. 2, a double diffusion region of a deep P well region 4 and a shallow N well region 5 is formed in the surface layer of a single crystal silicon substrate 3 having a (100) plane orientation. Then, an N-well region 5 of a conductivity type opposite to the surrounding conductivity type is formed.
Then, as shown in FIG. 7, a trench 26 is formed in the N well region 5 continuously or intermittently in the <110> direction or <100> direction of the single crystal silicon substrate and penetrates the N well region 5. I do. Further, as shown in FIG. 8, on the surface of single crystal silicon substrate 3, aluminum wirings 20, 21 electrically connected to at least one of N well region 5 and P well region 4, which is the surrounding region.
The lower portion of the single crystal silicon substrate 3 below the N well region 5 is etched by injecting an anisotropic etchant through the trench 26 while generating a potential difference between the N well region 5 and the P well region 4 through the trench. At the same time, the etching is stopped at the interface of the N-well region 5 to form a cavity 7 having the N-well region 5 as a diaphragm. further,
After the aluminum wirings 20 and 21 are removed as shown in FIG. 9, a sealing film 10 is formed by a low-pressure CVD method to close the trench 26 as shown in FIG.

As described above, after the aluminum wirings 20 and 21 are removed, the sealing film 10 is formed and the trench 26 is formed.
Therefore, problems due to the aluminum wirings 20 and 21 at the time of film formation can be avoided. (B) Wiring for the gauges 12a to 12d arranged on the diaphragm is performed after the trench 26 is closed, which is practically preferable. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.

19 to 26 show the steps of manufacturing the semiconductor pressure sensor according to the present embodiment. This embodiment is an example of a manufacturing method in which a metal wiring for electrochemical stop etching is formed before closing a trench, and is not removed unlike the first embodiment.

The details will be described below. First, as shown in FIG. 19, a silicon substrate 3 is bonded on a silicon substrate 1 via an oxide film 2, and the silicon substrate 3 is thinned by polishing or the like. Then, a P-well region 4 and an N-well region 5 are formed in the surface layer of the SOI layer 3 of the SOI wafer. Then, the gauge resistors 12a to 12d and the integrated circuit unit 13 are formed.

Subsequently, as shown in FIG. 20, an oxide film 6 is formed on the SOI layer 3 and a contact hole is formed at a necessary portion, on which metal electrodes 30 and 31 for electrochemical stop etching are formed. Is patterned. At this time, the metal wiring 3 for electrochemical stop etching is used.
Aluminum is used for 0 and 31 in the first embodiment, but here, wiring made of a metal having a melting point higher than the deposition temperature (deposition temperature) of the sealing film 10 is used. Specifically, for example, various barrier metals used in general semiconductors,
For example, TiW or the like. As described above, by using a metal wiring having a melting point higher than the deposition temperature of the sealing film 10, it is not necessary to remove the wiring for performing the electrochemical stop etching as in the first embodiment.

Then, as shown in FIG. 21, a protective film 22 is formed on the high melting point metal wirings 30 and 31. Specifically, a SiN-based film or a SiO ₂ -based film is used as the protective film 22. Subsequently, as shown in FIG. 22, the mask material 6 and the protective film 22 are patterned by dry etching to form through holes 23. Then, as shown in FIG. 23, the protective film 22 is etched using general photolithography to open predetermined regions 24 and 25 in the protective film 22. Further, as shown in FIG.
Is etched to form a trench 26 reaching the buried oxide film 2.

After that, as shown in FIG. 25, the SOI layer
Is etched to form a cavity 7 serving as a reference pressure chamber.
At this time, electrochemical stop etching is used.
That is, by applying a positive potential to the N-well region 5 and an arbitrary potential to the P-well region 4 (or leaving it floating), the etching is stopped near the PN junction.

Subsequently, as shown in FIG. 26, a film serving as the sealing member 10 is formed by using a low-pressure CVD method, patterning is performed to close each trench 26, and vacuum sealing is performed.
Further, aluminum wires (not shown) for the gauge resistors 12a to 12d and the integrated circuit portion 13 are formed. Finally, a surface protection film (not shown) is formed.

When the semiconductor sensor is manufactured in this manner, the diaphragm 11 having a high-accuracy thickness by electrochemical stop etching is provided, and the cavity 7 serving as a reference pressure chamber is formed by a low pressure (LP) CVD having a good embedding property. Vacuum sealing is possible with a thin film using the method.

As described above, this embodiment has the following features. (A) As shown in FIG. 19, the plane orientation of the surface is (100)
Forming a double diffusion region of a deep P-well region 4 and a shallow N-well region 5 in the surface layer portion of the single-crystal silicon substrate 3 on the surface;
An N well region 5 of a conductivity type opposite to that of the surrounding conductivity type is formed. As shown in FIG. 24, the N-well region 5 extends continuously or intermittently in the <110> direction or the <100> direction of the single-crystal silicon substrate, and the N-well region 5
Is formed. Further, as shown in FIG. 25, on the surface of single crystal silicon substrate 3, at least one of N well region 5 and P well region 4 is electrically connected, and the temperature is lower than the film forming temperature of sealing film 10. The lower side of the N-well region 5 is injected by injecting an anisotropic etching solution through the trench 26 while generating a potential difference between the N-well region 5 and the P-well region 4 through the wirings 30 and 31 made of a metal having a high melting point. Is etched at the interface between the N-well region 5 and the cavity 7 having the N-well region 5 as a diaphragm is formed. Then, as shown in FIG. 26, the sealing film 10 is formed by the low pressure CVD method to close the trench 26.

Therefore, electrochemical stop etching is performed using a metal (melting point metal) having a melting point higher than the film forming temperature of the sealing film as the wirings 30 and 31, and thereafter, the sealing film 10 is formed. Since the film is formed to cover the trench 26, it is possible to avoid problems due to wiring at the time of film formation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor pressure sensor according to an embodiment.

FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 3 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 4 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 5 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 6 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 7 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 8 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 9 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 10 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 11 is a plan view showing a mask pattern.

FIG. 12 is a cross-sectional view for explaining a manufacturing process.

FIG. 13 is a cross-sectional view for explaining a manufacturing process.

FIG. 14 is an explanatory diagram for explaining a manufacturing process.

FIG. 15 is a cross-sectional view for explaining a manufacturing process in a comparative example.

FIG. 16 is an explanatory diagram for explaining a manufacturing process in a comparative example.

FIG. 17 is an explanatory diagram for explaining a manufacturing process.

FIG. 18 is an explanatory diagram for explaining a manufacturing process in a comparative example.

FIG. 19 is a sectional view for explaining a manufacturing process of the semiconductor pressure sensor according to the second embodiment.

FIG. 20 is a sectional view for explaining the manufacturing process of the semiconductor pressure sensor.

FIG. 21 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 22 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 23 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 24 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 25 is a sectional view for explaining the manufacturing process of the semiconductor pressure sensor.

FIG. 26 is a cross-sectional view for explaining a manufacturing process of the semiconductor pressure sensor.

FIG. 27 is a cross-sectional view for explaining a manufacturing process of a semiconductor pressure sensor according to the prior art.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Buried oxide film, 3 ... SOI layer, 4
... P well region, 5 ... N well region, 7 ... hollow, 9 ... through hole, 10 ... sealing member, 11 ... diaphragm, 12a-
12d: gauge resistance, 20: aluminum wiring, 21: aluminum wiring, 26: trench, 30: high melting point metal wiring, 31 ...
High melting point metal wiring.

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 2F055 AA40 BB20 CC02 DD05 EE14 FF49 GG01 4M112 AA01 BA01 CA03 CA05 CA16 DA03 DA04 DA12 EA03 FA11 5F043 AA02 DD16 FF01 FF02 FF07 FF10 GG02 GG05 GG06 GG10

Claims (4)

[Claims] 1. A step of forming an impurity diffusion region of a conductivity type opposite to a surrounding conductivity type in a surface layer portion of a single crystal silicon substrate having a surface orientation of a (100) plane; <110> of silicon substrate
Forming a trench extending continuously or intermittently in the direction or the <100> direction and penetrating the impurity diffusion region; and at least one of the impurity diffusion region and its peripheral region on the surface of the single crystal silicon substrate. An anisotropic etchant is injected through the trench to generate a potential difference between the impurity diffusion region and the surrounding region through a wiring electrically connected to one of the impurity diffusion regions, thereby forming a single region below the impurity diffusion region. Etching the crystalline silicon substrate and stopping the etching at the interface of the impurity diffusion region to form a cavity having the impurity diffusion region as a diaphragm; and forming a sealing film after removing the wiring. And clogging the trench. 2. The method according to claim 1, wherein the wiring for the gauge arranged on the diaphragm is performed after the trench is closed.
3. The method for manufacturing a semiconductor pressure sensor according to claim 1. 3. A step of forming an impurity diffusion region of a conductivity type opposite to a surrounding conductivity type in a surface layer portion of a single crystal silicon substrate having a surface orientation of a (100) plane; <110> of silicon substrate
Forming a trench extending continuously or intermittently in the direction or the <100> direction and penetrating the impurity diffusion region; and at least one of the impurity diffusion region and its peripheral region on the surface of the single crystal silicon substrate. While being electrically connected to one side, and passing through the trench while generating a potential difference between the impurity diffusion region and the surrounding region through a wiring made of metal having a melting point higher than the film forming temperature of the sealing film. The single crystal silicon substrate below the impurity diffusion region is etched by injecting an anisotropic etchant, and the etching is stopped at the interface of the impurity diffusion region to form a cavity having the impurity diffusion region as a diaphragm. And a step of forming a sealing film to close the trench. The method of production. 4. The method for manufacturing a semiconductor pressure sensor according to claim 1, wherein the film for sealing is formed by a low pressure CVD method.