JP2000049166A - Epitaxial wafer for heterojunction bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer for a heterojunction bipolar transistor, which has a high current gain and a less loss of a current extracted through a collector contact layer. SOLUTION: A Se planar doped layer 7 is provided at an interface between a collector contact layer 5 as an epitaxial layer and a semi-insulating GaAs wafer 6 for the growth of the epitaxial layer to decrease the electron trap level of the interface and to increase a collector current IB. Thereby the loss of a current extracted via the collector contact layer 5 can be made less, and a high current gain can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an epitaxial wafer for a heterojunction bipolar transistor.

[0002]

2. Description of the Related Art FIG. 5 is a sectional view of a conventional epitaxial wafer for a heterojunction bipolar transistor.

The epitaxial wafer shown in FIG.
This is an AlGaAs emitter epitaxial wafer for T (Heterojunction Bipolar Transistor, a high-speed transistor having a wide gap structure using a heterojunction).

This epitaxial wafer is formed by MOVPE (Metal Org) on a semi-insulating GaAs wafer 6 as a substrate.
An n-GaAs collector contact layer 5, an n-GaAs collector layer 4, and a p-layer are formed by a vapor phase growth method such as an anic vapor phase epitaxy (Morganic metal vapor phase epitaxy) method or an MBE (Molecular Beam Epitaxy) method. GaAs base layer 3, n-AlGaAs emitter layer 2, and n-InG
This is formed by laminating epitaxial layers of the aAs emitter contact layer 1.

[0005] The conductivity type of the collector layer 4, base layer 3 and emitter layer 2 of this type of epitaxial wafer is n-type.
There are two types, a pn type and a pnp type. Here, a case where npn type epitaxial layers are stacked will be described.

As an n-type dopant, Si is generally used, and as a p-type dopant, elements such as carbon, zinc, and beryllium are used. In the HBT, a collector electrode is formed on the collector contact layer 5. After the electrodes are formed, the emitter contact layer 1 is usually used without alloying (junction). Therefore, an InGaAs layer highly doped with Si, Se, or the like is generally used.

Here, the current gain showing the characteristics of the HBT is represented by the ratio of the collector current I _C to the base current I _B. Increasing the current gain reduces the concentration and thickness of the base layer,
This is possible by reducing the recombination of electrons in the base layer, but instead increases the base resistance and lowers the circuit cutoff frequency.

For this reason, with the structure of the determined base layer,
It is important how to reduce the base current or how to increase the collector current.

[0009]

Considering the high-frequency characteristics in the HBT [0008] In order to obtain a high current gain in the base structure which is determined either reduces the base current I _B, or necessary to increase the collector current I _C There is.

[0010] Conventionally, in order to reduce the base current I _B, the leakage current from the recombination current and the emitter electrode surrounding the reverse injection current and the base layer from the base layer is responsible for the base current I _B, the emitter layer Various studies have been conducted to reduce the recombination current at the interface between the substrate and the base layer.

However, most of them focus on the emitter layer, the base layer, and the emitter / base interface, reduce defects at the epi / sub interface, reduce electron traps due to the defects, and reduce the collector current I without loss. Consideration has not been given so much about taking out _C.

In an epitaxial wafer for a field effect transistor (FET) or a high mobility transistor (HEMT), a channel layer and a GaAs wafer are formed on a GaAs wafer on which an epitaxial layer is grown so as to avoid inheriting defects from the GaAs wafer. And a buffer layer is formed between them.

In an HBT epitaxial wafer, a collector contact layer 5 is epitaxially grown directly on a base epitaxial wafer to form an FET.
There was no equivalent to the buffer layer used in the HEMT. For this reason, there is a problem that the dangling bond of As on the GaAs wafer surface traps electrons and causes a reduction in the collector current I _C.

An object of the present invention is to solve the above-mentioned problems and to provide an epitaxial wafer for a hetero-junction bipolar transistor having a small current loss and a high current gain through a collector contact layer.

[0015]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention relates to a method for growing a collector contact layer comprising an epitaxial layer and growing the epitaxial layer in an epitaxial wafer for a heterojunction bipolar transistor obtained by a vapor phase epitaxial method. A planar dope layer of Se is provided at the epi / sub interface with the substrate to be formed.

In addition to the above configuration, the present invention may reduce the electron trap level at the epi / sub interface to obtain a high current gain.

According to the present invention, a planar doped layer of Se is provided at the epi / sub interface between the collector contact layer made of an epitaxial layer and the substrate on which the epitaxial layer is grown, so that the epi / sub interface is formed. Since the electron trap level decreases and the collector current increases,
Loss at the time of taking out current through the collector contact layer is reduced, and a high current gain can be obtained.

[0018]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a structural view showing an embodiment of an epitaxial wafer for a heterojunction bipolar transistor (hereinafter referred to as "HBT") according to the present invention. Note that the same members as those of the conventional example shown in FIG.

The epitaxial wafer for a heterojunction bipolar transistor is the same as the epitaxial / sub interface (n-GaAs collector contact layer 5 and the semi-insulating GaAs wafer 6 as a substrate) of the conventional HBT wafer shown in FIG. ) Is characterized by inserting a planar dope layer of Se.

The HBT epitaxial wafer has a structure in which a Se-doped layer 7 is inserted at the epi / sub interface, so that the influence of the crystallinity and the like of the wafer before the epitaxial layer is grown can be reduced by the n-GaAs collector contact layer. 5 and the n-GaAs collector layer 4 are prevented from being taken over, and have a role equivalent to a buffer layer used in an epitaxial wafer for FET or HEMT, thereby reducing the electron trap level at the epi / sub interface and increasing the collector current. The loss at the time of extraction is reduced, so that the collector current is efficiently extracted. Thereby, a high current gain can be obtained.

[0022]

The present invention will be described with reference to specific numerical values, but the present invention is not limited thereto.

FIG. 2 is a diagram comparing HBTs on a conventional epitaxial wafer for HBT and an epitaxial wafer for HBT of the present invention, and comparing the collector currents. The horizontal axis indicates the base-emitter voltage V _BE , The vertical axis indicates the collector current I _C. FIG. 3 is a diagram in which HBTs are manufactured on the conventional epitaxial wafer for HBT and the epitaxial wafer for HBT of the present invention, respectively, and the base current is compared. The horizontal axis indicates the base-emitter voltage V _BE , and the vertical axis indicates the vertical axis. shows a base current I _B.

FIG. 2 and FIG. 3 show that a planar doped layer of Se (doping concentration: 2 × 10 ¹² / cm ² )
An AlGaAs emitter epitaxial wafer for HBT inserted at the sub interface, a collector current I _C of an epitaxial wafer not inserted at the epi / sub interface, and a base current I _C
This is a comparison with _B.

When the base resistance is 250 ohm / sq. An HBT having an emitter size of 50 μm square is fabricated on an epitaxial wafer having a collector current I _C and a base current I _C.
B was measured and compared. It was confirmed that the collector current was clearly higher in the wafer in which the planar doped layer of Se was inserted at the epi / sub interface. The difference of the base current I _B in the most both contrast was observed.

FIG. 4 is a plot of the relationship between the concentration of the Se planar doped layer and the current gain. The horizontal axis represents the Se planar doped concentration and the vertical axis represents the current gain.

The current gain is the same as that of H used to make FIG.
Using a BT structure (base resistance: 250 ohm / sq., Emitter size: 50 μm square), comparison was made at a value when the current density of the emitter electrode was 1 kA / cm ² . The point where the planar doping concentration of Se is zero indicates the current gain of the conventional HBT epitaxial wafer.

It was confirmed that the current gain was improved by about 28% as compared with the conventional product even with a small amount of planar doping such as 3 × 10 ¹⁰ / cm ² . Even at a higher doping concentration, an improvement in current gain of about 30% was confirmed. This is considered because it can semi-insulating electron trap level of epi / sub interface by Se arrives at the dangling bonds on the GaAs substrate is reduced, taken out efficiently collector current I _C . Since this effect has been obtained even with a very small amount of planar doping, Se that reaches dangling bonds on a semi-insulating GaAs wafer
Is considered that one atomic layer is sufficient.

Next, the basis of the optimum condition will be described.

The effect was confirmed even with a very small amount of Se doping. From this result, it is considered that the effect of improving the current gain can be obtained only by performing planar doping of Se in order to reduce defects on the epi / sub interface.

The same effect can be expected even when the same element as that of S is planar-doped in addition to Se. Similar effects can be expected by inserting a buffer layer such as that used for an epitaxial wafer for FET or HEMT, for example, a super lattice structure of GaAs and AlGaAs under the collector contact layer.

As described above, according to the present invention, by forming a structure in which a Se-doped layer is inserted at the epi / sub interface of an epitaxial wafer for HBT, the electron trap level at the epi / sub interface is reduced and the collector current is reduced. Can be increased. As a result of the improvement, the current gain can be improved up to 33% as compared with the conventional epitaxial wafer for HBT.

[0033]

In summary, according to the present invention, the following excellent effects are exhibited.

It is possible to provide an epitaxial wafer for a hetero-junction bipolar transistor having a small loss at the time of taking out a current through the collector contact layer and having a high current gain.

[Brief description of the drawings]

FIG. 1 is a structural view showing an embodiment of an epitaxial wafer for a heterojunction bipolar transistor of the present invention.

FIG. 2 shows an HB on a conventional HBT epitaxial wafer and an HBT epitaxial wafer of the present invention.
FIG. 6 is a diagram in which T is manufactured and the collector current is compared.

FIG. 3 shows an HB on a conventional HBT epitaxial wafer and an HBT epitaxial wafer of the present invention.
FIG. 4 is a diagram in which T is manufactured and a base current is compared.

FIG. 4 is a diagram plotting the relationship between the concentration of a planar doped layer of Se and current gain.

FIG. 5 is a cross-sectional view of a conventional epitaxial wafer for a heterojunction bipolar transistor.

[Explanation of symbols]

1 n-InGaAs emitter contact layer (emitter contact layer) 2 n-AlGaAs emitter layer (emitter layer) 3 p-GaAs base layer (base layer) 4 n-GaAs collector layer (collector layer) 5 n-GaAs collector contact layer ( Collector contact layer) 6 Semi-insulating GaAs wafer 7 Planar doped layer

Claims (2)

[Claims] 1. An epitaxial wafer for a hetero-junction bipolar transistor obtained by a vapor phase epitaxial method, wherein an Se / planar interface is formed at an epi / sub interface between a collector contact layer composed of an epitaxial layer and a substrate on which the epitaxial layer is grown. An epitaxial wafer for a heterojunction bipolar transistor, comprising a doped layer. 2. An electron trap level at the epi / sub interface is reduced to obtain a high current gain.
3. The epitaxial wafer for a hetero-junction bipolar transistor according to item 1.