JP2000046918A - Semiconductor testing apparatus and semiconductor test method using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily shorten the execution time of a test program with a simple configuration, by a method wherein the test condition of a second test item onward is compared with the test condition of a previous test item, and only different test conditions are set at an input/output means. SOLUTION: By a test-condition setting means 20 in an apparatus 10, a test-program analytical part 3 analyzes a test program in every test process so as to obtain its analyzed result. A test-condition storage and control part 4 stores a test condition in a memory 2. Then, by a test-condition comparison and control part 5, the test condition of a second test item onward stored in the memory 2 is compared with the test condition of a previous test item, which is copied in another storage region inside the memory 2 by a test-condition copying and control part 6. As a result, a test-condition setting and control part 7 supplies only different test conditions to a hardware part 1 in a testing apparatus. Consequently, only a changd test condition is set at the hardware part 1, and a test setting instruction in the test program can be reduced sharply.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor test apparatus and a semiconductor test method using the same, and more particularly, to a semiconductor test apparatus having a test program including a test condition setting command for setting test conditions in hardware. And a semiconductor test method using the same.

[0002]

2. Description of the Related Art As the degree of integration of a semiconductor device increases, the circuit in a semiconductor chip becomes more and more complicated. As a result, an enormous amount of time is required for testing the semiconductor device. For this reason, efficient semiconductor testing is indispensable for shortening the TAT (Turn Arround Time), and is also important for reducing the cost of the entire product.

A test program for controlling a semiconductor test apparatus is classified into two functions in view of the description content.
One is a test program control instruction for interpreting a test program for executing a test for determining whether a device under test (Dice Under Test: hereinafter simply referred to as a DUT) is a non-defective product or a defective product for each test item. One is a hardware control instruction for controlling hardware in accordance with the content of the test. The hardware control instruction mainly includes a hardware condition setting instruction for setting test conditions such as control of a voltage applied to the DUT to hardware such as a test head and a test execution instruction for controlling a test execution procedure. is there.

Since most of the test time is the test program execution time, it is required to shorten the test program execution time in order to shorten the TAT. Although it is not possible to reduce the number of test execution instructions in a test program, it is possible to reduce the number of test condition setting instructions. Has been adopted.

FIG. 6 is a schematic diagram for explaining setting of test conditions according to a conventional technique. As shown in the figure, a test condition setting instruction and a test execution instruction are described in the test program 110 for each test procedure. The test condition is stored in the test condition storage memory 12 of the test apparatus for each test procedure.
0, each test condition is supplied to the hardware 1 of the test apparatus based on the test execution command, and the condition is sequentially set. As described above, in many test conditions set for each test procedure, there are many duplicate test conditions. Therefore, the execution time can be shortened by reducing the overlapping portion.

As a specific method for reducing the test condition setting instruction, when describing test conditions for each test item, a test engineer who creates a test program requires a test engineer who has the same test conditions as the test items in the previous procedure. By omitting the description and describing only the changed test conditions, the description of the test conditions is optimized. According to this method, the time for setting the test conditions in the test program can be minimized, thereby reducing the total execution time of the test program.

[0007]

However, in order to optimize the test condition description, the test engineer compares the test condition of the test item with the previous test condition while always grasping the test condition of the previous procedure. It was necessary to describe only the changed test conditions. This means that when the procedure of test items is diversified, such as in a test program whose execution procedure can be changed in a test program due to multi-branch, etc., comprehension of the test conditions before and after is complicated. Burden was imposed.

Further, an ASIC (Application Specific)
With the advancement of systematization of LSIs such as Integrated Circuit technology, existing CPU products and the like have been mounted as core components in semiconductor products. When developing test programs for these products, it is expected to shorten the development period by diverting the test programs of existing products. In this case, it is necessary to combine the existing test program with the test programs in other parts.

However, it is necessary to analyze the existing program for each test item to create the test condition while grasping the test conditions for each test item. This requires a great deal of time and effort. To provide customers with timely products, Q (Quic
k) This contributed to lowering the TAT.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor test apparatus and a semiconductor test apparatus using the same that can easily reduce the test program execution time with a simple configuration. It is to provide a method.

[0011]

The present invention solves the above problems by the following means. That is, the present invention (Claim 1)
According to the above, a test pattern signal generating means for generating a test pattern signal, input / output means for inputting the test pattern signal to a semiconductor device as a device under test and receiving a response signal output from the device under test, A pass / fail judgment unit for comparing the response signal with a predetermined expected value to judge pass / fail of the test; and a test condition setting unit for setting a test condition in the input / output unit corresponding to the test pattern. The condition setting means compares the test condition of the test item with the test condition of the previous test item for the second and subsequent test items, and sets only the different test conditions in the input / output means. You.

The semiconductor test apparatus according to the present invention includes a first storage area for storing the test condition of the test item, a second storage area for storing the test condition of the previous test item, and A storage unit having a third storage area for storing a condition, wherein the test condition setting unit adds a flag to the different test condition from the first storage area and stores the flag in the third area. Is preferred.

The test condition setting means may change the setting of the input / output means by extracting the different test conditions from the third storage area immediately before the execution instruction of the test.

The test condition setting means compares the test condition with the previous test condition for each test process, and stores the comparison result in the third storage area. The setting of the input / output means may be sequentially changed based on the different test conditions.

Further, it is more preferable that the test condition setting means instructs execution of the test and replaces the storage contents stored in the third area with the second storage area.

Further, according to the present invention (claim 6), a test pattern signal generating means for generating a test pattern signal, and the test pattern signal is input to a semiconductor device as a device under test, and Input / output means for receiving the output response signal, pass / fail determination means for comparing the response signal with a predetermined expected value to determine pass / fail of the test, and providing test conditions to the input / output means corresponding to the test pattern. A semiconductor test method using a semiconductor test apparatus having test condition setting means for setting, wherein an initial condition setting step for setting the input / output means based on test conditions corresponding to the first test pattern. For the second and subsequent test patterns, the test condition is compared with the previous test condition, and the setting of the input / output means is changed based on only different test conditions. The semiconductor test method and a test condition changing process of is provided.

Further, according to the present invention (claim 7), a test pattern signal generating means for generating a test pattern signal, and the test pattern signal is input to a semiconductor device as a device under test, and Input / output means for receiving the output response signal, pass / fail determination means for comparing the response signal with a predetermined expected value to determine pass / fail of the test, and testing conditions of the input / output means corresponding to the test pattern. And a storage means for storing a test program including a test condition setting instruction to be set. A semiconductor test method using a semiconductor test apparatus, wherein a first test pattern is input based on an initial condition corresponding thereto. An initial condition setting process for setting the output means and a test condition of the test pattern after the test is stored as a pre-test condition in the first area of the storage means. A pre-test condition storing process, a test condition storing process of storing the test condition in the second area of the storage means, a test condition comparing process of comparing the test condition with the pre-test condition, When a different test condition is obtained by the condition comparison process, a flag is stored in a third area of the storage means by adding a flag, and the different test condition is stored from the third area. A setting change process of extracting the conditions and changing the settings of the input / output means, a test execution process of instructing execution of the test, and a setting change of repeating the test execution process from the pre-test condition storage process to the end of the test. A semiconductor test method comprising an iterative process is provided.

In the test execution process, immediately after the execution of the test is instructed, the storage contents of the third area are extracted and stored in the first storage area, and the storage contents of the first storage area are rewritten. Preferably, a rewriting process is provided.

In the test condition comparison process, the pre-test condition and the test condition are compared for each step of the test condition, and the setting change process is performed each time the different test condition is obtained. May be extracted from the third area to change the setting of the input / output means.

The setting change step may be executed after the test condition comparison step is completed.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of the present invention will be described below with reference to the drawings. In the following drawings, the same portions are denoted by the same reference numerals, and description thereof will not be repeated.

In general, from the viewpoint of a database transfer method, a semiconductor test apparatus includes a batch transfer method in which data is temporarily stored in a memory and then transferred, and an optional transfer method in which the data is directly transferred to hardware without going through a memory. There are two classifications. Therefore, in the following description, a case where the present invention is applied to each method will be described as an embodiment.

First, a first example of the semiconductor test apparatus according to the present invention will be described.
An embodiment will be described with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to a batch transfer type semiconductor test apparatus.

FIG. 2 is a block diagram showing an outline of the semiconductor test apparatus 10 according to the present embodiment. As shown in FIG. 1, the semiconductor test apparatus 10 includes a test apparatus hardware 1 such as a test head and a test condition setting means 20 characteristic of the present invention.

The test condition setting means 20 includes a test program analysis section 3 for analyzing a test program for each test process, a memory 2 for storing test conditions in the test program, and an analysis result of the test program analysis section 3. A test condition storage control unit 4 for obtaining the test condition in the memory 2 and a test condition comparison control unit 5 for comparing the test condition of the test item with the test condition of the previous test item;
A test condition setting control unit 7 for supplying only different test conditions to the test apparatus hardware 1 by the test condition comparison control unit 5, and a test condition copy control unit 6 for copying the test conditions stored in the memory to another storage area. And

The test apparatus hardware 1 inputs a test signal generating means for generating a test signal, a test signal supplied from the test signal generating means to the DUT, and outputs the test signal from the DUT. A test head for receiving a response signal, pass / fail determination means for comparing the expected value corresponding to the test signal with the response signal, and a fail memory for storing the result as fail information when the response is failed. Have.

FIG. 3 shows a specific configuration of the test condition setting means 20. The test condition setting means 20 shown in FIG. 2 includes a memory 2A for storing the test condition in the test program in the test item, and a test condition copy for copying the test condition as a pre-test condition to the memory 2B at the same time as starting the test. The test condition and the previous test condition were compared with the device 16, and when there was a difference between the test condition and the previous test condition, a storage flag was given as the different test condition using the difference. A test condition comparison device 15 that outputs the same test conditions as above,
A memory 2C for storing the same test conditions and different test conditions output from the test condition comparison device 15;

The operation of the test condition setting means 20 is described as a first embodiment of the semiconductor test method according to the present invention in FIG.
This will be described with reference to the flowchart of FIG.

First, at the start of the test, the memory 2A,
2B is cleared and initialized (step S1)
00). Next, the test program analysis unit 3 interprets the first test item in the series of test programs (step S110). By this interpretation, a test condition setting instruction in the test program is received (step S13).
0), the test condition in the first test item is stored in the memory 2A (step S150).

For the first test, there is no test condition for the previous test to be compared (step S
160), all test conditions are set in hardware (step S180).

Next, upon receiving a test execution instruction in the test program (step S130), a test is performed for the first test item (step S200). Immediately after the execution of the test, the test conditions stored in the memory 2A are copied to the memory 2B by the test condition copying device 16 (Step S).
210), the contents stored in the memory 2A are cleared.

Next, a test condition setting command for the second test item is received (step S140), and the second test condition is stored in the memory 2A (step S15).
0) Then, the test condition comparison device 15 compares the test condition of the second test item stored in the memory 2A with the test condition of the first test item stored in the memory 2B (step S160), and compares the comparison result. It is stored in the memory 2C (step S170). The process from step 140 to step 180 is repeated until a test execution instruction comes (step S130).

In this embodiment, the memories 2A and 2B
And compares the stored contents in the address order, stores the comparison result in the memory 2C, and sets a storage flag for different test conditions.

FIG. 4 is a schematic diagram showing the relationship between the test conditions stored in these three memories. In the present embodiment, the memories 2A to 2C have the same configuration, and store test conditions corresponding to the positions of the tester pins of the test head.

In FIG. 3, since the storage flag (1) is set for the data stored at the addresses (001), (003), and (005) in the memory 2C, the test condition is the address (001). ), (00
It can be seen that items 3) and (005) are different from the previous test conditions.

Returning to FIG. 5, when the comparison of the test conditions is completed and a test execution instruction is issued (step S130), the test condition setting control unit 7 sets the storage flag of the test conditions stored in the memory 2C to “0”. Only the set test conditions are extracted and transferred to the hardware, whereby the settings of the test apparatus hardware 1 such as the test head are changed (step S180), and immediately after that, the test is executed (step S200).

After the test is executed, the test condition stored in the memory 2A is copied to the memory 2B by the test condition copying device 16 (step S210), and is stored as a pre-test condition.

The processes of steps S130 to S210 are repeated until the test program ends (step S120), and the operation of test condition setting means 20 ends when the test program ends.

Next, the second embodiment of the semiconductor test apparatus according to the present invention will be described.
An embodiment will be described with reference to the drawings. This embodiment is an embodiment in which the present invention is applied to an as-necessary transfer type semiconductor test apparatus.

The semiconductor test apparatus 10 shown in FIGS. 2 and 3
In comparison with the semiconductor test apparatus 30 of the present embodiment,
Its basic configuration is the same, and its operation is different.

FIG. 1 is a flowchart for explaining the operation of the semiconductor test apparatus 30 as a second embodiment of the semiconductor test method according to the present invention. As shown in steps S170 and S180 in the figure, the feature of this embodiment is that every time a different test condition is obtained by comparing the test conditions, this is transferred to the hardware of the test apparatus immediately. That is, since the hardware setting is changed each time a different test condition is found, the change of the hardware setting can be ended at the same time as the end of the test condition comparison process, and the test is immediately executed (step S20).
0). Further, since it is not necessary to store different test conditions in the memory 2C until the test condition comparison process is completed, the memory 2C has a small storage capacity.

[0042]

As described in detail above, the present invention has the following effects.

That is, according to the semiconductor test apparatus of the present invention, for the second and subsequent test items, the test condition of the test item is compared with the test condition of the previous test item, and only different test conditions are input / output. A test condition setting means for setting a test condition, a semiconductor device in which only changed test conditions are always set in hardware even for a test program having test items whose execution procedures are different from each other due to a condition branch or the like. A test device is provided. This allows
Since the number of test condition setting instructions in the test program can be significantly reduced, the test program execution time can be reduced accordingly. In addition, since an optimum test program execution time is obtained in this way, the test engineer can create a test program without considering individual program execution procedures. Thus, a semiconductor test apparatus having a high degree of freedom in programming can be provided.

Further, according to the semiconductor test method of the present invention, a test condition comparing step of comparing the test condition with the previous test condition is performed. A different test condition storing step of adding a flag to a third area of the storage means and storing the same, a setting change step of extracting the different test condition from the third area and changing the setting of the input / output means. Therefore, there is provided a semiconductor test method in which only changed test conditions are always set in hardware. Thus, it is possible to provide a semiconductor test method in which the test program execution time is reduced and the degree of freedom in programming is high.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a semiconductor test method according to a second embodiment of the present invention.

FIG. 2 is a block diagram showing an outline of a first embodiment of a semiconductor test apparatus according to the present invention.

FIG. 3 is a block diagram showing a specific configuration of a test condition setting means provided in the semiconductor test apparatus shown in FIG.

FIG. 4 is a schematic diagram showing a relationship between test conditions stored in three memories included in the test condition setting means shown in FIG.

FIG. 5 is a flowchart illustrating a first embodiment of a semiconductor test method according to the present invention.

FIG. 6 is a schematic diagram illustrating setting of test conditions according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test equipment hardware 2, 2A, 2B, 2C memory 3 Test program analysis part 4 Test condition storage control part 5 Test condition comparison control part 6 Test condition copy control part 7 Test condition setting control part 10 Semiconductor test equipment 15 Test condition comparison Apparatus 16 Test condition copy device 20 Test condition setting means

Continued on the front page F term (reference) 2G032 AA01 AA03 AA07 AC03 AD05 AE07 AE08 AE12 AG01 AG04 AG10 AH03 AH07 AK01 AK02 AK11 AK15 4M106 AA04 BA14 DH01 DH16 DJ21

Claims (10)

[Claims] A test pattern signal generating means for generating a test pattern signal; an input / output means for inputting the test pattern signal to a semiconductor device as a device under test and receiving a response signal output from the device under test; A pass / fail determination unit configured to compare the response signal with a predetermined expected value to determine pass / fail of a test; and a test condition setting unit configured to set a test condition in the input / output unit in accordance with the test pattern. A semiconductor test apparatus wherein the test condition setting means compares the test conditions of the second and subsequent test items with the test conditions of the previous test item and sets only different test conditions in the input / output means. 2. A first storage area for storing test conditions of the test item, a second storage area for storing test conditions of the previous test item, and a third storage area for storing the different test conditions. And a storage unit having a storage area, wherein the test condition setting unit adds a flag to the different test condition from the first storage area and stores the flag in the third area. 2. The semiconductor test apparatus according to 1. 3. The test condition setting means changes the setting of the input / output means by extracting the different test conditions from the third storage area immediately before the execution instruction of the test. 3. The semiconductor test apparatus according to 2. 4. The test condition setting means compares the test condition with the previous test condition for each test process, and stores the comparison result in the third storage area. 3. The semiconductor test apparatus according to claim 2, wherein the setting of the input / output unit is sequentially changed based on the different test conditions. 5. The test condition setting means instructs execution of the test and replaces the storage content stored in the third area with the second storage area and stores the replacement. Item 5. A semiconductor test apparatus according to any one of Items 2 to 4. 6. A test pattern signal generating means for generating a test pattern signal, and input / output means for inputting the test pattern signal to a semiconductor device as a device under test and receiving a response signal output from the device under test. A semiconductor comprising: pass / fail determination means for comparing the response signal with a predetermined expected value to determine pass / fail of a test; and test condition setting means for setting test conditions in the input / output means in accordance with the test pattern In a semiconductor test method using a test apparatus, an initial condition setting step of setting the input / output means based on a test condition corresponding to the first test pattern, and a second test pattern Comparing the test condition with the previous test condition, and changing the setting of the input / output means based on only different test conditions. Conductor test method. 7. A test pattern signal generating means for generating a test pattern signal, and input / output means for inputting the test pattern signal to a semiconductor device as a device under test and receiving a response signal output from the device under test. A test program including pass / fail determination means for comparing the response signal with a predetermined expected value to determine pass / fail of a test, and a test condition setting instruction for setting test conditions of the input / output means in accordance with the test pattern. A semiconductor test method using a semiconductor test apparatus having a storage means for storing, for an initial test pattern, an initial condition setting step of setting the input / output means based on an initial condition corresponding thereto. A pre-test condition storing step of storing the test condition of the test pattern for which the test has been completed as a pre-test condition in a first area of the storage means; A test condition storing step of storing a test condition in a second area of the storage unit; a test condition comparing step of comparing the test condition with the pre-test condition; A difference test condition storing step of adding a flag to a third area of the storage means and storing the same in a case where the difference test condition is obtained; A semiconductor test method comprising: a setting change step of changing a setting; a test execution step of instructing execution of the test; and a setting change repetition step of repeating the pre-test condition storage step to the test execution step until the end of the test. . 8. In the test execution step, immediately after instructing execution of the test, the storage contents of the third area are extracted and stored in the first storage area, and the storage contents of the first storage area are stored. 8. The semiconductor test method according to claim 7, further comprising a rewriting step of rewriting the data. 9. The test condition comparing step compares the pre-test condition and the test condition for each step of the test condition, and the setting change step includes a step of changing each time the different test condition is obtained. 9. The semiconductor test method according to claim 7, wherein the setting of the input / output means is changed by pulling out from the third area. 10. The semiconductor test method according to claim 7, wherein said setting change step is executed after completion of said test condition comparison step.