JP2000041143A - Image processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the image processing unit that attains overlap processing by having only to write a change point in the case of designating overlapping of a same area without complicated arithmetic operation. SOLUTION: The image processing unit is provided with functions such as a synthesizer 1, a gamma correction A2, a color processing 3, a color correction 4, a magnification 5, a filter 6, a gamma correction B7, a gradation processing 8, and an area designation 9 and with a CPU 10 that controls each function. Then a code of change points being a start point and an end point that are a couple of positive/negative change points of data is detected and a difference between produced code number of times of the positive and negative change point codes is detected and contents of image processing are selected depending on the difference between the change point codes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus for performing processing different from that of a specific area of a raster scanning type image signal.

[0002]

2. Description of the Related Art As an image processing apparatus for performing processing different from that of other areas on a specific area of a raster scanning type image signal, switching information corresponding to ON / OFF of processing is previously stored in a bit map memory. An image processing apparatus is known which has a configuration in which data in a bitmap memory is sequentially read out during image processing in accordance with the progress of raster scanning and used for on / off control of the processing (Japanese Patent Application Laid-Open No. 59-1984).
No. 45765). However, it is necessary to increase the bitmap memory in the depth direction in accordance with an increase in the type of image processing to be controlled, so a large-capacity memory is required,
There is a problem that switching control of a plurality of types of image processing cannot be substantially realized.

The image processing apparatus disclosed in Japanese Patent Application Laid-Open No. 5-167844 does not require a particularly large-capacity memory, and performs a bitmap-shaped image processing for switching a plurality of types of image processing for a non-rectangular area. The processing mode information having one or more bits as the first bit is stored in the memory, and the processing mode information is read from the bit map memory in synchronization with the progress of the raster scanning of the image information, and the image processing specified by the processing mode information is performed. It has processing means for applying to image information. Thus, switching of image processing can be controlled for a non-rectangular area, and switching of a plurality of types of image processing can be performed without particularly increasing the bitmap memory in the depth direction.

Japanese Patent Application Laid-Open No. 7-322052 discloses that when a process for coloring a closed region in a document image is performed, the color does not protrude from the closed region, and an uncolored region cannot be formed. Techniques for doing so are shown.

In Japanese Patent Publication No. 7-75392,
A technique has been proposed in which data indicating a closed area is enlarged in a direction in which white spots are generated, and the memory capacity for storing data indicating the closed area is saved.

[0006]

Problems to be Solved by the Invention
In the technology described in Japanese Patent Laid-Open No. 4 (1999) -1999, high-speed processing is performed by writing a change point in a bitmap. However, overlapping is possible in different areas, but overlapping of the same group requires some contrivance in data to be written. . Also, when writing one figure, even when there is an overlap, it is necessary to devise the data to be written, and it is not possible to simply write the contour (area) specified by the operator.

[0007] Japanese Patent Application Laid-Open No. Hei 7-322052,
In the technique described in JP-A-75392, the area to be filled is controlled by 0 and 1 on the bitmap. However, since the contour (area) specified by the operator is filled and then written in the bitmap, the calculation is performed. take time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus capable of achieving overlap processing by designating a change point without specifying complicated operations when designating overlap of the same area. is there.

[0009]

According to one aspect of the present invention, there is provided an image processing apparatus for writing image processing contents in a bit map memory corresponding to an image read by an image reading means. A change point code detecting means for detecting a code of a change point which is a start point and an end point which is a pair of a change point of data and a detection means for detecting a difference between the number of generated codes of the change point code plus and minus And image processing content switching means for switching the content of the image processing based on the difference between the change point codes.

[0010] In order to achieve the above object, a second aspect is provided.
According to the invention described in claim 1, in the invention according to claim 1, a change point code is provided with a code of processing content of one bit or more for switching processing content, and when processing conflicts, a processing code is output in a predetermined priority order. It is characterized by doing.

[0011] In order to achieve the above object, a third aspect of the present invention is provided.
According to the invention described in the first or second aspect, the start of the data change point is always in one direction of plus or minus.

According to another aspect of the present invention, the above object is achieved.
The invention described in the first or second aspect is characterized in that, at the start of a data change point, either the plus or the minus is detected first.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. When the image processing apparatus ISP of the present embodiment is applied to a digital copying machine, the digital copying machine has an image scanner SC as shown in FIG.
R, image processing device ISP, and printer PTR. The original image is read by an image scanner SCR and converted into R, G, B digital data, and these data are converted by an image processing apparatus ISP into color signals (Bk, Bk, B) suitable for forming a color image by a printer PTR. C, M, and Y color recording density signals).
The printer PTR is, for example, a laser printer.

Hereinafter, an image processing apparatus ISP according to an embodiment of the present invention will be described in detail. First, the image processing device IS
An outline of the functional configuration of P is shown in FIG. The outline of each function is as follows.

Synthesis 1: Input image data (scanner SCR
R, G, and B data) and the image data held by the area designation 9 are synthesized. Whether to combine or not is determined by the area signal.

Gamma correction A2: The level of the input image data is corrected in accordance with the image reading characteristics of the scanner SCR.

Color processing 3: A certain color or hue is converted into another color or hue, or a specific area is made the same color.

Color Correction 4: A one-dimensional masking equation:
R, G, and B are converted into Y, M, C, and Bk data. Here, the output selectively outputs one color among Y, M, C, and Bk sequentially.

Magnification 5: Magnification in the main scanning direction and movement in the main scanning direction are performed on image data and area signals.

Filter 6: Performs a smoothing process for smoothing a halftone image such as a printed matter (photograph) and a sharpening process for enhancing characters and the like.

Γ correction B7: Corrects the γ characteristic to match the image forming characteristics of the printer PTR. Gradation processing 8: Converts to gradation data suitable for the density expression characteristics of the printer PTR (dither method, density pattern method, etc.).

Area designation 9: Area processing data is stored in the bitmap memory, and an area signal for switching image processing is generated in accordance with the progress of raster scanning. The area signal of the area designation 9 is cascaded to each of the processing blocks 1 to 8, and the area signal and the image data are output in synchronization with each block. From the output of the γ correction B7, n-bit image data is input to the area designation 9.

CPU 10: Connected to all blocks 1 to 9, sets processing parameters, reads / writes memory in each block, and performs various operations. The area signal and the image data are output in synchronization with each block, so that the combination of the processing is not shifted. The image data is 16 dots / m in both the main and sub scanning directions.
m.

The area designation 9 is a part related to the gist of the present invention. FIG. 3 shows an outline of the configuration of the area designation 9. The area designation 9 includes an image memory 91 and a coordinate memory 92.

FIG. 4 shows the configuration of the image memory 91. FIG.
When the resolution is 16 dots / mm in both the main scanning direction and the sub-scanning direction, the memory 11 has 4,800 dots in the main scanning and 6,944 lines in the sub-scanning.
It has a larger size than paper. Further, it has an n-bit gradation in the search direction. That is, there are n bits per dot (pixel), and the data written to the memory 11 has an n-bit configuration. In the memory 11, input data is written to an input address by inputting data and an address to an input terminal in and an address terminal AD, respectively, at the time of writing. At the time of reading, by inputting the address to the address terminal AD, the data of the input address is read and output from the output terminal out.

The main scanning counter 12 counts addresses in the main scanning direction, is set to an initial value by a line synchronization signal, and counts up once per one pixel clock. The sub-scanning (y) counter 13 counts addresses in the sub-scanning direction, is set to an initial value by a copy start signal, and counts up once per line. Address combining 14 is 32M
In order to perform mapping up to bits, based on the count values of these counters 12 and 13, pixels from 0 to 4,799 in the main scanning direction are set as effective images, and pixels from 0 to 6,943 in the sub-scanning direction. Is synthesized with the address that sets the line as an effective image.

The input data selector 15 selects the data of the input terminal A in the copy mode, outputs the data to the memory 11 through the output terminal Y, and selects the data of the input terminal B during standby. The I / O buffer 16 outputs the input signal of the terminal I / O to the input terminal B of the input data selector 15 via the output terminal out when the CPU 10 writes.
At the time of reading, the data of the input terminal in (output data of the memory 11) is output to the CPU 10 via the terminal I / O.

The address selector 17 selects the input terminal A (the output address of the address combining unit 14) in the copy mode, and selects the address of the input terminal B from the CPU 10 in the standby mode, and outputs the selected address to the memory 11. As a result, a specific area of the output image data of the γ correction B7 can be read into the memory 11, the data in the memory 11 can be read, and the data can be transferred to the synthesizing unit 1; Read / write is also possible, by reading the image data in the memory 11,
By processing it, data processing to be written to the memory 11 can be performed.

FIG. 5 shows the configuration of the coordinate memory 92 shown in FIG. The coordinate memory 92 includes a memory control 20, an area code extraction 30, and an image composition group 60. The memory control 20 is almost the same as the image memory 91 shown in FIG. 4, and the different points are as follows.

That is, the capacity of the memory 21 is 2,400 dots in the main scanning × 3,742 lines in the sub-scanning. When the resolution is 8 dots / mm, the memory 21 has a larger size than A3 and DLT paper. , Two bitmaps (21A, 21B). Assuming that the first sheet is the first memory 21A and the second sheet is the second memory 21B, data S1 and S2 of the same address are simultaneously stored in the first memory 21A.
And from the second memory 21B.

The main scanning counter 22 counts addresses in the main scanning direction, is set to an initial value by a line synchronization signal, and counts up once every two pixel clocks. The sub-scanning (y) counter 23 counts addresses in the sub-scanning direction, is set to an initial value by a copy start signal, and counts up m times for n lines. Although n and m vary depending on the magnification of the sub-scanning, the same magnification is n = 2 and m = 1. Memory 2
1 is 2,400 dots x 3,742 lines (one sheet)
Two sheets (S1 and S2) are output in the section.

Data S1, S written to memory 21
FIG. 6 shows the configuration of two bits. The sixth digit “1” bit is a change point bit, the fifth digit bit is a U / D flag,
The four digit bits of 0 to 0 are the area code indicating the area number.

SP of area code extraction 30 shown in FIG.
The (serial-parallel) converter 31 converts the serial data S
1 is converted into 6-bit parallel data PD10 to PD15 in synchronization with CLOCK (not shown). The change point detection (1) 32 is a circuit that detects a change point bit of the above-described 6-bit length code based on the parallel data PD15. When the change point bit is detected, the change point detection (1) 32 outputs an EN1 signal and outputs a U / D flag. Is output. At the same time, control is performed so that the EN1 signal is not generated for five clocks (the question where the area code is written).

As shown in FIG. 10, the decoder (1) 33 is a circuit for decoding 4-bit input data into 16 lines (the TTL LS 138 is expanded to 16 bits). Similarly, the SP conversion (2) 34, the conversion point detection (2) 35, and the decoder (2) 36 perform the same operation for the data S2.

Areas 0 to 15 are 3-bit up / down counters 37 to 52, where the EN1 signal is H and
When the output of the decoder (1) 33 is L (selected), or when the EN2 signal is H and the output of the decoder (2) is L (selected), the counter data is updated. .

When the U / D flag is 1, the counter is incremented (+1), and when the U / D flag is 0, the counter is decreased (-1). Here, when the count value of the up / down counter is 7 and the U / D flag is 1, an overflow occurs and the value becomes 0. When the count value of the up / down counter is 0 and the U / D flag is 0, an underflow occurs and the value becomes 7. The output of each area is L when the count value is 0, and H when the count value is not 0. Also,
The up / down counters 37 to 52 return to an arbitrary initial value (0) by the line synchronization signal.

As shown in FIG. 11, the priority order circuit 53 converts H at the inputs x15 to x0 into a 4-bit area number (area code). That is, x15 →
x14 → x13 →... → x2 → x1 are examined in this order, and a code representing the first place where H exists is generated.

The memory 21 shown in FIG. 5 has bitmap memories 21A + 21B corresponding to two originals, and the data S1 of the same address from each of the memories 21A and 21B is synchronized with the progress of the raster scanning of the image information. , S2
As described above, the data S1 is supplied to the change point detection circuit 32 and the decoder 33, and the data S2 is supplied to the conversion point detection circuit 35 and the decoder 36 in a bit serial manner.

In one bit map (conventional technology: for example, the above-mentioned Japanese Patent Application Laid-Open No. 5-167844), considering the minimum unit of area designation, the end of the area is indicated following the last bit of the area code indicating the area start. Even when an area code is written (it is impossible to write an area code overlaid because there is only one bit map), at least a length corresponding to the area code indicating the end of the area is required. Therefore, the minimum unit for area designation is several bits for the area code.

As described above, the present invention is characterized in that it has at least two bitmap memories and performs parallel processing. With this configuration, unlike the related art, the area code indicating the end of the area can be written at a position overlapping the area code indicating the start of the area (meaning that the corresponding position on the document overlaps). By writing the area code indicating the end of the area by shifting the area code indicating the start of the area by one bit, an area of one pixel can be specified as the minimum unit for specifying the area.

FIGS. 7 to 9 are time charts showing signal changes at various parts of the area code extraction 92. FIG.

1) In the initial state (left end in FIG. 7), area 0
Is fixed at H and the other is fixed at L. When the area code 2 and the U / D signal 1 are detected next time, the count value of area 2 becomes 1, the output signal of area 2 becomes H, and the area number Becomes 2.

2) When the area code 3 and the U / D signal 1 are detected, the count value of the area 3 becomes 1, the output signal of the area 3 becomes H, and the area number becomes 3.

3) When the area code 3 and the U / D signal 0 are detected, the count value of the area 3 becomes 0, the output signal of the area 3 becomes L, and the area number becomes 2.

4) When the area code 2 and the U / D signal 1 are detected, the count value of the area 2 becomes 2, the output signal of the area 2 becomes H, and the area number becomes 2.

5) When the area code 15 and the U / D signal 1 are detected, the count value of the area 15 becomes 1, the output signal of the area 15 becomes H, and the area number becomes 15.

6) When the area code 2 and the U / D signal 0 are detected, the count value of the area 2 becomes 1, the output signal of the area 2 becomes H, and the area number becomes 15.

7) When the area code 15 and the U / D signal 0 are detected, the count value of the area 15 becomes 0, the output signal of the area 15 becomes L, and the area number becomes 2.

8) When the area code 2 and the U / D signal 0 are detected, the count value of the area 2 becomes 0, the output signal of the area 2 becomes L, and the area number becomes 0.

That is, when the area 2 and the area 3 are overlapped by the user's area designation, the larger area number (area 3) is selected. Area 2
The area number having the largest number is selected not only when the area and the area 3 overlap but also when a plurality of areas overlap.

Here, the fact that the minimum unit for specifying an area is one pixel will be specifically described with reference to FIGS. Focusing on area code 3, an area code indicating the start of the area is read from S1 (the second line from the top).
Also, an area code indicating the end of the area is read from S2 (the ninth example). At this time, the area code of S1 and S
Since the area code of area 2 is read out by shifting by one bit, the output of area 3 is output only in the area of 1 bit (19th), and the area signal of area 3 has a 1-bit width (25th area). ).

The image composition 60 shown in FIG.
One bit of image data is combined with an area number. When the image data is H at the area number 15, the area number 15 is output as it is, and when the image data is L, the area number is forcibly set to 0. When the area number is other than 15, the area number is output as it is. As a result, the area surrounded by the area number 15 becomes the area signal 15 only when the image data is H. For example, if the processing for making the area signal 15 paint (the same color) is performed, 1
It becomes possible to combine bits of an image. Here, the area number 15 has been described, but the area number may be any number or a plurality. Further, the area number when the image data is H and the area number when the image data is L may be any number.

In the present embodiment, the image data is one bit. However, the multi-valued image is subjected to complex conversion into an area code. If you paint, multi-value synthesis becomes possible. The movement at the time of combining can be performed by read / write and address control of the memory 11.

Next, an actual operation flow will be described with reference to FIG. Here, the document 1, the document 2, and the document 3 are used for image processing, the document 2 and the document 3 are combined with the document 1, and the document 1 is subjected to a process of filling a closed loop. In this case, the operator first specifies an image cutout area of the original 2 and the original 3 and a filled area of the original 1.

Next, the original 2 is placed at the original reference position, and the cutout area (specified range) is read in the image memory 11. Then, the document 3 is placed at the document reference position, and the cutout area (specified range) is read in the image memory 11. From the above,
As shown in FIG. 12D, an image is taken into the image memory 11.

Next, the original 1 is placed at the original reference position, and an image outside the image area (specified range) of the originals 2 and 3 is read into the image memory 11. As a result, the original 1 is stored in the image memory 11 as shown in FIG.
-3 images are synthesized.

When reading of the originals 1 to 3 is completed, the CPU
10 detects a closed loop area (filled area) of the image memory 11 and writes the closed loop area in the coordinate memory 21. Here, since the resolution of the coordinate memory 21 and the resolution of the image memory 11 are different, for example, when there is a closed area as shown in FIG. 13, the resolution is converted so as to overlap the boundary of the closed area as shown in FIG. Write. The reason for specifying the overlap is to prevent the vicinity of the boundary of the closed figure from being processed and making the figure unsightly.

An area number corresponding to the image memory 11 is written in the coordinate memory 21. Subsequently, the original is read, and a portion to be combined is combined in combination 1, the inside of the closed loop is filled, and the final result shown in (f) of FIG. 12 is output.

Further, the designation of the area overlap will be described. This will be described with reference to FIG. At this time, when the writing order of the operator is a Chinese numeral, the U / D signal is set to-when moving down, and + when moving up. The U / D flag is + at the change point of P1 (the hatched square change point), and the U / D flag is-at the change point of P2 (scattered square change point). The arithmetic numbers inside these squares indicate the count values of the areas. In other words, the intersection processing of the closed figure can be performed by simply writing the contour.

FIG. 16 shows a modification of this case where the U / D flag comes first. FIG. 17 is an enclosed image diagram when rectangular coordinates of the same area are designated. In the case of the same area where rectangles overlap as shown in FIG. 17, it is necessary to write as shown in FIG. Calculation time is also required.

The present invention can be easily performed without considering the overlap as shown in FIG. The change point of P1 (a square change point formed by a dotted line) has a U / D flag of +, and the change point of P2 (a square change point of a solid line) has a U / D flag of-. The arithmetic numerals inside these squares indicate the count value of the area. In other words, the intersection processing of the closed figure can be performed by simply writing the contour. In the case of a polygon having no intersection, the management of the U / D flag can be easily controlled by simply fixing the contour tracing direction clockwise or counterclockwise. The U / D flag is simply a start point and an end point.

FIG. 19 shows an example in which two rectangles overlap different areas. The change point of P1 is when the U / D flag is + and P
The U / D flag of the change point 2 (the change point of the hatched square) is-. In the hatched square, an encircling line indicated by a solid line and a change point in a portion not indicated by the solid line mean different areas. The first numeral of the arithmetic numeral is the count value of the change point area of the encircling line indicated by the solid line, and the subsequent numeral is the count value of the change point area of the portion where the enclosing line is not indicated. Regarding this, Japanese Patent Laid-Open No. 5-1
This has the same effect as that of JP-A-67844 and JP-A-8-79544. Although the code data is written on the one-dimensional bitmap, it goes without saying that writing in the depth direction is also effective. Furthermore, in this embodiment, the area counter is described as having three bits, but any number of bits may be used.

[0063]

According to the first and third aspects of the present invention, it is possible to easily perform a process of switching a plurality of overlaps in the same area by using a plus and minus change point code.

According to the second aspect of the invention, in addition to the above-described effects, by adding a plurality of processing codes to the change point code, it is possible to easily perform the overlapping processing of different areas.

According to the fourth aspect of the present invention, the overlap of one figure can be easily processed by permitting the start of the plus and minus change points from any of them.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a copying machine using an image processing apparatus ISP of the present invention.

FIG. 2 is a block diagram illustrating a functional configuration of an image processing apparatus ISP according to an embodiment of the present invention.

FIG. 3 is a block diagram showing contents of an area designation 9 shown in FIG. 2;

FIG. 4 is a block diagram showing contents of an image memory 91 shown in FIG. 3;

FIG. 5 is a block diagram showing the contents of a coordinate memory 92 shown in FIG. 3;

6 is a table showing a bit configuration of area codes S1 and S2 shown in FIG.

7 is a time chart (No. 1) showing control signals in a coordinate memory 92 shown in FIG.

8 is a time chart (No. 2) showing control signals in the coordinate memory 92 shown in FIG.

9 is a time chart (No. 3) showing control signals in the coordinate memory 92 shown in FIG.

FIG. 10 shows a decoder 33 of the coordinate memory 92 shown in FIG.
36 is a table showing the relationship between the input and the output of No. 36.

11 is a diagram showing a priority finger 53 of the Zaharu memory 92 shown in FIG. 5;
4 is a table showing the relationship between the input and output of FIG.

FIG. 12 is a plan view illustrating a relationship between a document and a processing output in an example of image information processing by the image processing apparatus ISP illustrated in FIG. 2;

13 is a plan view showing an example of a closed area where the CPU 10 shown in FIG. 2 performs image processing.

14 is a plan view showing an area for which resolution is converted when the CPU 10 shown in FIG. 2 processes the closed area shown in FIG.

FIG. 15 is a diagram illustrating an example of overlapping areas.

FIG. 16 is a diagram showing a modification of FIG.

FIG. 17 is a diagram showing the same area where rectangles overlap;

FIG. 18 is a diagram for explaining the processing of the present invention.

FIG. 19 is a diagram illustrating an example of overlapping of areas where two rectangles are different.

FIG. 20 is a diagram for explaining conventional processing.

[Explanation of symbols]

 Reference Signs List 1 synthesis 2 γ correction A 3 color processing 4 color correction 5 scaling 6 filter 7 γ correction B 8 gradation processing 9 area designation 10 CPU

Claims (4)

[Claims] 1. An image processing apparatus for writing the contents of image processing into a bit map memory corresponding to an image read by an image reading means. Change point code detection means for detecting the code of the change code, detection means for detecting the difference between the number of occurrences of plus and minus codes of the change point code, and image processing content switching means for switching the content of the image processing based on the difference between the change point codes An image processing apparatus, comprising: 2. The method according to claim 1, wherein the change point code includes a code of processing content of one bit or more for switching processing content, and when the processing conflicts, the processing code is output in a predetermined priority order. An image processing apparatus characterized by the above-mentioned. 3. The image processing apparatus according to claim 1, wherein the start of the data change point is always in one direction of plus or minus. 4. The image processing apparatus according to claim 1, wherein the start of the data change point is detected in either plus or minus.