JP2000039926A - Current outputting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce current variation, power consumption, and mounting area by connecting plural current sample/hold circuits with a constant current circuit, operating the sample/hold of the currents of the constant current circuit, and outputting currents which are almost the same as the currents of the constant current circuit. SOLUTION: Plural current sample/hold circuits 2-1-2-n are connected with a constant current circuit 1, and each switch element of those current sample/ hold circuits 2-1-2-n is controlled so as to be successively turned on in each prescribed time, and reference currents Iref of the constant current circuit 1 are successively sampled. Then, when the reference currents Iref are sampled, the reference currents Iref are held by a current transforming operation, and output currents Iout1, Iout2-IoutN are supplied from each current sample/hold circuit 2-1-2-n to circuits C1-CN of a load.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current output circuit for outputting a plurality of currents identical to an input current.

[0002]

2. Description of the Related Art Conventionally, as such a current output circuit, for example, a method using a reference voltage circuit and a voltage-current conversion circuit, and a method using a reference current circuit and a current mirror circuit are known. FIG. 5 is a circuit diagram showing an example of a current output circuit using a reference voltage circuit and a voltage-current conversion circuit. In the figure, reference numeral 19 denotes a reference voltage circuit for outputting a reference voltage Vref;
20-n are voltage-current conversion circuits connected to the reference voltage circuit 19. The reference voltage Vref of the reference voltage circuit 19 is converted into constant currents by voltage-current conversion circuits 20-1 to 20-n, respectively, and output currents Iout1 to IoutN
Are supplied to the load circuits C1 to CN, respectively.

The voltage-current conversion circuit comprises, for example, an operational amplifier 21, an NPN transistor 22, and a resistor 23 as shown in FIG. 6, and a reference voltage Vref is inputted to a positive input terminal of the operational amplifier 21, and a negative input is provided. The voltage at the connection point between the emitter terminal of the transistor 22 and the resistor 23 is input to the terminal. In such a circuit, control is performed so that the voltage at the negative input terminal of the operational amplifier 21 is substantially equal to the reference voltage Vref at the positive input terminal. Therefore, the voltage across the resistor 23 is held at the reference voltage Vref. 23, a constant output current flows. For example, assuming that the resistance value of the resistor 23 is R1, a current of Iout = (Vref / R1) flows through the resistor 23 (provided that β of the transistor 22 is infinite), and this current reduces the reference voltage Vref. It is obtained as a constant output current converted to a current.

FIG. 7 is a circuit diagram showing an example of a current output circuit using a reference current circuit and a current mirror circuit.
In the circuit of FIG. 7, the current Iref of the reference current circuit 3 is configured to flow through one of the plurality of transistors of the current mirror circuit 24, and the currents of the other transistors of the current mirror circuit 24 are controlled by the load circuits C1 to C1. It is supplied to the circuit CN. In the current mirror circuit 24, since the same current Iref flows in every transistor, a plurality of identical currents are obtained, and the output current Iou is supplied to the circuits 1 to N.
It is supplied as t1 to IoutN.

[0005]

However, the conventional current output circuit of FIG. 5 has the following problems. If the resistance value of the resistor 23 of the voltage-current conversion circuit in FIG. 6 is not uniform, the output current value varies, and accordingly, if uniformity is required for the output current, appropriate resistance accuracy is required. In particular, in the case where integration is performed on a semiconductor substrate, an attempt to increase the resistance accuracy by using laser trimming or the like increases the manufacturing cost. Also, if an external resistor is used,
Since pins for connecting multiple resistors are required,
Again, the cost of the IC increases. The voltage drop due to the wiring resistance between the reference voltage circuit 19 and each voltage-to-current conversion circuit causes a difference in the reference voltage input to each voltage-to-current conversion circuit, and this voltage difference causes the output current to vary. Since a voltage-current conversion circuit is required in accordance with the number of output currents, the circuit scale is increased, and the power consumption is accordingly increased. If there is a temperature difference at the location of each voltage-current conversion circuit,
Since the resistance value changes depending on the inherent temperature coefficient of the resistor 23, the output current values vary.

Further, in the current output circuit of FIG. 7, since the current is used as a reference, it is not necessary to convert the voltage into the current.
Although the effects of voltage drop and temperature due to the wiring resistance as described above are reduced, there are the following problems. In order to obtain a plurality of output currents with high accuracy, it is necessary to arrange the current mirror circuit 24 in one place. For this purpose, an area required for routing the wiring of the output current to the circuit at the next stage is required. Therefore, a large wiring area is required on the substrate on which the circuit is mounted. If an attempt is made to obtain a large number of output currents, the size of the current mirror circuit is correspondingly increased, so that the distance between the transistors constituting the current mirror circuit is increased. For example, when the number of transistors in the current mirror circuit is increased to about 100, the distance from the reference transistor located at the left end to the 100th transistor located at the right end of the circuit in FIG. 7 is increased. Therefore, non-uniformity occurs in the current amplification factor and the like of each transistor constituting the current mirror circuit, and this causes variations in the output current.

The present invention has been made in view of the above-mentioned conventional problems, and has a simple circuit scale, small current variation,
It is an object of the present invention to provide a current output circuit with low power consumption and small mounting area.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a constant current circuit for outputting a predetermined current, and a constant current circuit connected to the constant current circuit and sampling / holding the current of the constant current circuit. This is achieved by a current output circuit including a plurality of current sample / hold circuits that output substantially the same current as the circuit current.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first embodiment of the current output circuit of the present invention. In FIG. 1, reference numeral 1 denotes a constant current circuit for outputting a constant reference current Iref, and 2-1 to 2-2,..., 2-n denote a plurality of current sample / hold circuits connected to the constant current circuit 1. is there. Each current sample / hold circuit samples and holds the reference current Iref of the constant current circuit 1 to supply currents Iout1 to IoutN to the circuits C1 to CN of the respective loads. Vdd is a power supply voltage.

FIG. 2A is a circuit diagram showing an example of a current sample / hold circuit. In the circuit shown in FIG. 2A, a current transformer circuit is used as a current sample / hold circuit, and is composed of a pair of NMOS transistors 4, 5, a capacitor 6, and switch elements SW1, SW2. Vss is a reference voltage.

FIG. 2B shows the operation timing of the switch elements SW1 and SW2 in the circuit of FIG. 2A. The switch elements SW1 and SW2 are driven by pulse signals from a timing control unit (not shown) so as to be simultaneously turned on as shown in FIG.
The current is sampled while W1 and SW2 are on. That is, when the switch elements SW1 and SW2 are turned on,
The reference current Iref of the constant current circuit 1 flows through the NMOS transistor 4, and at this time, the same current flows through the other NMOS transistor 5 due to the mirror operation.
ref can be sampled.

Next, when the switch elements SW1 and SW2 are turned off, the NMOS transistor 4 is turned off. However, since the gate potential of the other NMOS transistor 5 is held by the capacitor 6, the NMOS transistor 5 keeps on and the reference current Iref Is held. Here, FIG.
, A plurality of current sample / hold circuits 2-1, 2-2,..., 2-n switch elements SW1,
SW2 is controlled so as to be sequentially turned on for a predetermined time as shown in FIG. 2B, and sequentially samples the reference current Iref of the constant current circuit 1. When the current is sampled, the reference current Iref is held by the current transformer operation, and the current sample / hold circuits 2-1, 2-2,.
The output currents Iout1, Iout2,..., IoutN are supplied to the load circuits C1, C2,.

The current sample / hold circuit 2-
1, 2-2,..., 2-n are the reference currents I in order as described above.
When ref is sampled and the sampling of the current of the last current sample / hold circuit 2-n is completed, the reference current Iref is sampled sequentially from the first current sample / hold circuit 2-1. As described above, the current sample / hold circuits 2-1, 2-2,.
A constant current is supplied to the load circuits C1 to CN by sampling and holding ref. Note that the capacitance value of the capacitor 6 may be set according to a required hold time, and a parasitic capacitance such as a gate capacitance of an NMOS transistor can be used as the capacitor 6 depending on the hold time. Further, ON / OFF of the switch elements SW1, 2 is not necessarily the same. It may be shifted to reduce clock feedthrough.

FIG. 3A is a circuit diagram showing another example of the current sample / hold circuit. In the circuit of FIG.
A bias current circuit 7 for outputting a bias current Ibias using another type of current transformer circuit, an NMOS
Transistor 8, capacitor 9, switch elements SW3 to SW5
It is composed of The operation of the switch elements SW3 to SW5 is controlled by a pulse signal from a timing control circuit (not shown) as in FIG. Vss is a reference voltage.

FIG. 3B shows the operation timing of the switch elements SW3 to SW5 in the circuit of FIG. First, the switching elements SW3 and SW5 are shown in FIG.
As shown in (b), the NMOS transistor 4 is driven to be turned on simultaneously and the NMOS transistor 4 to be turned off by a pulse signal from the timing control circuit. This switch element SW3, SW
The period during which the switch 5 is turned on for a certain period and the switch element SW4 is turned off is a sampling period for sampling current. In this sample period, since the switch elements SW3 and SW5 are turned on, the NMOS transistor 8 is turned on, and this N
The reference current Ire of the constant current circuit 1 is
A current (Iref + Ibias) of the sum of f and the bias current Ibias from the bias current circuit 7 flows, and the gate potential of the NMOS transistor 8 is fixed.

Next, as shown in FIG. 3B, when the switch elements SW3 and SW5 are turned off and the switch element SW4 is turned on, the gate potential of the NMOS transistor 8 is changed by the capacitor 9 provided between the NMOS transistor 8 and the reference voltage Vss. Therefore, the current (Iref + Ibias) is held. In this hold state, the bias current Ibias is supplied from the bias current circuit 7, the reference current Iref is held by the current transformer operation, and the switch S
A current equal to the reference current Iref is supplied to the load circuit via W4. In the case of the circuit of FIG. 3A, similarly to the circuit of FIG. 2A, the current sample / hold circuits 2-1 and 2-
2,..., 2-n supply a current to a load circuit by sampling and holding the current at a constant cycle. The capacitor 9 is an NMOS as in the case of FIG.
A parasitic capacitance such as a gate capacitance of a transistor can be used. Also, ON / OFF of the switch elements 3, 4, 5
Are not necessarily the same. It may be shifted to reduce clock feedthrough.

Here, when the circuit of FIG. 3A is used,
At all times, the bias current Ibias is N
Since the current flows through the MOS transistor 8, the capacitor 9 is charged in advance, and the amount of change in the gate voltage when the reference current Iref flows in can be small, the sampling time is shortened as compared with the circuit of FIG. be able to. In the case of the circuit of FIG. 2A, the current mirror operation cannot always be accurate depending on the relative accuracy of the pair of NMOS transistors 4 and 5, and the accuracy of the output current may be degraded. Since only one NMOS transistor is used in the circuit of FIG. 3A, the relative accuracy of the NMOS transistor does not matter, and the accuracy of the output current is not affected.

In this embodiment, since a plurality of currents equal to the reference current are output using a plurality of current sample / hold circuits, the output current is non-uniform due to the voltage drop of the wiring, which is a conventional problem. In addition to eliminating output current non-uniformity due to performance and resistance accuracy, and output current non-uniformity due to temperature characteristics of the resistor, it can be mounted compactly without requiring a wide wiring routing area.
Further, since no operational amplifier is used, the circuit scale can be reduced, and power consumption can be reduced. Further, since the current transformer circuit is used as the current sample / hold circuit, the output current value is equal to the sampled reference current even if the ambient temperature is different in each current transformer circuit, so that it does not depend on the temperature. A uniform output current can be obtained.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the current output circuit according to the present invention. 4, first, the constant current circuit 1, the current sample / hold circuits 2-1, 2-2,..., 2-n are all the same as those in FIG. The constant current circuit 1 outputs a constant reference current Iref, and the current sample / hold circuits 2-1, 2-2,.
2-n samples / holds the reference current Iref and outputs a current equal to the reference current Iref. 2A and 3A are used as the current sample / hold circuit.

In this embodiment, the D / A converters B1, B2,... BN are connected to the outputs of the current sample / hold circuits 2-1, 2-2,. Loads L (Load) 1, L2,..., LN are connected to the outputs of the A converters B1, B2,. Digital signals 1, 2,... N are supplied to the D / A converters B1, B2,..., BN, and each D / A converter converts the reference current Iref supplied from the current sample / hold circuit according to the digital signal. The load is changed and supplied to the load.

In this embodiment, for example, the SCE
(Surface Conduction Emitter) By connecting the element as a load, it can be suitably used as a drive circuit of the SCE element. That is, the reference current Iref supplied from the current sample / hold circuit is changed to a desired current value by the D / A converter in accordance with the digital signal, and the SCE is changed.
By driving the elements, a current driver circuit with uniform output current, small circuit scale, and low power consumption can be realized.

[0022]

As described above, according to the present invention, since a plurality of output currents substantially the same as the reference current are obtained by sampling / holding the reference current, the circuit scale is reduced and the power consumption is reduced. In addition, the mounting area can be reduced, the temperature dependency of the output current can be reduced, and a compact, high-performance current output circuit with less variation in output current can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a current output circuit of the present invention.

FIG. 2 is a diagram illustrating an example of a current sample / hold circuit according to the embodiment of FIG. 1 and an operation timing thereof;

3 is a diagram showing another example of the current sample / hold circuit of the embodiment of FIG. 1 and its operation timing.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional current output circuit.

6 is a circuit diagram showing a voltage-current conversion circuit of the current output circuit of FIG.

FIG. 7 is a diagram showing another conventional current output circuit.

[Explanation of symbols]

1 constant current circuit 2-1, 2-2, ..., 2-n current sample / hold circuit 4, 5, 8 NMOS transistor 6, 9 capacity 7 bias current circuit C1, C2, ..., CN load circuit B1, B2 , ..., BN D / A converter L1, L2, ..., LN load SW1-SW5 switch element

Claims (3)

[Claims] A constant current circuit that outputs a predetermined current; and a current that is connected to the constant current circuit and that outputs a current substantially the same as the current of the constant current circuit by sampling / holding the current of the constant current circuit. And a plurality of current sample / hold circuits. 2. The current output circuit according to claim 1, wherein said current sample / hold circuit comprises a current transformer circuit. 3. An output of the current sample / hold circuit is input as a reference current of a D / A converter, and an output current of the D / A converter is changed according to an input digital signal. 2. The current output circuit according to 1.