JP3533842B2 - Constant voltage circuit - Google Patents

Constant voltage circuit

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Publication number
JP3533842B2
JP3533842B2 JP23456296A JP23456296A JP3533842B2 JP 3533842 B2 JP3533842 B2 JP 3533842B2 JP 23456296 A JP23456296 A JP 23456296A JP 23456296 A JP23456296 A JP 23456296A JP 3533842 B2 JP3533842 B2 JP 3533842B2
Authority
JP
Japan
Prior art keywords
resistance element
resistance
circuit
constant voltage
amplifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23456296A
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Japanese (ja)
Other versions
JPH1078826A (en
Inventor
益英 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
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Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP23456296A priority Critical patent/JP3533842B2/en
Publication of JPH1078826A publication Critical patent/JPH1078826A/en
Application granted granted Critical
Publication of JP3533842B2 publication Critical patent/JP3533842B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、定電圧回路に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant voltage circuit.

【0002】[0002]

【従来の技術】従来の定電圧回路を、図1、図2及び図
7を用いて説明する。図1は定電圧回路を示す図であ
る。図2は図1の回路図に対応した各ブロックの配置位
置の一実施例を示したレイアウト平面図である。図7は
図2内に示した抵抗素子群207、及び抵抗素子群21
7のさらに詳細な配置位置を示した従来のレイアウト平
面図である。
2. Description of the Related Art A conventional constant voltage circuit will be described with reference to FIGS. FIG. 1 is a diagram showing a constant voltage circuit. FIG. 2 is a layout plan view showing an example of the arrangement position of each block corresponding to the circuit diagram of FIG. FIG. 7 shows the resistive element group 207 and the resistive element group 21 shown in FIG.
7 is a conventional layout plan view showing further detailed arrangement positions of FIG.

【0003】第1の増幅手段102は、出力電圧VOUT1
をA1抵抗素子108とA2抵抗素子109で分圧し、
差動増幅回路103へフィードバックをかけているので
定電圧回路として働く。よって出力電圧VOUT1は、A1
抵抗素子108の抵抗値を A2、A2抵抗素子109
抵抗値を A1とすると
The first amplifying means 102 has an output voltage VOUT1.
Is divided by the A1 resistance element 108 and the A2 resistance element 109,
Since feedback is applied to the differential amplifier circuit 103, it functions as a constant voltage circuit. Therefore, the output voltage VOUT1 is A1
When the resistance value of the resistance element 108 is R A2 and the resistance value of the A2 resistance element 109 is R A1

【0004】[0004]

【数1】 [Equation 1]

【0005】で表される。It is represented by

【0006】また第2の増幅手段112も第1の増幅手
段102と全く同じ構成なためやはり定電圧回路として
働き、出力電圧VOUT2は、B1抵抗素子118の抵抗値
B2、B2抵抗素子119の抵抗値を B1とすると
Since the second amplifying means 112 also has the same configuration as the first amplifying means 102, it also functions as a constant voltage circuit, and the output voltage VOUT2 has the resistance values of the B1 resistance element 118 as R B2 and B2 resistance element 119. Let the resistance value of R B1 be

【0007】[0007]

【数2】 [Equation 2]

【0008】で表される。It is represented by

【0009】[0009]

【発明が解決しようとする課題】しかしながら上記で説
明した従来の定電圧回路にあっては、図7に示すよう
に、第1の増幅手段に属する第1の抵抗素子708(以
下、A1抵抗素子という)、第1の増幅手段に属する第
2の抵抗素子709(以下、A2抵抗素子という)、第
2の増幅手段に属する第1の抵抗素子718(以下、B
1抵抗素子という)、及び第2の増幅手段に属する第2
の抵抗素子719(以下、B2抵抗素子という)の配置
位置が、それぞれ1つの抵抗素子で構成されているた
め、ウェハーまたはロット間での製造ばらつきにより、
各抵抗素子の抵抗値がばらつき、抵抗素子に流れる電流
がばらつくことにより定電圧回路全体の消費電流もばら
つくため、特に低消費電力が要求される小型携帯機器の
電力設計では電池の容量を大きくする等マージンを考え
て設計する必要があるという第1の問題点を有する。す
なわち、抵抗値RA1、RA2、RB1、RB2のウェハまたは
ロット間の製造ばらつきによる抵抗変動分をそれぞれΔ
RA1、ΔRA2、ΔRB1、ΔRB2とすると抵抗素子群70
8と709に流れる電流IOUT1、及び抵抗素子群71
8、719に流れる電流IOUT2は
However, in the conventional constant voltage circuit described above, as shown in FIG. 7, the first resistance element 708 (hereinafter referred to as A1 resistance element) belonging to the first amplification means is used. Second resistance element 709 belonging to the first amplifying means (hereinafter referred to as A2 resistance element) and the first resistance element 718 belonging to the second amplifying means (hereinafter referred to as B).
1 resistance element), and the second belonging to the second amplification means
Since the arrangement position of the resistance element 719 (hereinafter referred to as the B2 resistance element) is composed of one resistance element, respectively, due to manufacturing variations between wafers or lots,
Since the resistance value of each resistance element varies and the current flowing through the resistance element also varies, the current consumption of the entire constant voltage circuit also varies, so increase the battery capacity especially in the power design of small portable devices that require low power consumption. There is a first problem that it is necessary to design in consideration of an equal margin. That is, the resistance variation due to the manufacturing variation between the wafers or lots of the resistance values RA1, RA2, RB1, and RB2 is Δ.
If RA1, ΔRA2, ΔRB1, and ΔRB2, the resistance element group 70
8 and 709, the current IOUT1 flowing through the resistor element group 71
The current IOUT2 flowing through 8,719 is

【0010】[0010]

【数3】 [Equation 3]

【0011】[0011]

【数4】 [Equation 4]

【0012】と表され抵抗素子に流れる電流値がばらつ
く。
The value of the current flowing through the resistance element varies.

【0013】また、A1抵抗素子708、A2抵抗素子
709、B1抵抗素子718、及びB2抵抗素子719
は、それぞれ近くに配置されていたため、チップ内部で
の製造ばらつきにより抵抗値がばらつくという第2の問
題点を有する。すなわち、抵抗値RA1、RA2、RB1、R
B2の製造ばらつきによる抵抗変動分をそれぞれδRA
1、δRA2、δRB1、δRB2とすると出力電圧VOUT
1、VOUT2は
Also, A1 resistance element 708, A2 resistance element 709, B1 resistance element 718, and B2 resistance element 719.
Have a second problem that the resistance value varies due to manufacturing variations inside the chip. That is, the resistance values RA1, RA2, RB1, R
Resistance variation due to manufacturing variation of B2 is δRA
1, δRA2, δRB1, δRB2, the output voltage VOUT
1, VOUT2

【0014】[0014]

【数5】 [Equation 5]

【0015】[0015]

【数6】 [Equation 6]

【0016】で表され出力電圧VOUT1、VOUT2間で電圧
値がばらつく。よって望む特性を得るためには、出力電
圧値を調整するために各定電圧回路毎に端子やヒューズ
回路等を設ける必要がありチップ面積が大きくなる。
The voltage value varies between the output voltages VOUT1 and VOUT2. Therefore, in order to obtain the desired characteristics, it is necessary to provide a terminal, a fuse circuit, or the like for each constant voltage circuit in order to adjust the output voltage value, which increases the chip area.

【0017】そこで本発明はこのような問題点を解決す
るもので、その目的とするところはウェハーまたはロッ
ト間での製造ばらつきにより、各ウェハーまたはロット
間での定電圧回路の消費電流のばらつきを抑えるところ
にある。本発明のさらなる目的は、チップ内部での製造
ばらつきに依存せず、各定電圧回路間での出力電圧の相
対値が一定の定電圧回路を提供するところにある。
Therefore, the present invention solves such a problem, and an object of the present invention is to reduce variations in current consumption of a constant voltage circuit between wafers or lots due to variations in manufacturing between wafers or lots. There is a place to hold down. A further object of the present invention is to provide a constant voltage circuit in which the relative value of the output voltage between the constant voltage circuits is constant, without depending on manufacturing variations inside the chip.

【0018】[0018]

【0019】[0019]

【0020】[0020]

【課題を解決するための手段】請求項1 記載の発明は、
基準電圧発生手段と、該基準電圧発生手段で生成された
基準電圧を入力とし、該基準電圧の電圧値の実数倍を出
力する第1の増幅手段と第2の増幅手段とから構成さ
れ、各該増幅手段は、差動増幅回路と、該差動増幅回路
の出力信号を入力とする出力増幅回路と、該差動増幅回
路の出力と該出力増幅回路間に設けた容量素子から構成
され、該出力増幅回路は、該差動増幅回路の出力信号を
入力信号として受ける能動素子と、該能動素子と直列接
続された該第1の抵抗素子と第2の抵抗素子から構成さ
れ、該第1の抵抗素子と該第2の抵抗素子との接続点を
該差動増幅回路へ負帰還かけた定電圧回路において、各
該増幅手段の該第1の抵抗素子及び該第2の抵抗素子を
第1の方向へそれぞれ少なくとも2つ以上に分割し、該
第1の方向へ該第1の増幅手段に属する該第1の抵抗素
子と該第2の増幅手段に属する該第1の抵抗素子を交互
に配置し、該第1の増幅手段に属する該第2の抵抗素子
と該第2の増幅手段に属する該第2の抵抗素子を交互に
配置したことを特徴とする。
The invention according to claim 1 is
It comprises a reference voltage generating means, a first amplifying means and a second amplifying means which receive the reference voltage generated by the reference voltage generating means as an input and output a real multiple of the voltage value of the reference voltage. The amplifying means includes a differential amplifying circuit, an output amplifying circuit that receives an output signal of the differential amplifying circuit, and a capacitive element provided between the output of the differential amplifying circuit and the output amplifying circuit. The output amplifier circuit includes an active element that receives an output signal of the differential amplifier circuit as an input signal, the first resistance element and a second resistance element that are connected in series with the active element, and the first resistance element and the second resistance element. In a constant voltage circuit in which a connection point between the resistance element and the second resistance element is negatively fed back to the differential amplifier circuit, the first resistance element and the second resistance element of each amplification unit are At least two or more in each of the first direction and the first direction in the first direction. The first resistance element belonging to the amplifying means and the first resistance element belonging to the second amplifying means are alternately arranged, and the second resistance element belonging to the first amplifying means and the second resistance element belonging to the second amplifying means. The second resistance elements belonging to the amplification means are alternately arranged.

【0021】請求項2記載の発明は、請求項1に記載の
定電圧回路であって、前記第1の抵抗素子及び前記第2
の抵抗素子は、前記第1の方向とは略直交する第2の方
向へ少なくとも2つ以上に分割したことを特徴とする。
The invention according to claim 2 is the constant voltage circuit according to claim 1 , wherein the first resistance element and the second resistance element are provided.
The resistance element is divided into at least two or more elements in a second direction substantially orthogonal to the first direction.

【0022】[0022]

【発明の実施の形態】以下本発明による実施例を説明す
る。請求項1に記載の発明を図1、図2、及び図3を用
いて説明する。図1は増幅手段が2つの場合の定電圧回
路を示す回路図である。基準電圧発生手段101は、第
1の増幅手段102と第2の増幅手段112へ基準電圧
VREFを供給している。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. The invention according to claim 1 will be described with reference to FIGS. 1, 2, and 3. FIG. 1 is a circuit diagram showing a constant voltage circuit when there are two amplifying means. The reference voltage generating means 101 supplies the reference voltage VREF to the first amplifying means 102 and the second amplifying means 112.

【0023】第1の増幅手段102は、作動増幅回路1
03、出力増幅回路104、及び位相補償用の容量素子
105から構成されている。出力増幅回路104はPc
hトランジスタ106と抵抗素子群107とから構成さ
れ、さらに抵抗素子群107は、A1抵抗素子108
と、A2抵抗素子109から構成されている。
The first amplifying means 102 is the operational amplifier circuit 1
03, an output amplifier circuit 104, and a capacitive element 105 for phase compensation. The output amplifier circuit 104 is Pc
It is composed of an h transistor 106 and a resistance element group 107, and the resistance element group 107 further includes an A1 resistance element 108.
And an A2 resistance element 109.

【0024】第2の増幅手段112は、作動増幅回路1
13、出力増幅回路114、及び位相補償用の容量素子
115から構成されている。出力増幅回路114はPc
hトランジスタ116と抵抗素子群117とから構成さ
れ、さらに抵抗素子群117は、B1抵抗素子118
と、B2抵抗素子119から構成されている。
The second amplifying means 112 is the operation amplifying circuit 1
13, an output amplifier circuit 114, and a capacitive element 115 for phase compensation. The output amplifier circuit 114 is Pc
The h-transistor 116 and the resistance element group 117 are included, and the resistance element group 117 includes the B1 resistance element 118.
And a B2 resistance element 119.

【0025】図2は、図1の回路図に対応した各ブロッ
クの配置場所の一実施例を示したレイアウト平面図であ
る。図2内の201は、図1の基準電圧発生手段101
に対応している。同様に他のブロックも図1と対応して
おり、202は第1の増幅手段102、212は第2の
増幅手段112、203と213は作動増幅回路103
と113、204と214は出力増幅回路104と11
4、205と215は容量素子105と115、206
と216はPchトランジスタ106と116、207
と217は抵抗素子群107と117、がそれぞれ対応
している。
FIG. 2 is a layout plan view showing an embodiment of the location of each block corresponding to the circuit diagram of FIG. Reference numeral 201 in FIG. 2 denotes the reference voltage generating means 101 in FIG.
It corresponds to. Similarly, the other blocks correspond to those in FIG. 1, in which 202 is the first amplification means 102, 212 is the second amplification means 112, and 203 and 213 are the operation amplification circuits 103.
And 113, 204 and 214 are output amplifier circuits 104 and 11
4, 205 and 215 are capacitive elements 105, 115 and 206.
And 216 are Pch transistors 106, 116 and 207.
And 217 correspond to the resistance element groups 107 and 117, respectively.

【0026】図3は、抵抗素子の配置場所を示した図で
ある。307は抵抗素子群であり、図1内では抵抗素子
群107と117に対応し、図2内では抵抗素子群20
7と217に対応している。308は図1内のA1抵抗
素子108に対応し、以下同様に309はA2抵抗素子
109、318はB1抵抗素子118、319はB2抵
抗素子119にそれぞれ対応している。321は第1の
配線手段、323は抵抗素子と第1の配線手段321を
電気的に接続しているコンタクトをあらわしている。
FIG. 3 is a diagram showing the location of the resistive element. Reference numeral 307 denotes a resistance element group, which corresponds to the resistance element groups 107 and 117 in FIG. 1 and the resistance element group 20 in FIG.
It corresponds to 7 and 217. Reference numeral 308 corresponds to the A1 resistance element 108 in FIG. 1, and hereinafter 309 corresponds to the A2 resistance element 109, 318 corresponds to the B1 resistance element 118, and 319 corresponds to the B2 resistance element 119, respectively. Reference numeral 321 represents a first wiring means, 323 represents a contact electrically connecting the resistance element and the first wiring means 321.

【0027】また図3は図7内において第1の方向へA
1抵抗素子708、B1抵抗素子718を4分割、A2
抵抗素子709、B2抵抗素719を8分割した実施例
である。
Further, FIG. 3 shows A in the first direction in FIG.
1 resistance element 708, B1 resistance element 718 divided into four, A2
In this embodiment, the resistance element 709 and the B2 resistance element 719 are divided into eight.

【0028】一般に平均値μ、標準偏差σで正規分布に
ばらつく母集団からランダムにおおきさnのサンプリン
グをした場合、そのサンプルの平均値の分布は、やはり
正規分布で平均値μ、標準偏差σ/√nとなる。
In general, when a sample of random numbers n is randomly sampled from a population that has a normal distribution with an average value μ and a standard deviation σ, the distribution of the average values of the samples is also a normal distribution, and the average value μ and the standard deviation σ are / √n.

【0029】よって、ロット間またはウェハー間のばら
つきは正規分布にばらつくため各抵抗素子をn分割する
と、抵抗素子の平均値の標準偏差が1/√nとなるため
ばらつきが抑えられる。例えば各抵抗素子をn分割した
とすると、抵抗素子308と309に流れる電流IOUT3
1、及び抵抗素子318、319に流れる電流IOUT32
は、式(3)及び式(4)の抵抗変動分ΔRA1とΔRB1
へ1/√n1、抵抗変動分ΔRA2とΔRB2へ1/√n2を
それぞれ乗じて次式を得る。
Therefore, since the variation between lots or wafers varies in a normal distribution, when each resistance element is divided into n, the standard deviation of the average value of the resistance elements becomes 1 / √n, and the variation is suppressed. For example, if each resistance element is divided into n, the current IOUT3 flowing through the resistance elements 308 and 309
1 and the current IOUT32 flowing through the resistance elements 318 and 319
Is the resistance fluctuations ΔRA1 and ΔRB1 in the equations (3) and (4).
1 / √n1 and resistance fluctuations ΔRA2 and ΔRB2 are respectively multiplied by 1 / √n2 to obtain the following equation.

【0030】[0030]

【数7】 [Equation 7]

【0031】[0031]

【数8】 [Equation 8]

【0032】従って、図3に示した実施例では、A1抵
抗素子308とB1抵抗素子318は1/√4=0.
5、A2抵抗素子309とB2抵抗素子319は1/√
8≒0.35だけばらつきを抑えることができる。
Therefore, in the embodiment shown in FIG. 3, the A1 resistance element 308 and the B1 resistance element 318 are 1 / √4 = 0.
5, A2 resistance element 309 and B2 resistance element 319 are 1 / √
The variation can be suppressed by 8≈0.35.

【0033】次に請求項2に記載の発明を図1、図2、
及び図4を用いて説明する。図1、図2は既に説明した
通りである。
Next, the invention described in claim 2 will be described with reference to FIGS.
And FIG. 4 will be described. 1 and 2 have already been described.

【0034】図4は、抵抗素子の配置場所を示した図で
ある。407は抵抗素子群であり、図1内では抵抗素子
群107と117に対応し、図2内では抵抗素子群20
7と217に対応している。408は図1内のA1抵抗
素子108に対応し、以下同様に409はA2抵抗素子
109、418はB1抵抗素子118、419はB2抵
抗素子119にそれぞれ対応している。421は第1の
配線手段、423は抵抗素子と第1の配線手段421を
電気的に接続しているコンタクトをあらわしている。
FIG. 4 is a diagram showing the location of the resistance element. Reference numeral 407 denotes a resistance element group, which corresponds to the resistance element groups 107 and 117 in FIG. 1 and the resistance element group 20 in FIG.
It corresponds to 7 and 217. Reference numeral 408 corresponds to the A1 resistance element 108 in FIG. 1, and similarly 409 corresponds to the A2 resistance elements 109, 418 to the B1 resistance elements 118 and 419 to the B2 resistance element 119, respectively. 421 is a first wiring means, 423 is a contact electrically connecting the resistance element and the first wiring means 421.

【0035】また図4は図3内のA1抵抗素子308、
A2抵抗素子309、B1抵抗素子318、及びB2抵
抗素319を、第2の方向へそれぞれ更に2分割した実
施例である。第2の方向は、第1の方向とは異なる方向
であって、たとえば、互いに略直交している。よって従
来の例と比較し、結果的に A1抵抗素子408、B1
抵抗素子418は8分割、A2抵抗素子409とB2抵
抗素419は16分割したことになり、よりいっそう抵
抗値のばらつきを抑えることができる。
FIG. 4 shows the A1 resistance element 308 in FIG.
This is an example in which the A2 resistance element 309, the B1 resistance element 318, and the B2 resistance element 319 are each further divided into two in the second direction. The second direction is a direction different from the first direction and is, for example, substantially orthogonal to each other. Therefore, compared with the conventional example, as a result, A1 resistance elements 408, B1
The resistance element 418 is divided into eight parts, and the A2 resistance element 409 and the B2 resistance element 419 are divided into sixteen parts, so that the variation in the resistance value can be further suppressed.

【0036】次に請求項3に記載の発明を図1、図2、
及び図5を用いて説明する。図1、図2は既に説明した
通りである。
Next, the invention described in claim 3 will be described with reference to FIGS.
And FIG. 5 will be described. 1 and 2 have already been described.

【0037】図5は、抵抗素子の配置場所を示した図で
ある。507は抵抗素子群であり、図1内では抵抗素子
群107と117に対応し、図2内では抵抗素子群20
7と217に対応している。508は図1内のA1抵抗
素子108に対応し、以下同様に509はA2抵抗素子
109、518はB1抵抗素子118、519はB2抵
抗素子119にそれぞれ対応している。521は第1の
配線手段、522は第2の配線手段、523は抵抗素子
と第1の配線手段521を電気的に接続しているコンタ
クト、523は配線手段521と配線手段522を電気
的に接続しているスルーホールをあらわしている。
FIG. 5 is a diagram showing the location of the resistive element. Reference numeral 507 denotes a resistance element group, which corresponds to the resistance element groups 107 and 117 in FIG. 1 and the resistance element group 20 in FIG.
It corresponds to 7 and 217. Reference numeral 508 corresponds to the A1 resistance element 108 in FIG. 1, and hereinafter 509 corresponds to the A2 resistance elements 109, 518, B1 resistance elements 118 and 519, respectively. 521 is a first wiring means, 522 is a second wiring means, 523 is a contact for electrically connecting the resistance element and the first wiring means 521, 523 is an electrical connection between the wiring means 521 and the wiring means 522. Represents a connected through hole.

【0038】また図5は第1の方向へA1抵抗素子50
8とB1抵抗素子518を2分割し、A2抵抗素子50
9とB2抵抗素子519を4分割し、さらに、A1抵抗
素子508とB1抵抗素子518、及びA2抵抗素子5
09とB2抵抗素子519を交互に配置した実施例であ
る。
Further, FIG. 5 shows the A1 resistance element 50 in the first direction.
8 and B1 resistance element 518 are divided into two, and A2 resistance element 50
9 and B2 resistance element 519 are divided into four, and further, A1 resistance element 508, B1 resistance element 518, and A2 resistance element 5
In this embodiment, 09 and B2 resistance elements 519 are alternately arranged.

【0039】分割したことによる効果は、請求項1及び
請求項2の実施例で説明した通りである。
The effect of the division is as described in the embodiments of claims 1 and 2.

【0040】図5に示す通りA1抵抗素子508とB1
抵抗素子518、及びA2抵抗素子509とB2抵抗素
子519を交互に配置してあるので製造ばらつきによる
抵抗変動分は
As shown in FIG. 5, A1 resistance elements 508 and B1
Since the resistance element 518 and the A2 resistance element 509 and the B2 resistance element 519 are arranged alternately,

【0041】[0041]

【数9】 [Equation 9]

【0042】となり、よって式(9)を、式(5)及び
式(6)へ代入して次式を得る。
Therefore, the equation (9) is substituted into the equations (5) and (6) to obtain the following equation.

【0043】[0043]

【数10】 [Equation 10]

【0044】[0044]

【数11】 [Equation 11]

【0045】例えば、各抵抗素子群の抵抗値が等しい場
合、すなわち
For example, when the resistance values of the resistance element groups are equal, that is,

【0046】[0046]

【数12】 [Equation 12]

【0047】とすると、出力電圧VOUT1、VOUT2は、式
(9)を式(10)及び式(11)へ代入して、
Then, the output voltages VOUT1 and VOUT2 are obtained by substituting the equation (9) into the equations (10) and (11).

【0048】[0048]

【数13】 [Equation 13]

【0049】となり、製造ばらつきによる抵抗変動分が
帳消しされて出力電圧VOUT1、VOUT2は等しくなる。ま
た出力電圧VOUT1とVOUT2が異なる電圧を出力する定電
圧回路の場合でも同様に抵抗変動分が帳消しされ、各出
力電圧の相対値が一定となる。
The resistance variation due to manufacturing variations is canceled out, and the output voltages VOUT1 and VOUT2 become equal. Also in the case of a constant voltage circuit that outputs different voltages for the output voltages VOUT1 and VOUT2, the resistance variation is canceled out in the same manner, and the relative value of each output voltage becomes constant.

【0050】次に請求項4に記載の発明を図1、図2、
及び図6を用いて説明する。図1、図2は既に説明した
通りである。
Next, the invention described in claim 4 will be described with reference to FIGS.
And FIG. 6 will be described. 1 and 2 have already been described.

【0051】図6は、抵抗素子の配置場所を示した図で
ある。607は抵抗素子群であり、図1内では抵抗素子
群107と117に対応し、図2内では抵抗素子群20
7と217に対応している。608は図1内のA1抵抗
素子108に対応し、以下同様に609はA2抵抗素子
109、618はB1抵抗素子118、619はB2抵
抗素子119にそれぞれ対応している。621は第1の
配線手段、622は第2の配線手段、623は抵抗素子
と第1の配線手段621を電気的に接続しているコンタ
クトをあらわしている。
FIG. 6 is a diagram showing the location of the resistive element. Reference numeral 607 denotes a resistance element group, which corresponds to the resistance element groups 107 and 117 in FIG. 1 and the resistance element group 20 in FIG.
It corresponds to 7 and 217. Reference numeral 608 corresponds to the A1 resistance element 108 in FIG. 1, and hereinafter 609 corresponds to the A2 resistance element 109, 618 corresponds to the B1 resistance element 118, and 619 corresponds to the B2 resistance element 119, respectively. 621 is a first wiring means, 622 is a second wiring means, and 623 is a contact which electrically connects the resistance element and the first wiring means 621.

【0052】また図6は図5内のA1抵抗素子508、
A2抵抗素子509、B1抵抗素子518、及びB2抵
抗素519を、第2の方向へそれぞれ更に2分割した実
施例である。第2の方向は、第1の方向とは異なり、た
とえば略直交している。よって請求項3の実施例で示し
た図5と比較し、さらにばらつきを約0.71へ抑える
ことができる。
FIG. 6 shows the A1 resistance element 508 in FIG.
This is an example in which the A2 resistance element 509, the B1 resistance element 518, and the B2 resistance element 519 are each further divided into two in the second direction. The second direction is different from the first direction and is, for example, substantially orthogonal. Therefore, compared with FIG. 5 shown in the embodiment of claim 3, the variation can be further suppressed to about 0.71.

【0053】図8は抵抗素子がポリシリコン抵抗の場合
の断面図である。821は第1の配線手段、822は第
2の配線手段、823はコンタクトスルーホール、82
4はスルーホール、825は該抵抗素子となるポリシリ
コン、826は層間絶縁膜、、827は基板をそれぞれ
あらわしている。他の抵抗素子としては、ウェル抵抗、
拡散抵抗、MOS抵抗、ポリシリコンダイオード抵抗等
が考えられる。
FIG. 8 is a sectional view when the resistance element is a polysilicon resistance. 821 is a first wiring means, 822 is a second wiring means, 823 is a contact through hole, 82
Reference numeral 4 is a through hole, 825 is polysilicon serving as the resistance element, 826 is an interlayer insulating film, and 827 is a substrate. Other resistance elements include well resistance,
Diffusion resistance, MOS resistance, polysilicon diode resistance, etc. can be considered.

【0054】[0054]

【発明の効果】以上説明したように本発明によれば、抵
抗素子を分割したことによって、ウェハーまたはロット
間での製造ばらつきにより、各ウェハーまたはロット間
での定電圧回路の消費電流のばらつきを抑えることがで
きるため、特に低消費電力が要求される小型携帯機器の
設計段階で必要以上の電力マージンを考える必要がなく
なり、搭載する電池の容量も小型化が可能となる。
As described above, according to the present invention, by dividing the resistance element, the variation in the current consumption of the constant voltage circuit between the wafers or lots is caused by the variation in the manufacturing between wafers or lots. Since the power consumption can be suppressed, it is not necessary to consider an unnecessary power margin at the design stage of a small portable device that requires low power consumption, and the capacity of a battery to be mounted can be reduced.

【0055】また本発明によれば、抵抗素子を交互に配
置したことによって、チップ内部で製造ばらつきが存在
しても各定電圧回路間での出力電圧の相対値が一定の定
電圧回路を提供できるため、出力電圧値を調整するため
の端子やヒューズ回路等は一組ですみチップ面積の増大
を防ぐことができる。
Further, according to the present invention, by arranging the resistance elements alternately, a constant voltage circuit in which the relative value of the output voltage between the constant voltage circuits is constant is provided even if manufacturing variations exist in the chip. Therefore, a set of terminals for adjusting the output voltage value, a fuse circuit, and the like can be provided, and an increase in the chip area can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】定電圧回路を示す回路図。FIG. 1 is a circuit diagram showing a constant voltage circuit.

【図2】図1の回路図に対応した各ブロックの配置位置
の一実施例を示したレイアウト平面図。
FIG. 2 is a layout plan view showing an example of an arrangement position of each block corresponding to the circuit diagram of FIG.

【図3】請求項1に記載の発明の一実施例を示した抵抗
素子郡のレイアウト平面図。
FIG. 3 is a layout plan view of a resistance element group showing an embodiment of the invention described in claim 1;

【図4】請求項2に記載の発明の一実施例を示した抵抗
素子郡のレイアウト平面図。
FIG. 4 is a layout plan view of a group of resistance elements showing an embodiment of the invention described in claim 2;

【図5】請求項3に記載の発明の一実施例を示した抵抗
素子郡のレイアウト平面図。
FIG. 5 is a layout plan view of a group of resistance elements showing an embodiment of the invention described in claim 3;

【図6】請求項4に記載の発明の一実施例を示した抵抗
素子郡のレイアウト平面図。
FIG. 6 is a layout plan view of a group of resistance elements showing an embodiment of the invention described in claim 4;

【図7】従来例を示した抵抗素子郡のレイアウト平面
図。
FIG. 7 is a layout plan view of a resistance element group showing a conventional example.

【図8】抵抗素子がポリシリコンの場合の断面図。FIG. 8 is a cross-sectional view when the resistance element is polysilicon.

【符号の説明】[Explanation of symbols]

101、201・・・基準電圧発生手段 102、202・・・第1の増幅手段 112、212・・・第2の増幅手段 103、113、203、213・・・差動増幅回路 104、114、204、214・・・出力増幅回路 105、115 205、215・・・容量素子 106、116、206、216・・・Pchトランジ
スタ 107、117、207、217、307、407、5
07、607、707・・・抵抗素子郡 108、308、408、508、608、708・・
・第1の増幅手段に属する第1の抵抗素子 109、309、409、509、609、709・・
・第1の増幅手段に属する第2の抵抗素子 118、318、418、518、618、718・・
・第2の増幅手段に属する第1の抵抗素子 119、319、419、519、619、719・・
・第2の増幅手段に属する第2の抵抗素子 321、421、521、621、721、821・・
・第1の配線手段 322、522、822・・・第2の配線手段 323、423、523、623、723、823・・
・コンタクト 324、524、824・・・スルーホール 825・・・ポリシリコン抵抗 826・・・層間絶縁膜 827・・・基板
101, 201 ... Reference voltage generating means 102, 202 ... First amplifying means 112, 212 ... Second amplifying means 103, 113, 203, 213 ... Differential amplifying circuits 104, 114, 204, 214 ... Output amplifier circuits 105, 115 205, 215 ... Capacitance elements 106, 116, 206, 216 ... Pch transistors 107, 117, 207, 217, 307, 407, 5
07, 607, 707 ... Resistance element groups 108, 308, 408, 508, 608, 708 ...
First resistance elements 109, 309, 409, 509, 609, 709 belonging to the first amplification means
The second resistance elements 118, 318, 418, 518, 618, 718 belonging to the first amplification means
First resistance element 119, 319, 419, 519, 619, 719 belonging to the second amplification means
-Second resistance elements 321, 421, 521, 621, 721, 821 belonging to the second amplification means.
First wiring means 322, 522, 822 ... Second wiring means 323, 423, 523, 623, 723, 823 ...
Contact 324, 524, 824 ... Through hole 825 ... Polysilicon resistance 826 ... Interlayer insulating film 827 ... Substrate

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) G05F 1/00 - 1/70 H01L 27/04 H03F 3/45 ─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. 7 , DB name) G05F 1/00-1/70 H01L 27/04 H03F 3/45

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】基準電圧発生手段と、 該基準電圧発生手段で生成された基準電圧を入力とし、
該基準電圧の電圧値の実数倍を出力する第1の増幅手段
と第2の増幅手段とから構成され、 各該増幅手段は、差動増幅回路と、 該差動増幅回路の出力信号を入力とする出力増幅回路
と、 該差動増幅回路の出力と該出力増幅回路間に設けた容量
素子から構成され、 該出力増幅回路は、該差動増幅回路の出力信号を入力信
号として受ける能動素子と、 該能動素子と直列接続された該第1の抵抗素子と第2の
抵抗素子から構成され、該第1の抵抗素子と該第2の抵
抗素子との接続点を該差動増幅回路へ負帰還かけた定電
圧回路において、 各該増幅手段の該第1の抵抗素子及び該第2の抵抗素子
を第1の方向へそれぞれ少なくとも2つ以上に分割し、 該第1の方向へ該第1の増幅手段に属する該第1の抵抗
素子と該第2の増幅手段に属する該第1の抵抗素子を交
互に配置し、 該第1の増幅手段に属する該第2の抵抗素子と該第2の
増幅手段に属する該第2の抵抗素子を交互に配置したこ
とを特徴とする定電圧回路。
1. A reference voltage generating means, and a reference voltage generated by the reference voltage generating means as an input,
It is composed of first amplifying means and second amplifying means for outputting a real multiple of the voltage value of the reference voltage, and each amplifying means receives a differential amplifying circuit and an output signal of the differential amplifying circuit. And an output element of the differential amplifier circuit and a capacitive element provided between the output amplifier circuit, the active element receiving the output signal of the differential amplifier circuit as an input signal. And a first resistance element and a second resistance element connected in series with the active element, and connecting the connection point of the first resistance element and the second resistance element to the differential amplifier circuit. In the negative feedback constant voltage circuit, each of the first resistance element and the second resistance element of each amplification means is divided into at least two or more in the first direction, and the first resistance element and the second resistance element are divided into at least two in the first direction. The first resistance element belonging to one amplification means and the first resistance element belonging to the second amplification means. Constant voltage, wherein the second resistance elements belonging to the first amplifying means and the second resistance elements belonging to the second amplifying means are arranged alternately. circuit.
【請求項2】請求項1に記載の定電圧回路であって、前
記第1の抵抗素子及び前記第2の抵抗素子は、前記第1
の方向とは略直交する第2の方向へ少なくとも2つ以上
に分割したことを特徴とする定電圧回路。
2. The constant voltage circuit according to claim 1, wherein the first resistance element and the second resistance element are the first resistance element and the second resistance element.
The constant voltage circuit is characterized by being divided into at least two or more parts in a second direction substantially orthogonal to the direction of.
JP23456296A 1996-09-04 1996-09-04 Constant voltage circuit Expired - Fee Related JP3533842B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23456296A JP3533842B2 (en) 1996-09-04 1996-09-04 Constant voltage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23456296A JP3533842B2 (en) 1996-09-04 1996-09-04 Constant voltage circuit

Publications (2)

Publication Number Publication Date
JPH1078826A JPH1078826A (en) 1998-03-24
JP3533842B2 true JP3533842B2 (en) 2004-05-31

Family

ID=16972967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23456296A Expired - Fee Related JP3533842B2 (en) 1996-09-04 1996-09-04 Constant voltage circuit

Country Status (1)

Country Link
JP (1) JP3533842B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002246545A (en) * 2001-02-21 2002-08-30 Matsushita Electric Ind Co Ltd Semiconductor device
JP3851303B2 (en) 2003-09-08 2006-11-29 ローム株式会社 Multi-output type power supply device and portable device using the same
JP4805643B2 (en) 2005-09-21 2011-11-02 株式会社リコー Constant voltage circuit
JP4841220B2 (en) 2005-10-14 2011-12-21 株式会社リコー Semiconductor device
KR100902084B1 (en) * 2007-06-15 2009-06-10 (주)태진기술 Voltage regulator and fabrication method thereof

Also Published As

Publication number Publication date
JPH1078826A (en) 1998-03-24

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